ARMBaseRegisterInfo.cpp revision f6d7df6f21abcf15cfa10a6ac7fbb2f7c959093d 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42namespace llvm {
43static cl::opt<bool>
44ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
45          cl::desc("Force use of virtual base registers for stack load/store"));
46static cl::opt<bool>
47EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
48          cl::desc("Enable pre-regalloc stack frame index allocation"));
49}
50
51using namespace llvm;
52
53static cl::opt<bool>
54EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57
58ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
59                                         const ARMSubtarget &sti)
60  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
61    TII(tii), STI(sti),
62    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
63    BasePtr(ARM::R6) {
64}
65
66const unsigned*
67ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
68  static const unsigned CalleeSavedRegs[] = {
69    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
70    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
71
72    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
73    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
74    0
75  };
76
77  static const unsigned DarwinCalleeSavedRegs[] = {
78    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
79    // register.
80    ARM::LR, ARM::R11, ARM::R10, ARM::R8,
81    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
82
83    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
84    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
85    0
86  };
87  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
88}
89
90BitVector ARMBaseRegisterInfo::
91getReservedRegs(const MachineFunction &MF) const {
92  // FIXME: avoid re-calculating this everytime.
93  BitVector Reserved(getNumRegs());
94  Reserved.set(ARM::SP);
95  Reserved.set(ARM::PC);
96  Reserved.set(ARM::FPSCR);
97  if (hasFP(MF))
98    Reserved.set(FramePtr);
99  if (hasBasePointer(MF))
100    Reserved.set(BasePtr);
101  // Some targets reserve R9.
102  if (STI.isR9Reserved())
103    Reserved.set(ARM::R9);
104  return Reserved;
105}
106
107bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
108                                        unsigned Reg) const {
109  switch (Reg) {
110  default: break;
111  case ARM::SP:
112  case ARM::PC:
113    return true;
114  case ARM::R6:
115    if (hasBasePointer(MF))
116      return true;
117    break;
118  case ARM::R7:
119  case ARM::R11:
120    if (FramePtr == Reg && hasFP(MF))
121      return true;
122    break;
123  case ARM::R9:
124    return STI.isR9Reserved();
125  }
126
127  return false;
128}
129
130const TargetRegisterClass *
131ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
132                                              const TargetRegisterClass *B,
133                                              unsigned SubIdx) const {
134  switch (SubIdx) {
135  default: return 0;
136  case ARM::ssub_0:
137  case ARM::ssub_1:
138  case ARM::ssub_2:
139  case ARM::ssub_3: {
140    // S sub-registers.
141    if (A->getSize() == 8) {
142      if (B == &ARM::SPR_8RegClass)
143        return &ARM::DPR_8RegClass;
144      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
145      if (A == &ARM::DPR_8RegClass)
146        return A;
147      return &ARM::DPR_VFP2RegClass;
148    }
149
150    if (A->getSize() == 16) {
151      if (B == &ARM::SPR_8RegClass)
152        return &ARM::QPR_8RegClass;
153      return &ARM::QPR_VFP2RegClass;
154    }
155
156    if (A->getSize() == 32) {
157      if (B == &ARM::SPR_8RegClass)
158        return 0;  // Do not allow coalescing!
159      return &ARM::QQPR_VFP2RegClass;
160    }
161
162    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
163    return 0;  // Do not allow coalescing!
164  }
165  case ARM::dsub_0:
166  case ARM::dsub_1:
167  case ARM::dsub_2:
168  case ARM::dsub_3: {
169    // D sub-registers.
170    if (A->getSize() == 16) {
171      if (B == &ARM::DPR_VFP2RegClass)
172        return &ARM::QPR_VFP2RegClass;
173      if (B == &ARM::DPR_8RegClass)
174        return 0;  // Do not allow coalescing!
175      return A;
176    }
177
178    if (A->getSize() == 32) {
179      if (B == &ARM::DPR_VFP2RegClass)
180        return &ARM::QQPR_VFP2RegClass;
181      if (B == &ARM::DPR_8RegClass)
182        return 0;  // Do not allow coalescing!
183      return A;
184    }
185
186    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
187    if (B != &ARM::DPRRegClass)
188      return 0;  // Do not allow coalescing!
189    return A;
190  }
191  case ARM::dsub_4:
192  case ARM::dsub_5:
193  case ARM::dsub_6:
194  case ARM::dsub_7: {
195    // D sub-registers of QQQQ registers.
196    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
197      return A;
198    return 0;  // Do not allow coalescing!
199  }
200
201  case ARM::qsub_0:
202  case ARM::qsub_1: {
203    // Q sub-registers.
204    if (A->getSize() == 32) {
205      if (B == &ARM::QPR_VFP2RegClass)
206        return &ARM::QQPR_VFP2RegClass;
207      if (B == &ARM::QPR_8RegClass)
208        return 0;  // Do not allow coalescing!
209      return A;
210    }
211
212    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
213    if (B == &ARM::QPRRegClass)
214      return A;
215    return 0;  // Do not allow coalescing!
216  }
217  case ARM::qsub_2:
218  case ARM::qsub_3: {
219    // Q sub-registers of QQQQ registers.
220    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
221      return A;
222    return 0;  // Do not allow coalescing!
223  }
224  }
225  return 0;
226}
227
228bool
229ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
230                                          SmallVectorImpl<unsigned> &SubIndices,
231                                          unsigned &NewSubIdx) const {
232
233  unsigned Size = RC->getSize() * 8;
234  if (Size < 6)
235    return 0;
236
237  NewSubIdx = 0;  // Whole register.
238  unsigned NumRegs = SubIndices.size();
239  if (NumRegs == 8) {
240    // 8 D registers -> 1 QQQQ register.
241    return (Size == 512 &&
242            SubIndices[0] == ARM::dsub_0 &&
243            SubIndices[1] == ARM::dsub_1 &&
244            SubIndices[2] == ARM::dsub_2 &&
245            SubIndices[3] == ARM::dsub_3 &&
246            SubIndices[4] == ARM::dsub_4 &&
247            SubIndices[5] == ARM::dsub_5 &&
248            SubIndices[6] == ARM::dsub_6 &&
249            SubIndices[7] == ARM::dsub_7);
250  } else if (NumRegs == 4) {
251    if (SubIndices[0] == ARM::qsub_0) {
252      // 4 Q registers -> 1 QQQQ register.
253      return (Size == 512 &&
254              SubIndices[1] == ARM::qsub_1 &&
255              SubIndices[2] == ARM::qsub_2 &&
256              SubIndices[3] == ARM::qsub_3);
257    } else if (SubIndices[0] == ARM::dsub_0) {
258      // 4 D registers -> 1 QQ register.
259      if (Size >= 256 &&
260          SubIndices[1] == ARM::dsub_1 &&
261          SubIndices[2] == ARM::dsub_2 &&
262          SubIndices[3] == ARM::dsub_3) {
263        if (Size == 512)
264          NewSubIdx = ARM::qqsub_0;
265        return true;
266      }
267    } else if (SubIndices[0] == ARM::dsub_4) {
268      // 4 D registers -> 1 QQ register (2nd).
269      if (Size == 512 &&
270          SubIndices[1] == ARM::dsub_5 &&
271          SubIndices[2] == ARM::dsub_6 &&
272          SubIndices[3] == ARM::dsub_7) {
273        NewSubIdx = ARM::qqsub_1;
274        return true;
275      }
276    } else if (SubIndices[0] == ARM::ssub_0) {
277      // 4 S registers -> 1 Q register.
278      if (Size >= 128 &&
279          SubIndices[1] == ARM::ssub_1 &&
280          SubIndices[2] == ARM::ssub_2 &&
281          SubIndices[3] == ARM::ssub_3) {
282        if (Size >= 256)
283          NewSubIdx = ARM::qsub_0;
284        return true;
285      }
286    }
287  } else if (NumRegs == 2) {
288    if (SubIndices[0] == ARM::qsub_0) {
289      // 2 Q registers -> 1 QQ register.
290      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
291        if (Size == 512)
292          NewSubIdx = ARM::qqsub_0;
293        return true;
294      }
295    } else if (SubIndices[0] == ARM::qsub_2) {
296      // 2 Q registers -> 1 QQ register (2nd).
297      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
298        NewSubIdx = ARM::qqsub_1;
299        return true;
300      }
301    } else if (SubIndices[0] == ARM::dsub_0) {
302      // 2 D registers -> 1 Q register.
303      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
304        if (Size >= 256)
305          NewSubIdx = ARM::qsub_0;
306        return true;
307      }
308    } else if (SubIndices[0] == ARM::dsub_2) {
309      // 2 D registers -> 1 Q register (2nd).
310      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
311        NewSubIdx = ARM::qsub_1;
312        return true;
313      }
314    } else if (SubIndices[0] == ARM::dsub_4) {
315      // 2 D registers -> 1 Q register (3rd).
316      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
317        NewSubIdx = ARM::qsub_2;
318        return true;
319      }
320    } else if (SubIndices[0] == ARM::dsub_6) {
321      // 2 D registers -> 1 Q register (3rd).
322      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
323        NewSubIdx = ARM::qsub_3;
324        return true;
325      }
326    } else if (SubIndices[0] == ARM::ssub_0) {
327      // 2 S registers -> 1 D register.
328      if (SubIndices[1] == ARM::ssub_1) {
329        if (Size >= 128)
330          NewSubIdx = ARM::dsub_0;
331        return true;
332      }
333    } else if (SubIndices[0] == ARM::ssub_2) {
334      // 2 S registers -> 1 D register (2nd).
335      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
336        NewSubIdx = ARM::dsub_1;
337        return true;
338      }
339    }
340  }
341  return false;
342}
343
344
345const TargetRegisterClass *
346ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
347  return ARM::GPRRegisterClass;
348}
349
350/// getAllocationOrder - Returns the register allocation order for a specified
351/// register class in the form of a pair of TargetRegisterClass iterators.
352std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
353ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
354                                        unsigned HintType, unsigned HintReg,
355                                        const MachineFunction &MF) const {
356  // Alternative register allocation orders when favoring even / odd registers
357  // of register pairs.
358
359  // No FP, R9 is available.
360  static const unsigned GPREven1[] = {
361    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
362    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
363    ARM::R9, ARM::R11
364  };
365  static const unsigned GPROdd1[] = {
366    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
367    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
368    ARM::R8, ARM::R10
369  };
370
371  // FP is R7, R9 is available.
372  static const unsigned GPREven2[] = {
373    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
374    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
375    ARM::R9, ARM::R11
376  };
377  static const unsigned GPROdd2[] = {
378    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
379    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
380    ARM::R8, ARM::R10
381  };
382
383  // FP is R11, R9 is available.
384  static const unsigned GPREven3[] = {
385    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
386    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
387    ARM::R9
388  };
389  static const unsigned GPROdd3[] = {
390    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
391    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
392    ARM::R8
393  };
394
395  // No FP, R9 is not available.
396  static const unsigned GPREven4[] = {
397    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
398    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
399    ARM::R11
400  };
401  static const unsigned GPROdd4[] = {
402    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
403    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
404    ARM::R10
405  };
406
407  // FP is R7, R9 is not available.
408  static const unsigned GPREven5[] = {
409    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
410    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
411    ARM::R11
412  };
413  static const unsigned GPROdd5[] = {
414    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
415    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
416    ARM::R10
417  };
418
419  // FP is R11, R9 is not available.
420  static const unsigned GPREven6[] = {
421    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
422    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
423  };
424  static const unsigned GPROdd6[] = {
425    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
426    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
427  };
428
429
430  if (HintType == ARMRI::RegPairEven) {
431    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
432      // It's no longer possible to fulfill this hint. Return the default
433      // allocation order.
434      return std::make_pair(RC->allocation_order_begin(MF),
435                            RC->allocation_order_end(MF));
436
437    if (!hasFP(MF)) {
438      if (!STI.isR9Reserved())
439        return std::make_pair(GPREven1,
440                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
441      else
442        return std::make_pair(GPREven4,
443                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
444    } else if (FramePtr == ARM::R7) {
445      if (!STI.isR9Reserved())
446        return std::make_pair(GPREven2,
447                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
448      else
449        return std::make_pair(GPREven5,
450                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
451    } else { // FramePtr == ARM::R11
452      if (!STI.isR9Reserved())
453        return std::make_pair(GPREven3,
454                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
455      else
456        return std::make_pair(GPREven6,
457                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
458    }
459  } else if (HintType == ARMRI::RegPairOdd) {
460    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
461      // It's no longer possible to fulfill this hint. Return the default
462      // allocation order.
463      return std::make_pair(RC->allocation_order_begin(MF),
464                            RC->allocation_order_end(MF));
465
466    if (!hasFP(MF)) {
467      if (!STI.isR9Reserved())
468        return std::make_pair(GPROdd1,
469                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
470      else
471        return std::make_pair(GPROdd4,
472                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
473    } else if (FramePtr == ARM::R7) {
474      if (!STI.isR9Reserved())
475        return std::make_pair(GPROdd2,
476                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
477      else
478        return std::make_pair(GPROdd5,
479                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
480    } else { // FramePtr == ARM::R11
481      if (!STI.isR9Reserved())
482        return std::make_pair(GPROdd3,
483                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
484      else
485        return std::make_pair(GPROdd6,
486                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
487    }
488  }
489  return std::make_pair(RC->allocation_order_begin(MF),
490                        RC->allocation_order_end(MF));
491}
492
493/// ResolveRegAllocHint - Resolves the specified register allocation hint
494/// to a physical register. Returns the physical register if it is successful.
495unsigned
496ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
497                                         const MachineFunction &MF) const {
498  if (Reg == 0 || !isPhysicalRegister(Reg))
499    return 0;
500  if (Type == 0)
501    return Reg;
502  else if (Type == (unsigned)ARMRI::RegPairOdd)
503    // Odd register.
504    return getRegisterPairOdd(Reg, MF);
505  else if (Type == (unsigned)ARMRI::RegPairEven)
506    // Even register.
507    return getRegisterPairEven(Reg, MF);
508  return 0;
509}
510
511void
512ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
513                                        MachineFunction &MF) const {
514  MachineRegisterInfo *MRI = &MF.getRegInfo();
515  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
516  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
517       Hint.first == (unsigned)ARMRI::RegPairEven) &&
518      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
519    // If 'Reg' is one of the even / odd register pair and it's now changed
520    // (e.g. coalesced) into a different register. The other register of the
521    // pair allocation hint must be updated to reflect the relationship
522    // change.
523    unsigned OtherReg = Hint.second;
524    Hint = MRI->getRegAllocationHint(OtherReg);
525    if (Hint.second == Reg)
526      // Make sure the pair has not already divorced.
527      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
528  }
529}
530
531/// hasFP - Return true if the specified function should have a dedicated frame
532/// pointer register.  This is true if the function has variable sized allocas
533/// or if frame pointer elimination is disabled.
534///
535bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
536  // Mac OS X requires FP not to be clobbered for backtracing purpose.
537  if (STI.isTargetDarwin())
538    return true;
539
540  const MachineFrameInfo *MFI = MF.getFrameInfo();
541  // Always eliminate non-leaf frame pointers.
542  return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
543          needsStackRealignment(MF) ||
544          MFI->hasVarSizedObjects() ||
545          MFI->isFrameAddressTaken());
546}
547
548bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
549  const MachineFrameInfo *MFI = MF.getFrameInfo();
550  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
551
552  if (!EnableBasePointer)
553    return false;
554
555  if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
556    return true;
557
558  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
559  // negative range for ldr/str (255), and thumb1 is positive offsets only.
560  // It's going to be better to use the SP or Base Pointer instead. When there
561  // are variable sized objects, we can't reference off of the SP, so we
562  // reserve a Base Pointer.
563  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
564    // Conservatively estimate whether the negative offset from the frame
565    // pointer will be sufficient to reach. If a function has a smallish
566    // frame, it's less likely to have lots of spills and callee saved
567    // space, so it's all more likely to be within range of the frame pointer.
568    // If it's wrong, the scavenger will still enable access to work, it just
569    // won't be optimal.
570    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
571      return false;
572    return true;
573  }
574
575  return false;
576}
577
578bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
579  const MachineFrameInfo *MFI = MF.getFrameInfo();
580  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
581  // We can't realign the stack if:
582  // 1. Dynamic stack realignment is explicitly disabled,
583  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
584  // 3. There are VLAs in the function and the base pointer is disabled.
585  return (RealignStack && !AFI->isThumb1OnlyFunction() &&
586          (!MFI->hasVarSizedObjects() || EnableBasePointer));
587}
588
589bool ARMBaseRegisterInfo::
590needsStackRealignment(const MachineFunction &MF) const {
591  const MachineFrameInfo *MFI = MF.getFrameInfo();
592  const Function *F = MF.getFunction();
593  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
594  bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
595                               F->hasFnAttr(Attribute::StackAlignment));
596
597  return requiresRealignment && canRealignStack(MF);
598}
599
600bool ARMBaseRegisterInfo::
601cannotEliminateFrame(const MachineFunction &MF) const {
602  const MachineFrameInfo *MFI = MF.getFrameInfo();
603  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
604    return true;
605  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
606    || needsStackRealignment(MF);
607}
608
609/// estimateStackSize - Estimate and return the size of the frame.
610static unsigned estimateStackSize(MachineFunction &MF) {
611  const MachineFrameInfo *FFI = MF.getFrameInfo();
612  int Offset = 0;
613  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
614    int FixedOff = -FFI->getObjectOffset(i);
615    if (FixedOff > Offset) Offset = FixedOff;
616  }
617  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
618    if (FFI->isDeadObjectIndex(i))
619      continue;
620    Offset += FFI->getObjectSize(i);
621    unsigned Align = FFI->getObjectAlignment(i);
622    // Adjust to alignment boundary
623    Offset = (Offset+Align-1)/Align*Align;
624  }
625  return (unsigned)Offset;
626}
627
628/// estimateRSStackSizeLimit - Look at each instruction that references stack
629/// frames and return the stack size limit beyond which some of these
630/// instructions will require a scratch register during their expansion later.
631unsigned
632ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
633  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
634  unsigned Limit = (1 << 12) - 1;
635  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
636    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
637         I != E; ++I) {
638      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
639        if (!I->getOperand(i).isFI()) continue;
640
641        // When using ADDri to get the address of a stack object, 255 is the
642        // largest offset guaranteed to fit in the immediate offset.
643        if (I->getOpcode() == ARM::ADDri) {
644          Limit = std::min(Limit, (1U << 8) - 1);
645          break;
646        }
647
648        // Otherwise check the addressing mode.
649        switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
650        case ARMII::AddrMode3:
651        case ARMII::AddrModeT2_i8:
652          Limit = std::min(Limit, (1U << 8) - 1);
653          break;
654        case ARMII::AddrMode5:
655        case ARMII::AddrModeT2_i8s4:
656          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
657          break;
658        case ARMII::AddrModeT2_i12:
659          // i12 supports only positive offset so these will be converted to
660          // i8 opcodes. See llvm::rewriteT2FrameIndex.
661          if (hasFP(MF) && AFI->hasStackFrame())
662            Limit = std::min(Limit, (1U << 8) - 1);
663          break;
664        case ARMII::AddrMode4:
665        case ARMII::AddrMode6:
666          // Addressing modes 4 & 6 (load/store) instructions can't encode an
667          // immediate offset for stack references.
668          return 0;
669        default:
670          break;
671        }
672        break; // At most one FI per instruction
673      }
674    }
675  }
676
677  return Limit;
678}
679
680static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
681                                       const ARMBaseInstrInfo &TII) {
682  unsigned FnSize = 0;
683  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
684       MBBI != E; ++MBBI) {
685    const MachineBasicBlock &MBB = *MBBI;
686    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
687         I != E; ++I)
688      FnSize += TII.GetInstSizeInBytes(I);
689  }
690  return FnSize;
691}
692
693void
694ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
695                                                       RegScavenger *RS) const {
696  // This tells PEI to spill the FP as if it is any other callee-save register
697  // to take advantage the eliminateFrameIndex machinery. This also ensures it
698  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
699  // to combine multiple loads / stores.
700  bool CanEliminateFrame = true;
701  bool CS1Spilled = false;
702  bool LRSpilled = false;
703  unsigned NumGPRSpills = 0;
704  SmallVector<unsigned, 4> UnspilledCS1GPRs;
705  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
706  MachineFrameInfo *MFI = MF.getFrameInfo();
707
708  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
709  // scratch register.
710  // FIXME: It will be better just to find spare register here.
711  if (needsStackRealignment(MF) &&
712      AFI->isThumb2Function())
713    MF.getRegInfo().setPhysRegUsed(ARM::R4);
714
715  // Spill LR if Thumb1 function uses variable length argument lists.
716  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
717    MF.getRegInfo().setPhysRegUsed(ARM::LR);
718
719  // Spill the BasePtr if it's used.
720  if (hasBasePointer(MF))
721    MF.getRegInfo().setPhysRegUsed(BasePtr);
722
723  // Don't spill FP if the frame can be eliminated. This is determined
724  // by scanning the callee-save registers to see if any is used.
725  const unsigned *CSRegs = getCalleeSavedRegs();
726  for (unsigned i = 0; CSRegs[i]; ++i) {
727    unsigned Reg = CSRegs[i];
728    bool Spilled = false;
729    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
730      AFI->setCSRegisterIsSpilled(Reg);
731      Spilled = true;
732      CanEliminateFrame = false;
733    } else {
734      // Check alias registers too.
735      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
736        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
737          Spilled = true;
738          CanEliminateFrame = false;
739        }
740      }
741    }
742
743    if (!ARM::GPRRegisterClass->contains(Reg))
744      continue;
745
746    if (Spilled) {
747      NumGPRSpills++;
748
749      if (!STI.isTargetDarwin()) {
750        if (Reg == ARM::LR)
751          LRSpilled = true;
752        CS1Spilled = true;
753        continue;
754      }
755
756      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
757      switch (Reg) {
758      case ARM::LR:
759        LRSpilled = true;
760        // Fallthrough
761      case ARM::R4:
762      case ARM::R5:
763      case ARM::R6:
764      case ARM::R7:
765        CS1Spilled = true;
766        break;
767      default:
768        break;
769      }
770    } else {
771      UnspilledCS1GPRs.push_back(Reg);
772    }
773  }
774
775  bool ForceLRSpill = false;
776  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
777    unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
778    // Force LR to be spilled if the Thumb function size is > 2048. This enables
779    // use of BL to implement far jump. If it turns out that it's not needed
780    // then the branch fix up path will undo it.
781    if (FnSize >= (1 << 11)) {
782      CanEliminateFrame = false;
783      ForceLRSpill = true;
784    }
785  }
786
787  // If any of the stack slot references may be out of range of an immediate
788  // offset, make sure a register (or a spill slot) is available for the
789  // register scavenger. Note that if we're indexing off the frame pointer, the
790  // effective stack size is 4 bytes larger since the FP points to the stack
791  // slot of the previous FP. Also, if we have variable sized objects in the
792  // function, stack slot references will often be negative, and some of
793  // our instructions are positive-offset only, so conservatively consider
794  // that case to want a spill slot (or register) as well. Similarly, if
795  // the function adjusts the stack pointer during execution and the
796  // adjustments aren't already part of our stack size estimate, our offset
797  // calculations may be off, so be conservative.
798  // FIXME: We could add logic to be more precise about negative offsets
799  //        and which instructions will need a scratch register for them. Is it
800  //        worth the effort and added fragility?
801  bool BigStack =
802    (RS &&
803     (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
804      estimateRSStackSizeLimit(MF)))
805    || MFI->hasVarSizedObjects()
806    || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
807
808  bool ExtraCSSpill = false;
809  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
810    AFI->setHasStackFrame(true);
811
812    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
813    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
814    if (!LRSpilled && CS1Spilled) {
815      MF.getRegInfo().setPhysRegUsed(ARM::LR);
816      AFI->setCSRegisterIsSpilled(ARM::LR);
817      NumGPRSpills++;
818      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
819                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
820      ForceLRSpill = false;
821      ExtraCSSpill = true;
822    }
823
824    if (hasFP(MF)) {
825      MF.getRegInfo().setPhysRegUsed(FramePtr);
826      NumGPRSpills++;
827    }
828
829    // If stack and double are 8-byte aligned and we are spilling an odd number
830    // of GPRs, spill one extra callee save GPR so we won't have to pad between
831    // the integer and double callee save areas.
832    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
833    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
834      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
835        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
836          unsigned Reg = UnspilledCS1GPRs[i];
837          // Don't spill high register if the function is thumb1
838          if (!AFI->isThumb1OnlyFunction() ||
839              isARMLowRegister(Reg) || Reg == ARM::LR) {
840            MF.getRegInfo().setPhysRegUsed(Reg);
841            AFI->setCSRegisterIsSpilled(Reg);
842            if (!isReservedReg(MF, Reg))
843              ExtraCSSpill = true;
844            break;
845          }
846        }
847      }
848    }
849
850    // Estimate if we might need to scavenge a register at some point in order
851    // to materialize a stack offset. If so, either spill one additional
852    // callee-saved register or reserve a special spill slot to facilitate
853    // register scavenging. Thumb1 needs a spill slot for stack pointer
854    // adjustments also, even when the frame itself is small.
855    if (BigStack && !ExtraCSSpill) {
856      // If any non-reserved CS register isn't spilled, just spill one or two
857      // extra. That should take care of it!
858      unsigned NumExtras = TargetAlign / 4;
859      SmallVector<unsigned, 2> Extras;
860      while (NumExtras && !UnspilledCS1GPRs.empty()) {
861        unsigned Reg = UnspilledCS1GPRs.back();
862        UnspilledCS1GPRs.pop_back();
863        if (!isReservedReg(MF, Reg) &&
864            (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
865             Reg == ARM::LR)) {
866          Extras.push_back(Reg);
867          NumExtras--;
868        }
869      }
870      if (Extras.size() && NumExtras == 0) {
871        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
872          MF.getRegInfo().setPhysRegUsed(Extras[i]);
873          AFI->setCSRegisterIsSpilled(Extras[i]);
874        }
875      } else if (!AFI->isThumb1OnlyFunction()) {
876        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
877        // closest to SP or frame pointer.
878        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
879        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
880                                                           RC->getAlignment(),
881                                                           false));
882      }
883    }
884  }
885
886  if (ForceLRSpill) {
887    MF.getRegInfo().setPhysRegUsed(ARM::LR);
888    AFI->setCSRegisterIsSpilled(ARM::LR);
889    AFI->setLRIsSpilledForFarJump(true);
890  }
891}
892
893unsigned ARMBaseRegisterInfo::getRARegister() const {
894  return ARM::LR;
895}
896
897unsigned
898ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
899  if (hasFP(MF))
900    return FramePtr;
901  return ARM::SP;
902}
903
904// Provide a base+offset reference to an FI slot for debug info. It's the
905// same as what we use for resolving the code-gen references for now.
906// FIXME: This can go wrong when references are SP-relative and simple call
907//        frames aren't used.
908int
909ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
910                                            unsigned &FrameReg) const {
911  return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
912}
913
914int
915ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
916                                                int FI,
917                                                unsigned &FrameReg,
918                                                int SPAdj) const {
919  const MachineFrameInfo *MFI = MF.getFrameInfo();
920  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
921  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
922  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
923  bool isFixed = MFI->isFixedObjectIndex(FI);
924
925  FrameReg = ARM::SP;
926  Offset += SPAdj;
927  if (AFI->isGPRCalleeSavedAreaFrame(FI))
928    return Offset - AFI->getGPRCalleeSavedAreaOffset();
929  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
930    return Offset - AFI->getDPRCalleeSavedAreaOffset();
931
932  // When dynamically realigning the stack, use the frame pointer for
933  // parameters, and the stack/base pointer for locals.
934  if (needsStackRealignment(MF)) {
935    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
936    if (isFixed) {
937      FrameReg = getFrameRegister(MF);
938      Offset = FPOffset;
939    } else if (MFI->hasVarSizedObjects()) {
940      assert(hasBasePointer(MF) &&
941             "VLAs and dynamic stack alignment, but missing base pointer!");
942      FrameReg = BasePtr;
943    }
944    return Offset;
945  }
946
947  // If there is a frame pointer, use it when we can.
948  if (hasFP(MF) && AFI->hasStackFrame()) {
949    // Use frame pointer to reference fixed objects. Use it for locals if
950    // there are VLAs (and thus the SP isn't reliable as a base).
951    if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
952      FrameReg = getFrameRegister(MF);
953      return FPOffset;
954    } else if (MFI->hasVarSizedObjects()) {
955      assert(hasBasePointer(MF) && "missing base pointer!");
956      // Try to use the frame pointer if we can, else use the base pointer
957      // since it's available. This is handy for the emergency spill slot, in
958      // particular.
959      if (AFI->isThumb2Function()) {
960        if (FPOffset >= -255 && FPOffset < 0) {
961          FrameReg = getFrameRegister(MF);
962          return FPOffset;
963        }
964      } else
965        FrameReg = BasePtr;
966    } else if (AFI->isThumb2Function()) {
967      // In Thumb2 mode, the negative offset is very limited. Try to avoid
968      // out of range references.
969      if (FPOffset >= -255 && FPOffset < 0) {
970        FrameReg = getFrameRegister(MF);
971        return FPOffset;
972      }
973    } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
974      // Otherwise, use SP or FP, whichever is closer to the stack slot.
975      FrameReg = getFrameRegister(MF);
976      return FPOffset;
977    }
978  }
979  // Use the base pointer if we have one.
980  if (hasBasePointer(MF))
981    FrameReg = BasePtr;
982  return Offset;
983}
984
985int
986ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
987                                         int FI) const {
988  unsigned FrameReg;
989  return getFrameIndexReference(MF, FI, FrameReg);
990}
991
992unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
993  llvm_unreachable("What is the exception register");
994  return 0;
995}
996
997unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
998  llvm_unreachable("What is the exception handler register");
999  return 0;
1000}
1001
1002int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1003  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1004}
1005
1006unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1007                                              const MachineFunction &MF) const {
1008  switch (Reg) {
1009  default: break;
1010  // Return 0 if either register of the pair is a special register.
1011  // So no R12, etc.
1012  case ARM::R1:
1013    return ARM::R0;
1014  case ARM::R3:
1015    return ARM::R2;
1016  case ARM::R5:
1017    return ARM::R4;
1018  case ARM::R7:
1019    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1020      ? 0 : ARM::R6;
1021  case ARM::R9:
1022    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1023  case ARM::R11:
1024    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1025
1026  case ARM::S1:
1027    return ARM::S0;
1028  case ARM::S3:
1029    return ARM::S2;
1030  case ARM::S5:
1031    return ARM::S4;
1032  case ARM::S7:
1033    return ARM::S6;
1034  case ARM::S9:
1035    return ARM::S8;
1036  case ARM::S11:
1037    return ARM::S10;
1038  case ARM::S13:
1039    return ARM::S12;
1040  case ARM::S15:
1041    return ARM::S14;
1042  case ARM::S17:
1043    return ARM::S16;
1044  case ARM::S19:
1045    return ARM::S18;
1046  case ARM::S21:
1047    return ARM::S20;
1048  case ARM::S23:
1049    return ARM::S22;
1050  case ARM::S25:
1051    return ARM::S24;
1052  case ARM::S27:
1053    return ARM::S26;
1054  case ARM::S29:
1055    return ARM::S28;
1056  case ARM::S31:
1057    return ARM::S30;
1058
1059  case ARM::D1:
1060    return ARM::D0;
1061  case ARM::D3:
1062    return ARM::D2;
1063  case ARM::D5:
1064    return ARM::D4;
1065  case ARM::D7:
1066    return ARM::D6;
1067  case ARM::D9:
1068    return ARM::D8;
1069  case ARM::D11:
1070    return ARM::D10;
1071  case ARM::D13:
1072    return ARM::D12;
1073  case ARM::D15:
1074    return ARM::D14;
1075  case ARM::D17:
1076    return ARM::D16;
1077  case ARM::D19:
1078    return ARM::D18;
1079  case ARM::D21:
1080    return ARM::D20;
1081  case ARM::D23:
1082    return ARM::D22;
1083  case ARM::D25:
1084    return ARM::D24;
1085  case ARM::D27:
1086    return ARM::D26;
1087  case ARM::D29:
1088    return ARM::D28;
1089  case ARM::D31:
1090    return ARM::D30;
1091  }
1092
1093  return 0;
1094}
1095
1096unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1097                                             const MachineFunction &MF) const {
1098  switch (Reg) {
1099  default: break;
1100  // Return 0 if either register of the pair is a special register.
1101  // So no R12, etc.
1102  case ARM::R0:
1103    return ARM::R1;
1104  case ARM::R2:
1105    return ARM::R3;
1106  case ARM::R4:
1107    return ARM::R5;
1108  case ARM::R6:
1109    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1110      ? 0 : ARM::R7;
1111  case ARM::R8:
1112    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1113  case ARM::R10:
1114    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1115
1116  case ARM::S0:
1117    return ARM::S1;
1118  case ARM::S2:
1119    return ARM::S3;
1120  case ARM::S4:
1121    return ARM::S5;
1122  case ARM::S6:
1123    return ARM::S7;
1124  case ARM::S8:
1125    return ARM::S9;
1126  case ARM::S10:
1127    return ARM::S11;
1128  case ARM::S12:
1129    return ARM::S13;
1130  case ARM::S14:
1131    return ARM::S15;
1132  case ARM::S16:
1133    return ARM::S17;
1134  case ARM::S18:
1135    return ARM::S19;
1136  case ARM::S20:
1137    return ARM::S21;
1138  case ARM::S22:
1139    return ARM::S23;
1140  case ARM::S24:
1141    return ARM::S25;
1142  case ARM::S26:
1143    return ARM::S27;
1144  case ARM::S28:
1145    return ARM::S29;
1146  case ARM::S30:
1147    return ARM::S31;
1148
1149  case ARM::D0:
1150    return ARM::D1;
1151  case ARM::D2:
1152    return ARM::D3;
1153  case ARM::D4:
1154    return ARM::D5;
1155  case ARM::D6:
1156    return ARM::D7;
1157  case ARM::D8:
1158    return ARM::D9;
1159  case ARM::D10:
1160    return ARM::D11;
1161  case ARM::D12:
1162    return ARM::D13;
1163  case ARM::D14:
1164    return ARM::D15;
1165  case ARM::D16:
1166    return ARM::D17;
1167  case ARM::D18:
1168    return ARM::D19;
1169  case ARM::D20:
1170    return ARM::D21;
1171  case ARM::D22:
1172    return ARM::D23;
1173  case ARM::D24:
1174    return ARM::D25;
1175  case ARM::D26:
1176    return ARM::D27;
1177  case ARM::D28:
1178    return ARM::D29;
1179  case ARM::D30:
1180    return ARM::D31;
1181  }
1182
1183  return 0;
1184}
1185
1186/// emitLoadConstPool - Emits a load from constpool to materialize the
1187/// specified immediate.
1188void ARMBaseRegisterInfo::
1189emitLoadConstPool(MachineBasicBlock &MBB,
1190                  MachineBasicBlock::iterator &MBBI,
1191                  DebugLoc dl,
1192                  unsigned DestReg, unsigned SubIdx, int Val,
1193                  ARMCC::CondCodes Pred,
1194                  unsigned PredReg) const {
1195  MachineFunction &MF = *MBB.getParent();
1196  MachineConstantPool *ConstantPool = MF.getConstantPool();
1197  const Constant *C =
1198        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1199  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1200
1201  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1202    .addReg(DestReg, getDefRegState(true), SubIdx)
1203    .addConstantPoolIndex(Idx)
1204    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1205}
1206
1207bool ARMBaseRegisterInfo::
1208requiresRegisterScavenging(const MachineFunction &MF) const {
1209  return true;
1210}
1211
1212bool ARMBaseRegisterInfo::
1213requiresFrameIndexScavenging(const MachineFunction &MF) const {
1214  return true;
1215}
1216
1217bool ARMBaseRegisterInfo::
1218requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1219  return EnableLocalStackAlloc;
1220}
1221
1222// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1223// not required, we reserve argument space for call sites in the function
1224// immediately on entry to the current function. This eliminates the need for
1225// add/sub sp brackets around call sites. Returns true if the call frame is
1226// included as part of the stack frame.
1227bool ARMBaseRegisterInfo::
1228hasReservedCallFrame(const MachineFunction &MF) const {
1229  const MachineFrameInfo *FFI = MF.getFrameInfo();
1230  unsigned CFSize = FFI->getMaxCallFrameSize();
1231  // It's not always a good idea to include the call frame as part of the
1232  // stack frame. ARM (especially Thumb) has small immediate offset to
1233  // address the stack frame. So a large call frame can cause poor codegen
1234  // and may even makes it impossible to scavenge a register.
1235  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1236    return false;
1237
1238  return !MF.getFrameInfo()->hasVarSizedObjects();
1239}
1240
1241// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1242// call frame pseudos can be simplified. Unlike most targets, having a FP
1243// is not sufficient here since we still may reference some objects via SP
1244// even when FP is available in Thumb2 mode.
1245bool ARMBaseRegisterInfo::
1246canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1247  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1248}
1249
1250static void
1251emitSPUpdate(bool isARM,
1252             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1253             DebugLoc dl, const ARMBaseInstrInfo &TII,
1254             int NumBytes,
1255             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1256  if (isARM)
1257    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1258                            Pred, PredReg, TII);
1259  else
1260    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1261                           Pred, PredReg, TII);
1262}
1263
1264
1265void ARMBaseRegisterInfo::
1266eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1267                              MachineBasicBlock::iterator I) const {
1268  if (!hasReservedCallFrame(MF)) {
1269    // If we have alloca, convert as follows:
1270    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1271    // ADJCALLSTACKUP   -> add, sp, sp, amount
1272    MachineInstr *Old = I;
1273    DebugLoc dl = Old->getDebugLoc();
1274    unsigned Amount = Old->getOperand(0).getImm();
1275    if (Amount != 0) {
1276      // We need to keep the stack aligned properly.  To do this, we round the
1277      // amount of space needed for the outgoing arguments up to the next
1278      // alignment boundary.
1279      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1280      Amount = (Amount+Align-1)/Align*Align;
1281
1282      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1283      assert(!AFI->isThumb1OnlyFunction() &&
1284             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1285      bool isARM = !AFI->isThumbFunction();
1286
1287      // Replace the pseudo instruction with a new instruction...
1288      unsigned Opc = Old->getOpcode();
1289      int PIdx = Old->findFirstPredOperandIdx();
1290      ARMCC::CondCodes Pred = (PIdx == -1)
1291        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1292      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1293        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1294        unsigned PredReg = Old->getOperand(2).getReg();
1295        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1296      } else {
1297        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1298        unsigned PredReg = Old->getOperand(3).getReg();
1299        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1300        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1301      }
1302    }
1303  }
1304  MBB.erase(I);
1305}
1306
1307int64_t ARMBaseRegisterInfo::
1308getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1309  const TargetInstrDesc &Desc = MI->getDesc();
1310  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1311  int64_t InstrOffs = 0;;
1312  int Scale = 1;
1313  unsigned ImmIdx = 0;
1314  switch (AddrMode) {
1315  case ARMII::AddrModeT2_i8:
1316  case ARMII::AddrModeT2_i12:
1317    // i8 supports only negative, and i12 supports only positive, so
1318    // based on Offset sign, consider the appropriate instruction
1319    InstrOffs = MI->getOperand(Idx+1).getImm();
1320    Scale = 1;
1321    break;
1322  case ARMII::AddrMode5: {
1323    // VFP address mode.
1324    const MachineOperand &OffOp = MI->getOperand(Idx+1);
1325    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1326    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1327      InstrOffs = -InstrOffs;
1328    Scale = 4;
1329    break;
1330  }
1331  case ARMII::AddrMode2: {
1332    ImmIdx = Idx+2;
1333    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1334    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1335      InstrOffs = -InstrOffs;
1336    break;
1337  }
1338  case ARMII::AddrMode3: {
1339    ImmIdx = Idx+2;
1340    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1341    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1342      InstrOffs = -InstrOffs;
1343    break;
1344  }
1345  case ARMII::AddrModeT1_s: {
1346    ImmIdx = Idx+1;
1347    InstrOffs = MI->getOperand(ImmIdx).getImm();
1348    Scale = 4;
1349    break;
1350  }
1351  default:
1352    llvm_unreachable("Unsupported addressing mode!");
1353    break;
1354  }
1355
1356  return InstrOffs * Scale;
1357}
1358
1359/// needsFrameBaseReg - Returns true if the instruction's frame index
1360/// reference would be better served by a base register other than FP
1361/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1362/// references it should create new base registers for.
1363bool ARMBaseRegisterInfo::
1364needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1365  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1366    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1367  }
1368
1369  // It's the load/store FI references that cause issues, as it can be difficult
1370  // to materialize the offset if it won't fit in the literal field. Estimate
1371  // based on the size of the local frame and some conservative assumptions
1372  // about the rest of the stack frame (note, this is pre-regalloc, so
1373  // we don't know everything for certain yet) whether this offset is likely
1374  // to be out of range of the immediate. Return true if so.
1375
1376  // We only generate virtual base registers for loads and stores, so
1377  // return false for everything else.
1378  unsigned Opc = MI->getOpcode();
1379  switch (Opc) {
1380  case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1381  case ARM::STR: case ARM::STRH: case ARM::STRB:
1382  case ARM::t2LDRi12: case ARM::t2LDRi8:
1383  case ARM::t2STRi12: case ARM::t2STRi8:
1384  case ARM::VLDRS: case ARM::VLDRD:
1385  case ARM::VSTRS: case ARM::VSTRD:
1386  case ARM::tSTRspi: case ARM::tLDRspi:
1387    if (ForceAllBaseRegAlloc)
1388      return true;
1389    break;
1390  default:
1391    return false;
1392  }
1393
1394  // Without a virtual base register, if the function has variable sized
1395  // objects, all fixed-size local references will be via the frame pointer,
1396  // Approximate the offset and see if it's legal for the instruction.
1397  // Note that the incoming offset is based on the SP value at function entry,
1398  // so it'll be negative.
1399  MachineFunction &MF = *MI->getParent()->getParent();
1400  MachineFrameInfo *MFI = MF.getFrameInfo();
1401  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1402
1403  // Estimate an offset from the frame pointer.
1404  // Conservatively assume all callee-saved registers get pushed. R4-R6
1405  // will be earlier than the FP, so we ignore those.
1406  // R7, LR
1407  int64_t FPOffset = Offset - 8;
1408  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1409  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1410    FPOffset -= 80;
1411  // Estimate an offset from the stack pointer.
1412  // The incoming offset is relating to the SP at the start of the function,
1413  // but when we access the local it'll be relative to the SP after local
1414  // allocation, so adjust our SP-relative offset by that allocation size.
1415  Offset = -Offset;
1416  Offset += MFI->getLocalFrameSize();
1417  // Assume that we'll have at least some spill slots allocated.
1418  // FIXME: This is a total SWAG number. We should run some statistics
1419  //        and pick a real one.
1420  Offset += 128; // 128 bytes of spill slots
1421
1422  // If there is a frame pointer, try using it.
1423  // The FP is only available if there is no dynamic realignment. We
1424  // don't know for sure yet whether we'll need that, so we guess based
1425  // on whether there are any local variables that would trigger it.
1426  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1427  if (hasFP(MF) &&
1428      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1429    if (isFrameOffsetLegal(MI, FPOffset))
1430      return false;
1431  }
1432  // If we can reference via the stack pointer, try that.
1433  // FIXME: This (and the code that resolves the references) can be improved
1434  //        to only disallow SP relative references in the live range of
1435  //        the VLA(s). In practice, it's unclear how much difference that
1436  //        would make, but it may be worth doing.
1437  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1438    return false;
1439
1440  // The offset likely isn't legal, we want to allocate a virtual base register.
1441  return true;
1442}
1443
1444/// materializeFrameBaseRegister - Insert defining instruction(s) for
1445/// BaseReg to be a pointer to FrameIdx before insertion point I.
1446void ARMBaseRegisterInfo::
1447materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1448                             int FrameIdx, int64_t Offset) const {
1449  ARMFunctionInfo *AFI =
1450    I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1451  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1452    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1453
1454  MachineInstrBuilder MIB =
1455    BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1456    .addFrameIndex(FrameIdx).addImm(Offset);
1457  if (!AFI->isThumb1OnlyFunction())
1458    AddDefaultCC(AddDefaultPred(MIB));
1459}
1460
1461void
1462ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1463                                       unsigned BaseReg, int64_t Offset) const {
1464  MachineInstr &MI = *I;
1465  MachineBasicBlock &MBB = *MI.getParent();
1466  MachineFunction &MF = *MBB.getParent();
1467  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1468  int Off = Offset; // ARM doesn't need the general 64-bit offsets
1469  unsigned i = 0;
1470
1471  assert(!AFI->isThumb1OnlyFunction() &&
1472         "This resolveFrameIndex does not support Thumb1!");
1473
1474  while (!MI.getOperand(i).isFI()) {
1475    ++i;
1476    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1477  }
1478  bool Done = false;
1479  if (!AFI->isThumbFunction())
1480    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1481  else {
1482    assert(AFI->isThumb2Function());
1483    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1484  }
1485  assert (Done && "Unable to resolve frame index!");
1486}
1487
1488bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1489                                             int64_t Offset) const {
1490  const TargetInstrDesc &Desc = MI->getDesc();
1491  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1492  unsigned i = 0;
1493
1494  while (!MI->getOperand(i).isFI()) {
1495    ++i;
1496    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1497  }
1498
1499  // AddrMode4 and AddrMode6 cannot handle any offset.
1500  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1501    return Offset == 0;
1502
1503  unsigned NumBits = 0;
1504  unsigned Scale = 1;
1505  bool isSigned = true;
1506  switch (AddrMode) {
1507  case ARMII::AddrModeT2_i8:
1508  case ARMII::AddrModeT2_i12:
1509    // i8 supports only negative, and i12 supports only positive, so
1510    // based on Offset sign, consider the appropriate instruction
1511    Scale = 1;
1512    if (Offset < 0) {
1513      NumBits = 8;
1514      Offset = -Offset;
1515    } else {
1516      NumBits = 12;
1517    }
1518    break;
1519  case ARMII::AddrMode5:
1520    // VFP address mode.
1521    NumBits = 8;
1522    Scale = 4;
1523    break;
1524  case ARMII::AddrMode2:
1525    NumBits = 12;
1526    break;
1527  case ARMII::AddrMode3:
1528    NumBits = 8;
1529    break;
1530  case ARMII::AddrModeT1_s:
1531    NumBits = 5;
1532    Scale = 4;
1533    isSigned = false;
1534    break;
1535  default:
1536    llvm_unreachable("Unsupported addressing mode!");
1537    break;
1538  }
1539
1540  Offset += getFrameIndexInstrOffset(MI, i);
1541  // Make sure the offset is encodable for instructions that scale the
1542  // immediate.
1543  if ((Offset & (Scale-1)) != 0)
1544    return false;
1545
1546  if (isSigned && Offset < 0)
1547    Offset = -Offset;
1548
1549  unsigned Mask = (1 << NumBits) - 1;
1550  if ((unsigned)Offset <= Mask * Scale)
1551    return true;
1552
1553  return false;
1554}
1555
1556void
1557ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1558                                         int SPAdj, RegScavenger *RS) const {
1559  unsigned i = 0;
1560  MachineInstr &MI = *II;
1561  MachineBasicBlock &MBB = *MI.getParent();
1562  MachineFunction &MF = *MBB.getParent();
1563  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1564  assert(!AFI->isThumb1OnlyFunction() &&
1565         "This eliminateFrameIndex does not support Thumb1!");
1566
1567  while (!MI.getOperand(i).isFI()) {
1568    ++i;
1569    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1570  }
1571
1572  int FrameIndex = MI.getOperand(i).getIndex();
1573  unsigned FrameReg;
1574
1575  int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1576
1577  // Special handling of dbg_value instructions.
1578  if (MI.isDebugValue()) {
1579    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1580    MI.getOperand(i+1).ChangeToImmediate(Offset);
1581    return;
1582  }
1583
1584  // Modify MI as necessary to handle as much of 'Offset' as possible
1585  bool Done = false;
1586  if (!AFI->isThumbFunction())
1587    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1588  else {
1589    assert(AFI->isThumb2Function());
1590    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1591  }
1592  if (Done)
1593    return;
1594
1595  // If we get here, the immediate doesn't fit into the instruction.  We folded
1596  // as much as possible above, handle the rest, providing a register that is
1597  // SP+LargeImm.
1598  assert((Offset ||
1599          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1600          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1601         "This code isn't needed if offset already handled!");
1602
1603  unsigned ScratchReg = 0;
1604  int PIdx = MI.findFirstPredOperandIdx();
1605  ARMCC::CondCodes Pred = (PIdx == -1)
1606    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1607  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1608  if (Offset == 0)
1609    // Must be addrmode4/6.
1610    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1611  else {
1612    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1613    if (!AFI->isThumbFunction())
1614      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1615                              Offset, Pred, PredReg, TII);
1616    else {
1617      assert(AFI->isThumb2Function());
1618      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1619                             Offset, Pred, PredReg, TII);
1620    }
1621    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1622  }
1623}
1624
1625/// Move iterator past the next bunch of callee save load / store ops for
1626/// the particular spill area (1: integer area 1, 2: fp area, 0: don't care).
1627static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1628                                   MachineBasicBlock::iterator &MBBI,
1629                                   int Opc1, int Opc2, unsigned Area,
1630                                   const ARMSubtarget &STI) {
1631  while (MBBI != MBB.end() &&
1632         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1633         MBBI->getOperand(1).isFI()) {
1634    if (Area != 0) {
1635      bool Done = false;
1636      unsigned Category = 0;
1637      switch (MBBI->getOperand(0).getReg()) {
1638      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1639      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1640      case ARM::LR:
1641        Category = 1;
1642        break;
1643      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1644      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1645        Category = 2;
1646        break;
1647      default:
1648        Done = true;
1649        break;
1650      }
1651      if (Done || Category != Area)
1652        break;
1653    }
1654
1655    ++MBBI;
1656  }
1657}
1658
1659void ARMBaseRegisterInfo::
1660emitPrologue(MachineFunction &MF) const {
1661  MachineBasicBlock &MBB = MF.front();
1662  MachineBasicBlock::iterator MBBI = MBB.begin();
1663  MachineFrameInfo  *MFI = MF.getFrameInfo();
1664  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1665  assert(!AFI->isThumb1OnlyFunction() &&
1666         "This emitPrologue does not support Thumb1!");
1667  bool isARM = !AFI->isThumbFunction();
1668  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1669  unsigned NumBytes = MFI->getStackSize();
1670  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1671  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1672
1673  // Determine the sizes of each callee-save spill areas and record which frame
1674  // belongs to which callee-save spill areas.
1675  unsigned GPRCSSize = 0, DPRCSSize = 0;
1676  int FramePtrSpillFI = 0;
1677
1678  // Allocate the vararg register save area. This is not counted in NumBytes.
1679  if (VARegSaveSize)
1680    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1681
1682  if (!AFI->hasStackFrame()) {
1683    if (NumBytes != 0)
1684      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1685    return;
1686  }
1687
1688  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1689    unsigned Reg = CSI[i].getReg();
1690    int FI = CSI[i].getFrameIdx();
1691    switch (Reg) {
1692    case ARM::R4:
1693    case ARM::R5:
1694    case ARM::R6:
1695    case ARM::R7:
1696    case ARM::R8:
1697    case ARM::R9:
1698    case ARM::R10:
1699    case ARM::R11:
1700    case ARM::LR:
1701      if (Reg == FramePtr)
1702        FramePtrSpillFI = FI;
1703      AFI->addGPRCalleeSavedAreaFrame(FI);
1704      GPRCSSize += 4;
1705      break;
1706    default:
1707      AFI->addDPRCalleeSavedAreaFrame(FI);
1708      DPRCSSize += 8;
1709    }
1710  }
1711
1712  // Build the new SUBri to adjust SP for integer callee-save spill area.
1713  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCSSize);
1714  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1715
1716  // Set FP to point to the stack slot that contains the previous FP.
1717  bool HasFP = hasFP(MF);
1718  if (HasFP) {
1719    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1720    MachineInstrBuilder MIB =
1721      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1722      .addFrameIndex(FramePtrSpillFI).addImm(0);
1723    AddDefaultCC(AddDefaultPred(MIB));
1724  }
1725
1726  // Build the new SUBri to adjust SP for FP callee-save spill area.
1727  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1728
1729  // Determine starting offsets of spill areas.
1730  unsigned DPRCSOffset  = NumBytes - (GPRCSSize + DPRCSSize);
1731  unsigned GPRCSOffset = DPRCSOffset + DPRCSSize;
1732  if (HasFP)
1733    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1734                                NumBytes);
1735  AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset);
1736  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1737
1738  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 2, STI);
1739  NumBytes = DPRCSOffset;
1740  if (NumBytes) {
1741    // Adjust SP after all the callee-save spills.
1742    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1743    if (HasFP)
1744      AFI->setShouldRestoreSPFromFP(true);
1745  }
1746
1747  if (STI.isTargetELF() && hasFP(MF)) {
1748    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1749                             AFI->getFramePtrSpillOffset());
1750    AFI->setShouldRestoreSPFromFP(true);
1751  }
1752
1753  AFI->setGPRCalleeSavedAreaSize(GPRCSSize);
1754  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1755
1756  // If we need dynamic stack realignment, do it here. Be paranoid and make
1757  // sure if we also have VLAs, we have a base pointer for frame access.
1758  if (needsStackRealignment(MF)) {
1759    unsigned MaxAlign = MFI->getMaxAlignment();
1760    assert (!AFI->isThumb1OnlyFunction());
1761    if (!AFI->isThumbFunction()) {
1762      // Emit bic sp, sp, MaxAlign
1763      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1764                                          TII.get(ARM::BICri), ARM::SP)
1765                                  .addReg(ARM::SP, RegState::Kill)
1766                                  .addImm(MaxAlign-1)));
1767    } else {
1768      // We cannot use sp as source/dest register here, thus we're emitting the
1769      // following sequence:
1770      // mov r4, sp
1771      // bic r4, r4, MaxAlign
1772      // mov sp, r4
1773      // FIXME: It will be better just to find spare register here.
1774      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1775        .addReg(ARM::SP, RegState::Kill);
1776      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1777                                          TII.get(ARM::t2BICri), ARM::R4)
1778                                  .addReg(ARM::R4, RegState::Kill)
1779                                  .addImm(MaxAlign-1)));
1780      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1781        .addReg(ARM::R4, RegState::Kill);
1782    }
1783
1784    AFI->setShouldRestoreSPFromFP(true);
1785  }
1786
1787  // If we need a base pointer, set it up here. It's whatever the value
1788  // of the stack pointer is at this point. Any variable size objects
1789  // will be allocated after this, so we can still use the base pointer
1790  // to reference locals.
1791  if (hasBasePointer(MF)) {
1792    if (isARM)
1793      BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr)
1794        .addReg(ARM::SP)
1795        .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1796    else
1797      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
1798        .addReg(ARM::SP);
1799  }
1800
1801  // If the frame has variable sized objects then the epilogue must restore
1802  // the sp from fp.
1803  if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1804    AFI->setShouldRestoreSPFromFP(true);
1805}
1806
1807static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1808  for (unsigned i = 0; CSRegs[i]; ++i)
1809    if (Reg == CSRegs[i])
1810      return true;
1811  return false;
1812}
1813
1814static bool isCSRestore(MachineInstr *MI,
1815                        const ARMBaseInstrInfo &TII,
1816                        const unsigned *CSRegs) {
1817  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1818           MI->getOpcode() == (int)ARM::LDR ||
1819           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1820          MI->getOperand(1).isFI() &&
1821          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1822}
1823
1824void ARMBaseRegisterInfo::
1825emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1826  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1827  assert(MBBI->getDesc().isReturn() &&
1828         "Can only insert epilog into returning blocks");
1829  unsigned RetOpcode = MBBI->getOpcode();
1830  DebugLoc dl = MBBI->getDebugLoc();
1831  MachineFrameInfo *MFI = MF.getFrameInfo();
1832  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1833  assert(!AFI->isThumb1OnlyFunction() &&
1834         "This emitEpilogue does not support Thumb1!");
1835  bool isARM = !AFI->isThumbFunction();
1836
1837  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1838  int NumBytes = (int)MFI->getStackSize();
1839
1840  if (!AFI->hasStackFrame()) {
1841    if (NumBytes != 0)
1842      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1843  } else {
1844    // Unwind MBBI to point to first LDR / VLDRD.
1845    const unsigned *CSRegs = getCalleeSavedRegs();
1846    if (MBBI != MBB.begin()) {
1847      do
1848        --MBBI;
1849      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1850      if (!isCSRestore(MBBI, TII, CSRegs))
1851        ++MBBI;
1852    }
1853
1854    // Move SP to start of FP callee save spill area.
1855    NumBytes -= (AFI->getGPRCalleeSavedAreaSize() +
1856                 AFI->getDPRCalleeSavedAreaSize());
1857
1858    // Reset SP based on frame pointer only if the stack frame extends beyond
1859    // frame pointer stack slot or target is ELF and the function has FP.
1860    if (AFI->shouldRestoreSPFromFP()) {
1861      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1862      if (NumBytes) {
1863        if (isARM)
1864          emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1865                                  ARMCC::AL, 0, TII);
1866        else
1867          emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1868                                 ARMCC::AL, 0, TII);
1869      } else {
1870        // Thumb2 or ARM.
1871        if (isARM)
1872          BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1873            .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1874        else
1875          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1876            .addReg(FramePtr);
1877      }
1878    } else if (NumBytes)
1879      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1880
1881    // Move SP to start of integer callee save spill area.
1882    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 2, STI);
1883    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1884
1885    // Move SP to SP upon entry to the function.
1886    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1887    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedAreaSize());
1888  }
1889
1890  if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1891      RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1892    // Tail call return: adjust the stack pointer and jump to callee.
1893    MBBI = prior(MBB.end());
1894    MachineOperand &JumpTarget = MBBI->getOperand(0);
1895
1896    // Jump to label or value in register.
1897    if (RetOpcode == ARM::TCRETURNdi) {
1898      BuildMI(MBB, MBBI, dl,
1899            TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1900        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1901                         JumpTarget.getTargetFlags());
1902    } else if (RetOpcode == ARM::TCRETURNdiND) {
1903      BuildMI(MBB, MBBI, dl,
1904            TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1905        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1906                         JumpTarget.getTargetFlags());
1907    } else if (RetOpcode == ARM::TCRETURNri) {
1908      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1909        addReg(JumpTarget.getReg(), RegState::Kill);
1910    } else if (RetOpcode == ARM::TCRETURNriND) {
1911      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1912        addReg(JumpTarget.getReg(), RegState::Kill);
1913    }
1914
1915    MachineInstr *NewMI = prior(MBBI);
1916    for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1917      NewMI->addOperand(MBBI->getOperand(i));
1918
1919    // Delete the pseudo instruction TCRETURN.
1920    MBB.erase(MBBI);
1921  }
1922
1923  if (VARegSaveSize)
1924    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1925}
1926
1927#include "ARMGenRegisterInfo.inc"
1928