ARMFastISel.cpp revision 022b7fb045973531a1b05f4f0dae28fd836c9890 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMRegisterInfo.h"
20#include "ARMTargetMachine.h"
21#include "ARMSubtarget.h"
22#include "ARMConstantPoolValue.h"
23#include "llvm/CallingConv.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/Instructions.h"
27#include "llvm/IntrinsicInst.h"
28#include "llvm/Module.h"
29#include "llvm/CodeGen/Analysis.h"
30#include "llvm/CodeGen/FastISel.h"
31#include "llvm/CodeGen/FunctionLoweringInfo.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineConstantPool.h"
35#include "llvm/CodeGen/MachineFrameInfo.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/Support/CallSite.h"
38#include "llvm/Support/CommandLine.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/GetElementPtrTypeIterator.h"
41#include "llvm/Target/TargetData.h"
42#include "llvm/Target/TargetInstrInfo.h"
43#include "llvm/Target/TargetLowering.h"
44#include "llvm/Target/TargetMachine.h"
45#include "llvm/Target/TargetOptions.h"
46using namespace llvm;
47
48static cl::opt<bool>
49EnableARMFastISel("arm-fast-isel",
50                  cl::desc("Turn on experimental ARM fast-isel support"),
51                  cl::init(false), cl::Hidden);
52
53namespace {
54
55class ARMFastISel : public FastISel {
56
57  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
58  /// make the right decision when generating code for different targets.
59  const ARMSubtarget *Subtarget;
60  const TargetMachine &TM;
61  const TargetInstrInfo &TII;
62  const TargetLowering &TLI;
63  ARMFunctionInfo *AFI;
64
65  // Convenience variables to avoid some queries.
66  bool isThumb;
67  LLVMContext *Context;
68
69  public:
70    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
71    : FastISel(funcInfo),
72      TM(funcInfo.MF->getTarget()),
73      TII(*TM.getInstrInfo()),
74      TLI(*TM.getTargetLowering()) {
75      Subtarget = &TM.getSubtarget<ARMSubtarget>();
76      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
77      isThumb = AFI->isThumbFunction();
78      Context = &funcInfo.Fn->getContext();
79    }
80
81    // Code from FastISel.cpp.
82    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
83                                   const TargetRegisterClass *RC);
84    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
85                                    const TargetRegisterClass *RC,
86                                    unsigned Op0, bool Op0IsKill);
87    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
88                                     const TargetRegisterClass *RC,
89                                     unsigned Op0, bool Op0IsKill,
90                                     unsigned Op1, bool Op1IsKill);
91    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
92                                     const TargetRegisterClass *RC,
93                                     unsigned Op0, bool Op0IsKill,
94                                     uint64_t Imm);
95    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
96                                     const TargetRegisterClass *RC,
97                                     unsigned Op0, bool Op0IsKill,
98                                     const ConstantFP *FPImm);
99    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
100                                    const TargetRegisterClass *RC,
101                                    uint64_t Imm);
102    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
103                                      const TargetRegisterClass *RC,
104                                      unsigned Op0, bool Op0IsKill,
105                                      unsigned Op1, bool Op1IsKill,
106                                      uint64_t Imm);
107    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
108                                                unsigned Op0, bool Op0IsKill,
109                                                uint32_t Idx);
110
111    // Backend specific FastISel code.
112    virtual bool TargetSelectInstruction(const Instruction *I);
113    virtual unsigned TargetMaterializeConstant(const Constant *C);
114    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
115
116  #include "ARMGenFastISel.inc"
117
118    // Instruction selection routines.
119  private:
120    virtual bool SelectLoad(const Instruction *I);
121    virtual bool SelectStore(const Instruction *I);
122    virtual bool SelectBranch(const Instruction *I);
123    virtual bool SelectCmp(const Instruction *I);
124    virtual bool SelectFPExt(const Instruction *I);
125    virtual bool SelectFPTrunc(const Instruction *I);
126    virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
127    virtual bool SelectSIToFP(const Instruction *I);
128    virtual bool SelectFPToSI(const Instruction *I);
129    virtual bool SelectSDiv(const Instruction *I);
130    virtual bool SelectCall(const Instruction *I);
131
132    // Utility routines.
133  private:
134    bool isTypeLegal(const Type *Ty, EVT &VT);
135    bool isLoadTypeLegal(const Type *Ty, EVT &VT);
136    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
137    bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
138    bool ARMLoadAlloca(const Instruction *I, EVT VT);
139    bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
140    bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
141    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
142    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
143    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
144    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
145    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
146
147    // Call handling routines.
148  private:
149    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
150    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
151                         SmallVectorImpl<unsigned> &ArgRegs,
152                         SmallVectorImpl<EVT> &ArgVTs,
153                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
154                         SmallVectorImpl<unsigned> &RegArgs,
155                         CallingConv::ID CC,
156                         unsigned &NumBytes);
157    bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
158                    const Instruction *I, CallingConv::ID CC,
159                    unsigned &NumBytes);
160    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
161
162    // OptionalDef handling routines.
163  private:
164    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
165    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
166};
167
168} // end anonymous namespace
169
170#include "ARMGenCallingConv.inc"
171
172// DefinesOptionalPredicate - This is different from DefinesPredicate in that
173// we don't care about implicit defs here, just places we'll need to add a
174// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
175bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
176  const TargetInstrDesc &TID = MI->getDesc();
177  if (!TID.hasOptionalDef())
178    return false;
179
180  // Look to see if our OptionalDef is defining CPSR or CCR.
181  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
182    const MachineOperand &MO = MI->getOperand(i);
183    if (!MO.isReg() || !MO.isDef()) continue;
184    if (MO.getReg() == ARM::CPSR)
185      *CPSR = true;
186  }
187  return true;
188}
189
190// If the machine is predicable go ahead and add the predicate operands, if
191// it needs default CC operands add those.
192const MachineInstrBuilder &
193ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
194  MachineInstr *MI = &*MIB;
195
196  // Do we use a predicate?
197  if (TII.isPredicable(MI))
198    AddDefaultPred(MIB);
199
200  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
201  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
202  bool CPSR = false;
203  if (DefinesOptionalPredicate(MI, &CPSR)) {
204    if (CPSR)
205      AddDefaultT1CC(MIB);
206    else
207      AddDefaultCC(MIB);
208  }
209  return MIB;
210}
211
212unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
213                                    const TargetRegisterClass* RC) {
214  unsigned ResultReg = createResultReg(RC);
215  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
216
217  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
218  return ResultReg;
219}
220
221unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
222                                     const TargetRegisterClass *RC,
223                                     unsigned Op0, bool Op0IsKill) {
224  unsigned ResultReg = createResultReg(RC);
225  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
226
227  if (II.getNumDefs() >= 1)
228    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
229                   .addReg(Op0, Op0IsKill * RegState::Kill));
230  else {
231    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
232                   .addReg(Op0, Op0IsKill * RegState::Kill));
233    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
234                   TII.get(TargetOpcode::COPY), ResultReg)
235                   .addReg(II.ImplicitDefs[0]));
236  }
237  return ResultReg;
238}
239
240unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
241                                      const TargetRegisterClass *RC,
242                                      unsigned Op0, bool Op0IsKill,
243                                      unsigned Op1, bool Op1IsKill) {
244  unsigned ResultReg = createResultReg(RC);
245  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
246
247  if (II.getNumDefs() >= 1)
248    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
249                   .addReg(Op0, Op0IsKill * RegState::Kill)
250                   .addReg(Op1, Op1IsKill * RegState::Kill));
251  else {
252    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
253                   .addReg(Op0, Op0IsKill * RegState::Kill)
254                   .addReg(Op1, Op1IsKill * RegState::Kill));
255    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
256                           TII.get(TargetOpcode::COPY), ResultReg)
257                   .addReg(II.ImplicitDefs[0]));
258  }
259  return ResultReg;
260}
261
262unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
263                                      const TargetRegisterClass *RC,
264                                      unsigned Op0, bool Op0IsKill,
265                                      uint64_t Imm) {
266  unsigned ResultReg = createResultReg(RC);
267  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
268
269  if (II.getNumDefs() >= 1)
270    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
271                   .addReg(Op0, Op0IsKill * RegState::Kill)
272                   .addImm(Imm));
273  else {
274    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
275                   .addReg(Op0, Op0IsKill * RegState::Kill)
276                   .addImm(Imm));
277    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
278                           TII.get(TargetOpcode::COPY), ResultReg)
279                   .addReg(II.ImplicitDefs[0]));
280  }
281  return ResultReg;
282}
283
284unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
285                                      const TargetRegisterClass *RC,
286                                      unsigned Op0, bool Op0IsKill,
287                                      const ConstantFP *FPImm) {
288  unsigned ResultReg = createResultReg(RC);
289  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
290
291  if (II.getNumDefs() >= 1)
292    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
293                   .addReg(Op0, Op0IsKill * RegState::Kill)
294                   .addFPImm(FPImm));
295  else {
296    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
297                   .addReg(Op0, Op0IsKill * RegState::Kill)
298                   .addFPImm(FPImm));
299    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
300                           TII.get(TargetOpcode::COPY), ResultReg)
301                   .addReg(II.ImplicitDefs[0]));
302  }
303  return ResultReg;
304}
305
306unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
307                                       const TargetRegisterClass *RC,
308                                       unsigned Op0, bool Op0IsKill,
309                                       unsigned Op1, bool Op1IsKill,
310                                       uint64_t Imm) {
311  unsigned ResultReg = createResultReg(RC);
312  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
313
314  if (II.getNumDefs() >= 1)
315    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
316                   .addReg(Op0, Op0IsKill * RegState::Kill)
317                   .addReg(Op1, Op1IsKill * RegState::Kill)
318                   .addImm(Imm));
319  else {
320    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
321                   .addReg(Op0, Op0IsKill * RegState::Kill)
322                   .addReg(Op1, Op1IsKill * RegState::Kill)
323                   .addImm(Imm));
324    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
325                           TII.get(TargetOpcode::COPY), ResultReg)
326                   .addReg(II.ImplicitDefs[0]));
327  }
328  return ResultReg;
329}
330
331unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
332                                     const TargetRegisterClass *RC,
333                                     uint64_t Imm) {
334  unsigned ResultReg = createResultReg(RC);
335  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
336
337  if (II.getNumDefs() >= 1)
338    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
339                   .addImm(Imm));
340  else {
341    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
342                   .addImm(Imm));
343    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
344                           TII.get(TargetOpcode::COPY), ResultReg)
345                   .addReg(II.ImplicitDefs[0]));
346  }
347  return ResultReg;
348}
349
350unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
351                                                 unsigned Op0, bool Op0IsKill,
352                                                 uint32_t Idx) {
353  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
354  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
355         "Cannot yet extract from physregs");
356  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
357                         DL, TII.get(TargetOpcode::COPY), ResultReg)
358                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
359  return ResultReg;
360}
361
362// TODO: Don't worry about 64-bit now, but when this is fixed remove the
363// checks from the various callers.
364unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
365  if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
366
367  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
368  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
369                          TII.get(ARM::VMOVRS), MoveReg)
370                  .addReg(SrcReg));
371  return MoveReg;
372}
373
374unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
375  if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
376
377  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
378  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
379                          TII.get(ARM::VMOVSR), MoveReg)
380                  .addReg(SrcReg));
381  return MoveReg;
382}
383
384// For double width floating point we need to materialize two constants
385// (the high and the low) into integer registers then use a move to get
386// the combined constant into an FP reg.
387unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
388  const APFloat Val = CFP->getValueAPF();
389  bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
390
391  // This checks to see if we can use VFP3 instructions to materialize
392  // a constant, otherwise we have to go through the constant pool.
393  if (TLI.isFPImmLegal(Val, VT)) {
394    unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
395    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
396    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
397                            DestReg)
398                    .addFPImm(CFP));
399    return DestReg;
400  }
401
402  // Require VFP2 for loading fp constants.
403  if (!Subtarget->hasVFP2()) return false;
404
405  // MachineConstantPool wants an explicit alignment.
406  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
407  if (Align == 0) {
408    // TODO: Figure out if this is correct.
409    Align = TD.getTypeAllocSize(CFP->getType());
410  }
411  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
412  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
413  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
414
415  // The extra reg is for addrmode5.
416  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
417                          DestReg)
418                  .addConstantPoolIndex(Idx)
419                  .addReg(0));
420  return DestReg;
421}
422
423unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
424
425  // For now 32-bit only.
426  if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
427
428  // MachineConstantPool wants an explicit alignment.
429  unsigned Align = TD.getPrefTypeAlignment(C->getType());
430  if (Align == 0) {
431    // TODO: Figure out if this is correct.
432    Align = TD.getTypeAllocSize(C->getType());
433  }
434  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
435  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
436
437  if (isThumb)
438    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
439                            TII.get(ARM::t2LDRpci), DestReg)
440                    .addConstantPoolIndex(Idx));
441  else
442    // The extra reg and immediate are for addrmode2.
443    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
444                            TII.get(ARM::LDRcp), DestReg)
445                    .addConstantPoolIndex(Idx)
446                    .addReg(0).addImm(0));
447
448  return DestReg;
449}
450
451unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
452  // For now 32-bit only.
453  if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
454
455  Reloc::Model RelocM = TM.getRelocationModel();
456
457  // TODO: No external globals for now.
458  if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
459
460  // TODO: Need more magic for ARM PIC.
461  if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
462
463  // MachineConstantPool wants an explicit alignment.
464  unsigned Align = TD.getPrefTypeAlignment(GV->getType());
465  if (Align == 0) {
466    // TODO: Figure out if this is correct.
467    Align = TD.getTypeAllocSize(GV->getType());
468  }
469
470  // Grab index.
471  unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
472  unsigned Id = AFI->createConstPoolEntryUId();
473  ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
474                                                       ARMCP::CPValue, PCAdj);
475  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
476
477  // Load value.
478  MachineInstrBuilder MIB;
479  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
480  if (isThumb) {
481    unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
482    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
483          .addConstantPoolIndex(Idx);
484    if (RelocM == Reloc::PIC_)
485      MIB.addImm(Id);
486  } else {
487    // The extra reg and immediate are for addrmode2.
488    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
489                  DestReg)
490          .addConstantPoolIndex(Idx)
491          .addReg(0).addImm(0);
492  }
493  AddOptionalDefs(MIB);
494  return DestReg;
495}
496
497unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
498  EVT VT = TLI.getValueType(C->getType(), true);
499
500  // Only handle simple types.
501  if (!VT.isSimple()) return 0;
502
503  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
504    return ARMMaterializeFP(CFP, VT);
505  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
506    return ARMMaterializeGV(GV, VT);
507  else if (isa<ConstantInt>(C))
508    return ARMMaterializeInt(C, VT);
509
510  return 0;
511}
512
513unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
514  // Don't handle dynamic allocas.
515  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
516
517  EVT VT;
518  if (!isTypeLegal(AI->getType(), VT)) return false;
519
520  DenseMap<const AllocaInst*, int>::iterator SI =
521    FuncInfo.StaticAllocaMap.find(AI);
522
523  // This will get lowered later into the correct offsets and registers
524  // via rewriteXFrameIndex.
525  if (SI != FuncInfo.StaticAllocaMap.end()) {
526    TargetRegisterClass* RC = TLI.getRegClassFor(VT);
527    unsigned ResultReg = createResultReg(RC);
528    unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
529    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
530                            TII.get(Opc), ResultReg)
531                            .addFrameIndex(SI->second)
532                            .addImm(0));
533    return ResultReg;
534  }
535
536  return 0;
537}
538
539bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
540  VT = TLI.getValueType(Ty, true);
541
542  // Only handle simple types.
543  if (VT == MVT::Other || !VT.isSimple()) return false;
544
545  // Handle all legal types, i.e. a register that will directly hold this
546  // value.
547  return TLI.isTypeLegal(VT);
548}
549
550bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
551  if (isTypeLegal(Ty, VT)) return true;
552
553  // If this is a type than can be sign or zero-extended to a basic operation
554  // go ahead and accept it now.
555  if (VT == MVT::i8 || VT == MVT::i16)
556    return true;
557
558  return false;
559}
560
561// Computes the Reg+Offset to get to an object.
562bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
563                                      int &Offset) {
564  // Some boilerplate from the X86 FastISel.
565  const User *U = NULL;
566  unsigned Opcode = Instruction::UserOp1;
567  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
568    // Don't walk into other basic blocks; it's possible we haven't
569    // visited them yet, so the instructions may not yet be assigned
570    // virtual registers.
571    if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
572      return false;
573    Opcode = I->getOpcode();
574    U = I;
575  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
576    Opcode = C->getOpcode();
577    U = C;
578  }
579
580  if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
581    if (Ty->getAddressSpace() > 255)
582      // Fast instruction selection doesn't support the special
583      // address spaces.
584      return false;
585
586  switch (Opcode) {
587    default:
588    break;
589    case Instruction::Alloca: {
590      assert(false && "Alloca should have been handled earlier!");
591      return false;
592    }
593  }
594
595  // FIXME: Handle global variables.
596  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
597    (void)GV;
598    return false;
599  }
600
601  // Try to get this in a register if nothing else has worked.
602  Reg = getRegForValue(Obj);
603  if (Reg == 0) return false;
604
605  // Since the offset may be too large for the load instruction
606  // get the reg+offset into a register.
607  // TODO: Verify the additions work, otherwise we'll need to add the
608  // offset instead of 0 to the instructions and do all sorts of operand
609  // munging.
610  // TODO: Optimize this somewhat.
611  if (Offset != 0) {
612    ARMCC::CondCodes Pred = ARMCC::AL;
613    unsigned PredReg = 0;
614
615    if (!isThumb)
616      emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
617                              Reg, Reg, Offset, Pred, PredReg,
618                              static_cast<const ARMBaseInstrInfo&>(TII));
619    else {
620      assert(AFI->isThumb2Function());
621      emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
622                             Reg, Reg, Offset, Pred, PredReg,
623                             static_cast<const ARMBaseInstrInfo&>(TII));
624    }
625  }
626  return true;
627}
628
629bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
630  Value *Op0 = I->getOperand(0);
631
632  // Verify it's an alloca.
633  if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
634    DenseMap<const AllocaInst*, int>::iterator SI =
635      FuncInfo.StaticAllocaMap.find(AI);
636
637    if (SI != FuncInfo.StaticAllocaMap.end()) {
638      TargetRegisterClass* RC = TLI.getRegClassFor(VT);
639      unsigned ResultReg = createResultReg(RC);
640      TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
641                               ResultReg, SI->second, RC,
642                               TM.getRegisterInfo());
643      UpdateValueMap(I, ResultReg);
644      return true;
645    }
646  }
647  return false;
648}
649
650bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
651                              unsigned Reg, int Offset) {
652
653  assert(VT.isSimple() && "Non-simple types are invalid here!");
654  unsigned Opc;
655  bool isFloat = false;
656  switch (VT.getSimpleVT().SimpleTy) {
657    default:
658      // This is mostly going to be Neon/vector support.
659      return false;
660    case MVT::i16:
661      Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
662      VT = MVT::i32;
663      break;
664    case MVT::i8:
665      Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
666      VT = MVT::i32;
667      break;
668    case MVT::i32:
669      Opc = isThumb ? ARM::tLDR : ARM::LDR;
670      break;
671    case MVT::f32:
672      Opc = ARM::VLDRS;
673      isFloat = true;
674      break;
675    case MVT::f64:
676      Opc = ARM::VLDRD;
677      isFloat = true;
678      break;
679  }
680
681  ResultReg = createResultReg(TLI.getRegClassFor(VT));
682
683  // TODO: Fix the Addressing modes so that these can share some code.
684  // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
685  // The thumb addressing mode has operands swapped from the arm addressing
686  // mode, the floating point one only has two operands.
687  if (isFloat)
688    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
689                            TII.get(Opc), ResultReg)
690                    .addReg(Reg).addImm(Offset));
691  else if (isThumb)
692    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
693                            TII.get(Opc), ResultReg)
694                    .addReg(Reg).addImm(Offset).addReg(0));
695  else
696    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
697                            TII.get(Opc), ResultReg)
698                    .addReg(Reg).addReg(0).addImm(Offset));
699  return true;
700}
701
702bool ARMFastISel::SelectLoad(const Instruction *I) {
703  // Verify we have a legal type before going any further.
704  EVT VT;
705  if (!isLoadTypeLegal(I->getType(), VT))
706    return false;
707
708  // If we're an alloca we know we have a frame index and can emit the load
709  // directly in short order.
710  if (ARMLoadAlloca(I, VT))
711    return true;
712
713  // Our register and offset with innocuous defaults.
714  unsigned Reg = 0;
715  int Offset = 0;
716
717  // See if we can handle this as Reg + Offset
718  if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
719    return false;
720
721  unsigned ResultReg;
722  if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
723
724  UpdateValueMap(I, ResultReg);
725  return true;
726}
727
728bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
729  Value *Op1 = I->getOperand(1);
730
731  // Verify it's an alloca.
732  if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
733    DenseMap<const AllocaInst*, int>::iterator SI =
734      FuncInfo.StaticAllocaMap.find(AI);
735
736    if (SI != FuncInfo.StaticAllocaMap.end()) {
737      TargetRegisterClass* RC = TLI.getRegClassFor(VT);
738      assert(SrcReg != 0 && "Nothing to store!");
739      TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
740                              SrcReg, true /*isKill*/, SI->second, RC,
741                              TM.getRegisterInfo());
742      return true;
743    }
744  }
745  return false;
746}
747
748bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
749                               unsigned DstReg, int Offset) {
750  unsigned StrOpc;
751  bool isFloat = false;
752  switch (VT.getSimpleVT().SimpleTy) {
753    default: return false;
754    case MVT::i1:
755    case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
756    case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
757    case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
758    case MVT::f32:
759      if (!Subtarget->hasVFP2()) return false;
760      StrOpc = ARM::VSTRS;
761      isFloat = true;
762      break;
763    case MVT::f64:
764      if (!Subtarget->hasVFP2()) return false;
765      StrOpc = ARM::VSTRD;
766      isFloat = true;
767      break;
768  }
769
770  // The thumb addressing mode has operands swapped from the arm addressing
771  // mode, the floating point one only has two operands.
772  if (isFloat)
773    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
774                            TII.get(StrOpc))
775                    .addReg(SrcReg).addReg(DstReg).addImm(Offset));
776  else if (isThumb)
777    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
778                            TII.get(StrOpc))
779                    .addReg(SrcReg).addReg(DstReg).addImm(Offset).addReg(0));
780
781  else
782    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
783                            TII.get(StrOpc))
784                    .addReg(SrcReg).addReg(DstReg).addReg(0).addImm(Offset));
785
786  return true;
787}
788
789bool ARMFastISel::SelectStore(const Instruction *I) {
790  Value *Op0 = I->getOperand(0);
791  unsigned SrcReg = 0;
792
793  // Yay type legalization
794  EVT VT;
795  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
796    return false;
797
798  // Get the value to be stored into a register.
799  SrcReg = getRegForValue(Op0);
800  if (SrcReg == 0)
801    return false;
802
803  // If we're an alloca we know we have a frame index and can emit the store
804  // quickly.
805  if (ARMStoreAlloca(I, SrcReg, VT))
806    return true;
807
808  // Our register and offset with innocuous defaults.
809  unsigned Reg = 0;
810  int Offset = 0;
811
812  // See if we can handle this as Reg + Offset
813  if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
814    return false;
815
816  if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
817
818  return true;
819}
820
821static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
822  switch (Pred) {
823    // Needs two compares...
824    case CmpInst::FCMP_ONE:
825    case CmpInst::FCMP_UEQ:
826    default:
827      assert(false && "Unhandled CmpInst::Predicate!");
828      return ARMCC::AL;
829    case CmpInst::ICMP_EQ:
830    case CmpInst::FCMP_OEQ:
831      return ARMCC::EQ;
832    case CmpInst::ICMP_SGT:
833    case CmpInst::FCMP_OGT:
834      return ARMCC::GT;
835    case CmpInst::ICMP_SGE:
836    case CmpInst::FCMP_OGE:
837      return ARMCC::GE;
838    case CmpInst::ICMP_UGT:
839    case CmpInst::FCMP_UGT:
840      return ARMCC::HI;
841    case CmpInst::FCMP_OLT:
842      return ARMCC::MI;
843    case CmpInst::ICMP_ULE:
844    case CmpInst::FCMP_OLE:
845      return ARMCC::LS;
846    case CmpInst::FCMP_ORD:
847      return ARMCC::VC;
848    case CmpInst::FCMP_UNO:
849      return ARMCC::VS;
850    case CmpInst::FCMP_UGE:
851      return ARMCC::PL;
852    case CmpInst::ICMP_SLT:
853    case CmpInst::FCMP_ULT:
854      return ARMCC::LT;
855    case CmpInst::ICMP_SLE:
856    case CmpInst::FCMP_ULE:
857      return ARMCC::LE;
858    case CmpInst::FCMP_UNE:
859    case CmpInst::ICMP_NE:
860      return ARMCC::NE;
861    case CmpInst::ICMP_UGE:
862      return ARMCC::HS;
863    case CmpInst::ICMP_ULT:
864      return ARMCC::LO;
865  }
866}
867
868bool ARMFastISel::SelectBranch(const Instruction *I) {
869  const BranchInst *BI = cast<BranchInst>(I);
870  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
871  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
872
873  // Simple branch support.
874  // TODO: Try to avoid the re-computation in some places.
875  unsigned CondReg = getRegForValue(BI->getCondition());
876  if (CondReg == 0) return false;
877
878  // Re-set the flags just in case.
879  unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
880  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
881                  .addReg(CondReg).addImm(1));
882
883  unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
884  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
885                  .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
886  FastEmitBranch(FBB, DL);
887  FuncInfo.MBB->addSuccessor(TBB);
888  return true;
889}
890
891bool ARMFastISel::SelectCmp(const Instruction *I) {
892  const CmpInst *CI = cast<CmpInst>(I);
893
894  EVT VT;
895  const Type *Ty = CI->getOperand(0)->getType();
896  if (!isTypeLegal(Ty, VT))
897    return false;
898
899  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
900  if (isFloat && !Subtarget->hasVFP2())
901    return false;
902
903  unsigned CmpOpc;
904  unsigned CondReg;
905  switch (VT.getSimpleVT().SimpleTy) {
906    default: return false;
907    // TODO: Verify compares.
908    case MVT::f32:
909      CmpOpc = ARM::VCMPES;
910      CondReg = ARM::FPSCR;
911      break;
912    case MVT::f64:
913      CmpOpc = ARM::VCMPED;
914      CondReg = ARM::FPSCR;
915      break;
916    case MVT::i32:
917      CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
918      CondReg = ARM::CPSR;
919      break;
920  }
921
922  // Get the compare predicate.
923  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
924
925  // We may not handle every CC for now.
926  if (ARMPred == ARMCC::AL) return false;
927
928  unsigned Arg1 = getRegForValue(CI->getOperand(0));
929  if (Arg1 == 0) return false;
930
931  unsigned Arg2 = getRegForValue(CI->getOperand(1));
932  if (Arg2 == 0) return false;
933
934  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
935                  .addReg(Arg1).addReg(Arg2));
936
937  // For floating point we need to move the result to a comparison register
938  // that we can then use for branches.
939  if (isFloat)
940    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
941                            TII.get(ARM::FMSTAT)));
942
943  // Now set a register based on the comparison. Explicitly set the predicates
944  // here.
945  unsigned MovCCOpc = isThumb ? ARM::tMOVCCi : ARM::MOVCCi;
946  unsigned DestReg = createResultReg(ARM::GPRRegisterClass);
947  Constant *Zero
948    = ConstantInt::get(Type::getInt32Ty(*Context), 0);
949  unsigned ZeroReg = TargetMaterializeConstant(Zero);
950  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
951          .addReg(ZeroReg).addImm(1)
952          .addImm(ARMPred).addReg(CondReg);
953
954  UpdateValueMap(I, DestReg);
955  return true;
956}
957
958bool ARMFastISel::SelectFPExt(const Instruction *I) {
959  // Make sure we have VFP and that we're extending float to double.
960  if (!Subtarget->hasVFP2()) return false;
961
962  Value *V = I->getOperand(0);
963  if (!I->getType()->isDoubleTy() ||
964      !V->getType()->isFloatTy()) return false;
965
966  unsigned Op = getRegForValue(V);
967  if (Op == 0) return false;
968
969  unsigned Result = createResultReg(ARM::DPRRegisterClass);
970  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
971                          TII.get(ARM::VCVTDS), Result)
972                  .addReg(Op));
973  UpdateValueMap(I, Result);
974  return true;
975}
976
977bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
978  // Make sure we have VFP and that we're truncating double to float.
979  if (!Subtarget->hasVFP2()) return false;
980
981  Value *V = I->getOperand(0);
982  if (!(I->getType()->isFloatTy() &&
983        V->getType()->isDoubleTy())) return false;
984
985  unsigned Op = getRegForValue(V);
986  if (Op == 0) return false;
987
988  unsigned Result = createResultReg(ARM::SPRRegisterClass);
989  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
990                          TII.get(ARM::VCVTSD), Result)
991                  .addReg(Op));
992  UpdateValueMap(I, Result);
993  return true;
994}
995
996bool ARMFastISel::SelectSIToFP(const Instruction *I) {
997  // Make sure we have VFP.
998  if (!Subtarget->hasVFP2()) return false;
999
1000  EVT DstVT;
1001  const Type *Ty = I->getType();
1002  if (!isTypeLegal(Ty, DstVT))
1003    return false;
1004
1005  unsigned Op = getRegForValue(I->getOperand(0));
1006  if (Op == 0) return false;
1007
1008  // The conversion routine works on fp-reg to fp-reg and the operand above
1009  // was an integer, move it to the fp registers if possible.
1010  unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1011  if (FP == 0) return false;
1012
1013  unsigned Opc;
1014  if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1015  else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1016  else return 0;
1017
1018  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1019  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1020                          ResultReg)
1021                  .addReg(FP));
1022  UpdateValueMap(I, ResultReg);
1023  return true;
1024}
1025
1026bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1027  // Make sure we have VFP.
1028  if (!Subtarget->hasVFP2()) return false;
1029
1030  EVT DstVT;
1031  const Type *RetTy = I->getType();
1032  if (!isTypeLegal(RetTy, DstVT))
1033    return false;
1034
1035  unsigned Op = getRegForValue(I->getOperand(0));
1036  if (Op == 0) return false;
1037
1038  unsigned Opc;
1039  const Type *OpTy = I->getOperand(0)->getType();
1040  if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1041  else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1042  else return 0;
1043
1044  // f64->s32 or f32->s32 both need an intermediate f32 reg.
1045  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1046  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1047                          ResultReg)
1048                  .addReg(Op));
1049
1050  // This result needs to be in an integer register, but the conversion only
1051  // takes place in fp-regs.
1052  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1053  if (IntReg == 0) return false;
1054
1055  UpdateValueMap(I, IntReg);
1056  return true;
1057}
1058
1059bool ARMFastISel::SelectSDiv(const Instruction *I) {
1060  EVT VT;
1061  const Type *Ty = I->getType();
1062  if (!isTypeLegal(Ty, VT))
1063    return false;
1064
1065  // If we have integer div support we should have selected this automagically.
1066  // In case we have a real miss go ahead and return false and we'll pick
1067  // it up later.
1068  if (Subtarget->hasDivide()) return false;
1069
1070  // Otherwise emit a libcall.
1071  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1072  if (VT == MVT::i16)
1073    LC = RTLIB::SDIV_I16;
1074  else if (VT == MVT::i32)
1075    LC = RTLIB::SDIV_I32;
1076  else if (VT == MVT::i64)
1077    LC = RTLIB::SDIV_I64;
1078  else if (VT == MVT::i128)
1079    LC = RTLIB::SDIV_I128;
1080  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1081
1082  return ARMEmitLibcall(I, LC);
1083}
1084
1085bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1086  EVT VT  = TLI.getValueType(I->getType(), true);
1087
1088  // We can get here in the case when we want to use NEON for our fp
1089  // operations, but can't figure out how to. Just use the vfp instructions
1090  // if we have them.
1091  // FIXME: It'd be nice to use NEON instructions.
1092  const Type *Ty = I->getType();
1093  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1094  if (isFloat && !Subtarget->hasVFP2())
1095    return false;
1096
1097  unsigned Op1 = getRegForValue(I->getOperand(0));
1098  if (Op1 == 0) return false;
1099
1100  unsigned Op2 = getRegForValue(I->getOperand(1));
1101  if (Op2 == 0) return false;
1102
1103  unsigned Opc;
1104  bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1105                 VT.getSimpleVT().SimpleTy == MVT::i64;
1106  switch (ISDOpcode) {
1107    default: return false;
1108    case ISD::FADD:
1109      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1110      break;
1111    case ISD::FSUB:
1112      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1113      break;
1114    case ISD::FMUL:
1115      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1116      break;
1117  }
1118  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1119  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1120                          TII.get(Opc), ResultReg)
1121                  .addReg(Op1).addReg(Op2));
1122  UpdateValueMap(I, ResultReg);
1123  return true;
1124}
1125
1126// Call Handling Code
1127
1128// This is largely taken directly from CCAssignFnForNode - we don't support
1129// varargs in FastISel so that part has been removed.
1130// TODO: We may not support all of this.
1131CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1132  switch (CC) {
1133  default:
1134    llvm_unreachable("Unsupported calling convention");
1135  case CallingConv::C:
1136  case CallingConv::Fast:
1137    // Use target triple & subtarget features to do actual dispatch.
1138    if (Subtarget->isAAPCS_ABI()) {
1139      if (Subtarget->hasVFP2() &&
1140          FloatABIType == FloatABI::Hard)
1141        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1142      else
1143        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1144    } else
1145        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1146  case CallingConv::ARM_AAPCS_VFP:
1147    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1148  case CallingConv::ARM_AAPCS:
1149    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1150  case CallingConv::ARM_APCS:
1151    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1152  }
1153}
1154
1155bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1156                                  SmallVectorImpl<unsigned> &ArgRegs,
1157                                  SmallVectorImpl<EVT> &ArgVTs,
1158                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1159                                  SmallVectorImpl<unsigned> &RegArgs,
1160                                  CallingConv::ID CC,
1161                                  unsigned &NumBytes) {
1162  SmallVector<CCValAssign, 16> ArgLocs;
1163  CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1164  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1165
1166  // Get a count of how many bytes are to be pushed on the stack.
1167  NumBytes = CCInfo.getNextStackOffset();
1168
1169  // Issue CALLSEQ_START
1170  unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1171  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1172          .addImm(NumBytes);
1173
1174  // Process the args.
1175  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1176    CCValAssign &VA = ArgLocs[i];
1177    unsigned Arg = ArgRegs[VA.getValNo()];
1178    EVT ArgVT = ArgVTs[VA.getValNo()];
1179
1180    // Handle arg promotion, etc.
1181    switch (VA.getLocInfo()) {
1182      case CCValAssign::Full: break;
1183      default:
1184      assert(false && "Handle arg promotion.");
1185      return false;
1186    }
1187
1188    // Now copy/store arg to correct locations.
1189    if (VA.isRegLoc()) {
1190      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1191              VA.getLocReg())
1192      .addReg(Arg);
1193      RegArgs.push_back(VA.getLocReg());
1194    } else {
1195      // Need to store
1196      return false;
1197    }
1198  }
1199
1200  return true;
1201}
1202
1203bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1204                             const Instruction *I, CallingConv::ID CC,
1205                             unsigned &NumBytes) {
1206  // Issue CALLSEQ_END
1207  unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1208  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1209          .addImm(NumBytes).addImm(0);
1210
1211  // Now the return value.
1212  if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1213    SmallVector<CCValAssign, 16> RVLocs;
1214    CCState CCInfo(CC, false, TM, RVLocs, *Context);
1215    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1216
1217    // Copy all of the result registers out of their specified physreg.
1218    if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) {
1219      // For this move we copy into two registers and then move into the
1220      // double fp reg we want.
1221      // TODO: Are the copies necessary?
1222      TargetRegisterClass *CopyRC = TLI.getRegClassFor(MVT::i32);
1223      unsigned Copy1 = createResultReg(CopyRC);
1224      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1225              Copy1).addReg(RVLocs[0].getLocReg());
1226      UsedRegs.push_back(RVLocs[0].getLocReg());
1227
1228      unsigned Copy2 = createResultReg(CopyRC);
1229      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1230              Copy2).addReg(RVLocs[1].getLocReg());
1231      UsedRegs.push_back(RVLocs[1].getLocReg());
1232
1233      EVT DestVT = RVLocs[0].getValVT();
1234      TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1235      unsigned ResultReg = createResultReg(DstRC);
1236      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1237                              TII.get(ARM::VMOVDRR), ResultReg)
1238                      .addReg(Copy1).addReg(Copy2));
1239
1240      // Finally update the result.
1241      UpdateValueMap(I, ResultReg);
1242    } else {
1243      assert(RVLocs.size() == 1 && "Can't handle non-double multi-reg retvals!");
1244      EVT CopyVT = RVLocs[0].getValVT();
1245      TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1246
1247      unsigned ResultReg = createResultReg(DstRC);
1248      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1249              ResultReg).addReg(RVLocs[0].getLocReg());
1250      UsedRegs.push_back(RVLocs[0].getLocReg());
1251
1252      // Finally update the result.
1253      UpdateValueMap(I, ResultReg);
1254    }
1255  }
1256
1257  return true;
1258}
1259
1260// A quick function that will emit a call for a named libcall in F with the
1261// vector of passed arguments for the Instruction in I. We can assume that we
1262// can emit a call for any libcall we can produce. This is an abridged version
1263// of the full call infrastructure since we won't need to worry about things
1264// like computed function pointers or strange arguments at call sites.
1265// TODO: Try to unify this and the normal call bits for ARM, then try to unify
1266// with X86.
1267bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1268  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1269
1270  // Handle *simple* calls for now.
1271  const Type *RetTy = I->getType();
1272  EVT RetVT;
1273  if (RetTy->isVoidTy())
1274    RetVT = MVT::isVoid;
1275  else if (!isTypeLegal(RetTy, RetVT))
1276    return false;
1277
1278  // For now we're using BLX etc on the assumption that we have v5t ops.
1279  if (!Subtarget->hasV5TOps()) return false;
1280
1281  // Set up the argument vectors.
1282  SmallVector<Value*, 8> Args;
1283  SmallVector<unsigned, 8> ArgRegs;
1284  SmallVector<EVT, 8> ArgVTs;
1285  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1286  Args.reserve(I->getNumOperands());
1287  ArgRegs.reserve(I->getNumOperands());
1288  ArgVTs.reserve(I->getNumOperands());
1289  ArgFlags.reserve(I->getNumOperands());
1290  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1291    Value *Op = I->getOperand(i);
1292    unsigned Arg = getRegForValue(Op);
1293    if (Arg == 0) return false;
1294
1295    const Type *ArgTy = Op->getType();
1296    EVT ArgVT;
1297    if (!isTypeLegal(ArgTy, ArgVT)) return false;
1298
1299    ISD::ArgFlagsTy Flags;
1300    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1301    Flags.setOrigAlign(OriginalAlignment);
1302
1303    Args.push_back(Op);
1304    ArgRegs.push_back(Arg);
1305    ArgVTs.push_back(ArgVT);
1306    ArgFlags.push_back(Flags);
1307  }
1308
1309  // Handle the arguments now that we've gotten them.
1310  SmallVector<unsigned, 4> RegArgs;
1311  unsigned NumBytes;
1312  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1313    return false;
1314
1315  // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1316  // TODO: Turn this into the table of arm call ops.
1317  MachineInstrBuilder MIB;
1318  unsigned CallOpc;
1319  if(isThumb)
1320    CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1321  else
1322    CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1323  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1324        .addExternalSymbol(TLI.getLibcallName(Call));
1325
1326  // Add implicit physical register uses to the call.
1327  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1328    MIB.addReg(RegArgs[i]);
1329
1330  // Finish off the call including any return values.
1331  SmallVector<unsigned, 4> UsedRegs;
1332  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1333
1334  // Set all unused physreg defs as dead.
1335  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1336
1337  return true;
1338}
1339
1340bool ARMFastISel::SelectCall(const Instruction *I) {
1341  const CallInst *CI = cast<CallInst>(I);
1342  const Value *Callee = CI->getCalledValue();
1343
1344  // Can't handle inline asm or worry about intrinsics yet.
1345  if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1346
1347  // Only handle global variable Callees that are direct calls.
1348  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1349  if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1350    return false;
1351
1352  // Check the calling convention.
1353  ImmutableCallSite CS(CI);
1354  CallingConv::ID CC = CS.getCallingConv();
1355  // TODO: Avoid some calling conventions?
1356  if (CC != CallingConv::C) {
1357    errs() << "Can't handle calling convention: " << CC << "\n";
1358    return false;
1359  }
1360
1361  // Let SDISel handle vararg functions.
1362  const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1363  const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1364  if (FTy->isVarArg())
1365    return false;
1366
1367  // Handle *simple* calls for now.
1368  const Type *RetTy = I->getType();
1369  EVT RetVT;
1370  if (RetTy->isVoidTy())
1371    RetVT = MVT::isVoid;
1372  else if (!isTypeLegal(RetTy, RetVT))
1373    return false;
1374
1375  // For now we're using BLX etc on the assumption that we have v5t ops.
1376  // TODO: Maybe?
1377  if (!Subtarget->hasV5TOps()) return false;
1378
1379  // Set up the argument vectors.
1380  SmallVector<Value*, 8> Args;
1381  SmallVector<unsigned, 8> ArgRegs;
1382  SmallVector<EVT, 8> ArgVTs;
1383  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1384  Args.reserve(CS.arg_size());
1385  ArgRegs.reserve(CS.arg_size());
1386  ArgVTs.reserve(CS.arg_size());
1387  ArgFlags.reserve(CS.arg_size());
1388  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1389       i != e; ++i) {
1390    unsigned Arg = getRegForValue(*i);
1391
1392    if (Arg == 0)
1393      return false;
1394    ISD::ArgFlagsTy Flags;
1395    unsigned AttrInd = i - CS.arg_begin() + 1;
1396    if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1397      Flags.setSExt();
1398    if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1399      Flags.setZExt();
1400
1401         // FIXME: Only handle *easy* calls for now.
1402    if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1403        CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1404        CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1405        CS.paramHasAttr(AttrInd, Attribute::ByVal))
1406      return false;
1407
1408    const Type *ArgTy = (*i)->getType();
1409    EVT ArgVT;
1410    if (!isTypeLegal(ArgTy, ArgVT))
1411      return false;
1412    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1413    Flags.setOrigAlign(OriginalAlignment);
1414
1415    Args.push_back(*i);
1416    ArgRegs.push_back(Arg);
1417    ArgVTs.push_back(ArgVT);
1418    ArgFlags.push_back(Flags);
1419  }
1420
1421  // Handle the arguments now that we've gotten them.
1422  SmallVector<unsigned, 4> RegArgs;
1423  unsigned NumBytes;
1424  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1425    return false;
1426
1427  // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1428  // TODO: Turn this into the table of arm call ops.
1429  MachineInstrBuilder MIB;
1430  unsigned CallOpc;
1431  if(isThumb)
1432    CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1433  else
1434    CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1435  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1436              .addGlobalAddress(GV, 0, 0);
1437
1438  // Add implicit physical register uses to the call.
1439  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1440    MIB.addReg(RegArgs[i]);
1441
1442  // Finish off the call including any return values.
1443  SmallVector<unsigned, 4> UsedRegs;
1444  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1445
1446  // Set all unused physreg defs as dead.
1447  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1448
1449  return true;
1450
1451}
1452
1453// TODO: SoftFP support.
1454bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1455  // No Thumb-1 for now.
1456  if (isThumb && !AFI->isThumb2Function()) return false;
1457
1458  switch (I->getOpcode()) {
1459    case Instruction::Load:
1460      return SelectLoad(I);
1461    case Instruction::Store:
1462      return SelectStore(I);
1463    case Instruction::Br:
1464      return SelectBranch(I);
1465    case Instruction::ICmp:
1466    case Instruction::FCmp:
1467      return SelectCmp(I);
1468    case Instruction::FPExt:
1469      return SelectFPExt(I);
1470    case Instruction::FPTrunc:
1471      return SelectFPTrunc(I);
1472    case Instruction::SIToFP:
1473      return SelectSIToFP(I);
1474    case Instruction::FPToSI:
1475      return SelectFPToSI(I);
1476    case Instruction::FAdd:
1477      return SelectBinaryOp(I, ISD::FADD);
1478    case Instruction::FSub:
1479      return SelectBinaryOp(I, ISD::FSUB);
1480    case Instruction::FMul:
1481      return SelectBinaryOp(I, ISD::FMUL);
1482    case Instruction::SDiv:
1483      return SelectSDiv(I);
1484    case Instruction::Call:
1485      return SelectCall(I);
1486    default: break;
1487  }
1488  return false;
1489}
1490
1491namespace llvm {
1492  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1493    if (EnableARMFastISel) return new ARMFastISel(funcInfo);
1494    return 0;
1495  }
1496}
1497