ARMFastISel.cpp revision 1f58741aabd00545468f4ecf29db3dba8e0bd6ac 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMRegisterInfo.h"
19#include "ARMTargetMachine.h"
20#include "ARMSubtarget.h"
21#include "llvm/CallingConv.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/GlobalVariable.h"
24#include "llvm/Instructions.h"
25#include "llvm/IntrinsicInst.h"
26#include "llvm/CodeGen/Analysis.h"
27#include "llvm/CodeGen/FastISel.h"
28#include "llvm/CodeGen/FunctionLoweringInfo.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineModuleInfo.h"
31#include "llvm/CodeGen/MachineConstantPool.h"
32#include "llvm/CodeGen/MachineFrameInfo.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/Support/CallSite.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/GetElementPtrTypeIterator.h"
38#include "llvm/Target/TargetData.h"
39#include "llvm/Target/TargetInstrInfo.h"
40#include "llvm/Target/TargetLowering.h"
41#include "llvm/Target/TargetMachine.h"
42#include "llvm/Target/TargetOptions.h"
43using namespace llvm;
44
45static cl::opt<bool>
46EnableARMFastISel("arm-fast-isel",
47                  cl::desc("Turn on experimental ARM fast-isel support"),
48                  cl::init(false), cl::Hidden);
49
50namespace {
51
52class ARMFastISel : public FastISel {
53
54  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55  /// make the right decision when generating code for different targets.
56  const ARMSubtarget *Subtarget;
57  const TargetMachine &TM;
58  const TargetInstrInfo &TII;
59  const TargetLowering &TLI;
60  const ARMFunctionInfo *AFI;
61
62  // Convenience variable to avoid checking all the time.
63  bool isThumb;
64
65  public:
66    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
67    : FastISel(funcInfo),
68      TM(funcInfo.MF->getTarget()),
69      TII(*TM.getInstrInfo()),
70      TLI(*TM.getTargetLowering()) {
71      Subtarget = &TM.getSubtarget<ARMSubtarget>();
72      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
73      isThumb = AFI->isThumbFunction();
74    }
75
76    // Code from FastISel.cpp.
77    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
78                                   const TargetRegisterClass *RC);
79    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
80                                    const TargetRegisterClass *RC,
81                                    unsigned Op0, bool Op0IsKill);
82    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
83                                     const TargetRegisterClass *RC,
84                                     unsigned Op0, bool Op0IsKill,
85                                     unsigned Op1, bool Op1IsKill);
86    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
87                                     const TargetRegisterClass *RC,
88                                     unsigned Op0, bool Op0IsKill,
89                                     uint64_t Imm);
90    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
91                                     const TargetRegisterClass *RC,
92                                     unsigned Op0, bool Op0IsKill,
93                                     const ConstantFP *FPImm);
94    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
95                                    const TargetRegisterClass *RC,
96                                    uint64_t Imm);
97    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
98                                      const TargetRegisterClass *RC,
99                                      unsigned Op0, bool Op0IsKill,
100                                      unsigned Op1, bool Op1IsKill,
101                                      uint64_t Imm);
102    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
103                                                unsigned Op0, bool Op0IsKill,
104                                                uint32_t Idx);
105
106    // Backend specific FastISel code.
107    virtual bool TargetSelectInstruction(const Instruction *I);
108    virtual unsigned TargetMaterializeConstant(const Constant *C);
109
110  #include "ARMGenFastISel.inc"
111
112    // Instruction selection routines.
113    virtual bool ARMSelectLoad(const Instruction *I);
114    virtual bool ARMSelectStore(const Instruction *I);
115
116    // Utility routines.
117  private:
118    bool isTypeLegal(const Type *Ty, EVT &VT);
119    bool isLoadTypeLegal(const Type *Ty, EVT &VT);
120    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
121    bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
122    bool ARMLoadAlloca(const Instruction *I);
123    bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg);
124    bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
125    bool ARMMaterializeConstant(const ConstantInt *Val, unsigned &Reg);
126
127    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
128    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
129};
130
131} // end anonymous namespace
132
133// #include "ARMGenCallingConv.inc"
134
135// DefinesOptionalPredicate - This is different from DefinesPredicate in that
136// we don't care about implicit defs here, just places we'll need to add a
137// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
138bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
139  const TargetInstrDesc &TID = MI->getDesc();
140  if (!TID.hasOptionalDef())
141    return false;
142
143  // Look to see if our OptionalDef is defining CPSR or CCR.
144  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
145    const MachineOperand &MO = MI->getOperand(i);
146    if (!MO.isReg() || !MO.isDef()) continue;
147    if (MO.getReg() == ARM::CPSR)
148      *CPSR = true;
149  }
150  return true;
151}
152
153// If the machine is predicable go ahead and add the predicate operands, if
154// it needs default CC operands add those.
155const MachineInstrBuilder &
156ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
157  MachineInstr *MI = &*MIB;
158
159  // Do we use a predicate?
160  if (TII.isPredicable(MI))
161    AddDefaultPred(MIB);
162
163  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
164  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
165  bool CPSR = false;
166  if (DefinesOptionalPredicate(MI, &CPSR)) {
167    if (CPSR)
168      AddDefaultT1CC(MIB);
169    else
170      AddDefaultCC(MIB);
171  }
172  return MIB;
173}
174
175unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
176                                    const TargetRegisterClass* RC) {
177  unsigned ResultReg = createResultReg(RC);
178  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
179
180  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
181  return ResultReg;
182}
183
184unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
185                                     const TargetRegisterClass *RC,
186                                     unsigned Op0, bool Op0IsKill) {
187  unsigned ResultReg = createResultReg(RC);
188  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
189
190  if (II.getNumDefs() >= 1)
191    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
192                   .addReg(Op0, Op0IsKill * RegState::Kill));
193  else {
194    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
195                   .addReg(Op0, Op0IsKill * RegState::Kill));
196    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
197                   TII.get(TargetOpcode::COPY), ResultReg)
198                   .addReg(II.ImplicitDefs[0]));
199  }
200  return ResultReg;
201}
202
203unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
204                                      const TargetRegisterClass *RC,
205                                      unsigned Op0, bool Op0IsKill,
206                                      unsigned Op1, bool Op1IsKill) {
207  unsigned ResultReg = createResultReg(RC);
208  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
209
210  if (II.getNumDefs() >= 1)
211    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
212                   .addReg(Op0, Op0IsKill * RegState::Kill)
213                   .addReg(Op1, Op1IsKill * RegState::Kill));
214  else {
215    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
216                   .addReg(Op0, Op0IsKill * RegState::Kill)
217                   .addReg(Op1, Op1IsKill * RegState::Kill));
218    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
219                           TII.get(TargetOpcode::COPY), ResultReg)
220                   .addReg(II.ImplicitDefs[0]));
221  }
222  return ResultReg;
223}
224
225unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
226                                      const TargetRegisterClass *RC,
227                                      unsigned Op0, bool Op0IsKill,
228                                      uint64_t Imm) {
229  unsigned ResultReg = createResultReg(RC);
230  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
231
232  if (II.getNumDefs() >= 1)
233    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
234                   .addReg(Op0, Op0IsKill * RegState::Kill)
235                   .addImm(Imm));
236  else {
237    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
238                   .addReg(Op0, Op0IsKill * RegState::Kill)
239                   .addImm(Imm));
240    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
241                           TII.get(TargetOpcode::COPY), ResultReg)
242                   .addReg(II.ImplicitDefs[0]));
243  }
244  return ResultReg;
245}
246
247unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
248                                      const TargetRegisterClass *RC,
249                                      unsigned Op0, bool Op0IsKill,
250                                      const ConstantFP *FPImm) {
251  unsigned ResultReg = createResultReg(RC);
252  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
253
254  if (II.getNumDefs() >= 1)
255    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
256                   .addReg(Op0, Op0IsKill * RegState::Kill)
257                   .addFPImm(FPImm));
258  else {
259    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
260                   .addReg(Op0, Op0IsKill * RegState::Kill)
261                   .addFPImm(FPImm));
262    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
263                           TII.get(TargetOpcode::COPY), ResultReg)
264                   .addReg(II.ImplicitDefs[0]));
265  }
266  return ResultReg;
267}
268
269unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
270                                       const TargetRegisterClass *RC,
271                                       unsigned Op0, bool Op0IsKill,
272                                       unsigned Op1, bool Op1IsKill,
273                                       uint64_t Imm) {
274  unsigned ResultReg = createResultReg(RC);
275  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
276
277  if (II.getNumDefs() >= 1)
278    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
279                   .addReg(Op0, Op0IsKill * RegState::Kill)
280                   .addReg(Op1, Op1IsKill * RegState::Kill)
281                   .addImm(Imm));
282  else {
283    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
284                   .addReg(Op0, Op0IsKill * RegState::Kill)
285                   .addReg(Op1, Op1IsKill * RegState::Kill)
286                   .addImm(Imm));
287    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
288                           TII.get(TargetOpcode::COPY), ResultReg)
289                   .addReg(II.ImplicitDefs[0]));
290  }
291  return ResultReg;
292}
293
294unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
295                                     const TargetRegisterClass *RC,
296                                     uint64_t Imm) {
297  unsigned ResultReg = createResultReg(RC);
298  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
299
300  if (II.getNumDefs() >= 1)
301    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
302                   .addImm(Imm));
303  else {
304    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
305                   .addImm(Imm));
306    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
307                           TII.get(TargetOpcode::COPY), ResultReg)
308                   .addReg(II.ImplicitDefs[0]));
309  }
310  return ResultReg;
311}
312
313unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
314                                                 unsigned Op0, bool Op0IsKill,
315                                                 uint32_t Idx) {
316  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
317  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
318         "Cannot yet extract from physregs");
319  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
320                         DL, TII.get(TargetOpcode::COPY), ResultReg)
321                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
322  return ResultReg;
323}
324
325unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
326  // TODO: Implement this for floating point constants and integer constants
327  // if we care about non-v6 architectures.
328  return 0;
329}
330
331bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
332  VT = TLI.getValueType(Ty, true);
333
334  // Only handle simple types.
335  if (VT == MVT::Other || !VT.isSimple()) return false;
336
337  // Handle all legal types, i.e. a register that will directly hold this
338  // value.
339  return TLI.isTypeLegal(VT);
340}
341
342bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
343  if (isTypeLegal(Ty, VT)) return true;
344
345  // If this is a type than can be sign or zero-extended to a basic operation
346  // go ahead and accept it now.
347  if (VT == MVT::i8 || VT == MVT::i16)
348    return true;
349
350  return false;
351}
352
353// Computes the Reg+Offset to get to an object.
354bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
355                                      int &Offset) {
356  // Some boilerplate from the X86 FastISel.
357  const User *U = NULL;
358  unsigned Opcode = Instruction::UserOp1;
359  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
360    // Don't walk into other basic blocks; it's possible we haven't
361    // visited them yet, so the instructions may not yet be assigned
362    // virtual registers.
363    if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
364      return false;
365
366    Opcode = I->getOpcode();
367    U = I;
368  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
369    Opcode = C->getOpcode();
370    U = C;
371  }
372
373  if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
374    if (Ty->getAddressSpace() > 255)
375      // Fast instruction selection doesn't support the special
376      // address spaces.
377      return false;
378
379  switch (Opcode) {
380    default:
381    //errs() << "Failing Opcode is: " << *Op1 << "\n";
382    break;
383    case Instruction::Alloca: {
384      assert(false && "Alloca should have been handled earlier!");
385      return false;
386    }
387  }
388
389  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
390    //errs() << "Failing GV is: " << GV << "\n";
391    (void)GV;
392    return false;
393  }
394
395  // Try to get this in a register if nothing else has worked.
396  Reg = getRegForValue(Obj);
397  if (Reg == 0) return false;
398
399  // Since the offset may be too large for the load instruction
400  // get the reg+offset into a register.
401  // TODO: Verify the additions work, otherwise we'll need to add the
402  // offset instead of 0 to the instructions and do all sorts of operand
403  // munging.
404  // TODO: Optimize this somewhat.
405  if (Offset != 0) {
406    ARMCC::CondCodes Pred = ARMCC::AL;
407    unsigned PredReg = 0;
408
409    if (!isThumb)
410      emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
411                              Reg, Reg, Offset, Pred, PredReg,
412                              static_cast<const ARMBaseInstrInfo&>(TII));
413    else {
414      assert(AFI->isThumb2Function());
415      emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
416                             Reg, Reg, Offset, Pred, PredReg,
417                             static_cast<const ARMBaseInstrInfo&>(TII));
418    }
419  }
420
421  return true;
422}
423
424bool ARMFastISel::ARMLoadAlloca(const Instruction *I) {
425  Value *Op0 = I->getOperand(0);
426
427  // Verify it's an alloca.
428  if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
429    DenseMap<const AllocaInst*, int>::iterator SI =
430      FuncInfo.StaticAllocaMap.find(AI);
431
432    if (SI != FuncInfo.StaticAllocaMap.end()) {
433      TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
434      unsigned ResultReg = createResultReg(RC);
435      TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
436                               ResultReg, SI->second, RC,
437                               TM.getRegisterInfo());
438      UpdateValueMap(I, ResultReg);
439      return true;
440    }
441  }
442  return false;
443}
444
445bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
446                              unsigned Reg, int Offset) {
447
448  assert(VT.isSimple() && "Non-simple types are invalid here!");
449  unsigned Opc;
450
451  switch (VT.getSimpleVT().SimpleTy) {
452    default:
453      assert(false && "Trying to emit for an unhandled type!");
454      return false;
455    case MVT::i16:
456      Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
457      VT = MVT::i32;
458      break;
459    case MVT::i8:
460      Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
461      VT = MVT::i32;
462      break;
463    case MVT::i32:
464      Opc = isThumb ? ARM::tLDR : ARM::LDR;
465      break;
466  }
467
468  ResultReg = createResultReg(TLI.getRegClassFor(VT));
469
470  // TODO: Fix the Addressing modes so that these can share some code.
471  // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
472  if (isThumb)
473    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
474                            TII.get(Opc), ResultReg)
475                    .addReg(Reg).addImm(Offset).addReg(0));
476  else
477    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
478                            TII.get(Opc), ResultReg)
479                    .addReg(Reg).addReg(0).addImm(Offset));
480
481  return true;
482}
483
484bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg) {
485  Value *Op1 = I->getOperand(1);
486
487  // Verify it's an alloca.
488  if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
489    DenseMap<const AllocaInst*, int>::iterator SI =
490      FuncInfo.StaticAllocaMap.find(AI);
491
492    if (SI != FuncInfo.StaticAllocaMap.end()) {
493      TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
494      assert(SrcReg != 0 && "Nothing to store!");
495      TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
496                              SrcReg, true /*isKill*/, SI->second, RC,
497                              TM.getRegisterInfo());
498      return true;
499    }
500  }
501  return false;
502}
503
504bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
505                               unsigned DstReg, int Offset) {
506  unsigned StrOpc;
507  switch (VT.getSimpleVT().SimpleTy) {
508    default: return false;
509    case MVT::i1:
510    case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
511    case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
512    case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
513  }
514
515  if (isThumb)
516    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
517                            TII.get(StrOpc), SrcReg)
518                    .addReg(DstReg).addImm(Offset).addReg(0));
519  else
520    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
521                            TII.get(StrOpc), SrcReg)
522                    .addReg(DstReg).addReg(0).addImm(Offset));
523
524  return true;
525}
526
527bool ARMFastISel::ARMSelectStore(const Instruction *I) {
528  Value *Op0 = I->getOperand(0);
529  unsigned SrcReg = 0;
530
531  // Yay type legalization
532  EVT VT;
533  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
534    return false;
535
536  // Get the value to be stored into a register.
537  SrcReg = getRegForValue(Op0);
538  if (SrcReg == 0)
539    return false;
540
541  // If we're an alloca we know we have a frame index and can emit the store
542  // quickly.
543  if (ARMStoreAlloca(I, SrcReg))
544    return true;
545
546  // Our register and offset with innocuous defaults.
547  unsigned Reg = 0;
548  int Offset = 0;
549
550  // See if we can handle this as Reg + Offset
551  if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
552    return false;
553
554  if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
555
556  return false;
557
558}
559
560bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
561  // If we're an alloca we know we have a frame index and can emit the load
562  // directly in short order.
563  if (ARMLoadAlloca(I))
564    return true;
565
566  // Verify we have a legal type before going any further.
567  EVT VT;
568  if (!isLoadTypeLegal(I->getType(), VT))
569    return false;
570
571  // Our register and offset with innocuous defaults.
572  unsigned Reg = 0;
573  int Offset = 0;
574
575  // See if we can handle this as Reg + Offset
576  if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
577    return false;
578
579  unsigned ResultReg;
580  if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
581
582  UpdateValueMap(I, ResultReg);
583  return true;
584}
585
586bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
587  // No Thumb-1 for now.
588  if (isThumb && !AFI->isThumb2Function()) return false;
589
590  switch (I->getOpcode()) {
591    case Instruction::Load:
592      return ARMSelectLoad(I);
593    case Instruction::Store:
594      return ARMSelectStore(I);
595    default: break;
596  }
597  return false;
598}
599
600namespace llvm {
601  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
602    if (EnableARMFastISel) return new ARMFastISel(funcInfo);
603    return 0;
604  }
605}
606