ARMFastISel.cpp revision 530f7cefd3082e8aaa74b7d65636f30d0312b6ec 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMRegisterInfo.h"
20#include "ARMTargetMachine.h"
21#include "ARMSubtarget.h"
22#include "ARMConstantPoolValue.h"
23#include "MCTargetDesc/ARMAddressingModes.h"
24#include "llvm/CallingConv.h"
25#include "llvm/DerivedTypes.h"
26#include "llvm/GlobalVariable.h"
27#include "llvm/Instructions.h"
28#include "llvm/IntrinsicInst.h"
29#include "llvm/Module.h"
30#include "llvm/Operator.h"
31#include "llvm/CodeGen/Analysis.h"
32#include "llvm/CodeGen/FastISel.h"
33#include "llvm/CodeGen/FunctionLoweringInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineModuleInfo.h"
36#include "llvm/CodeGen/MachineConstantPool.h"
37#include "llvm/CodeGen/MachineFrameInfo.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/MachineRegisterInfo.h"
40#include "llvm/CodeGen/PseudoSourceValue.h"
41#include "llvm/Support/CallSite.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/GetElementPtrTypeIterator.h"
45#include "llvm/Target/TargetData.h"
46#include "llvm/Target/TargetInstrInfo.h"
47#include "llvm/Target/TargetLowering.h"
48#include "llvm/Target/TargetMachine.h"
49#include "llvm/Target/TargetOptions.h"
50using namespace llvm;
51
52static cl::opt<bool>
53DisableARMFastISel("disable-arm-fast-isel",
54                    cl::desc("Turn off experimental ARM fast-isel support"),
55                    cl::init(false), cl::Hidden);
56
57extern cl::opt<bool> EnableARMLongCalls;
58
59namespace {
60
61  // All possible address modes, plus some.
62  typedef struct Address {
63    enum {
64      RegBase,
65      FrameIndexBase
66    } BaseType;
67
68    union {
69      unsigned Reg;
70      int FI;
71    } Base;
72
73    int Offset;
74
75    // Innocuous defaults for our address.
76    Address()
77     : BaseType(RegBase), Offset(0) {
78       Base.Reg = 0;
79     }
80  } Address;
81
82class ARMFastISel : public FastISel {
83
84  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
85  /// make the right decision when generating code for different targets.
86  const ARMSubtarget *Subtarget;
87  const TargetMachine &TM;
88  const TargetInstrInfo &TII;
89  const TargetLowering &TLI;
90  ARMFunctionInfo *AFI;
91
92  // Convenience variables to avoid some queries.
93  bool isThumb;
94  LLVMContext *Context;
95
96  public:
97    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
98    : FastISel(funcInfo),
99      TM(funcInfo.MF->getTarget()),
100      TII(*TM.getInstrInfo()),
101      TLI(*TM.getTargetLowering()) {
102      Subtarget = &TM.getSubtarget<ARMSubtarget>();
103      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
104      isThumb = AFI->isThumbFunction();
105      Context = &funcInfo.Fn->getContext();
106    }
107
108    // Code from FastISel.cpp.
109    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
110                                   const TargetRegisterClass *RC);
111    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
112                                    const TargetRegisterClass *RC,
113                                    unsigned Op0, bool Op0IsKill);
114    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
115                                     const TargetRegisterClass *RC,
116                                     unsigned Op0, bool Op0IsKill,
117                                     unsigned Op1, bool Op1IsKill);
118    virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
119                                      const TargetRegisterClass *RC,
120                                      unsigned Op0, bool Op0IsKill,
121                                      unsigned Op1, bool Op1IsKill,
122                                      unsigned Op2, bool Op2IsKill);
123    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
124                                     const TargetRegisterClass *RC,
125                                     unsigned Op0, bool Op0IsKill,
126                                     uint64_t Imm);
127    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
128                                     const TargetRegisterClass *RC,
129                                     unsigned Op0, bool Op0IsKill,
130                                     const ConstantFP *FPImm);
131    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
132                                      const TargetRegisterClass *RC,
133                                      unsigned Op0, bool Op0IsKill,
134                                      unsigned Op1, bool Op1IsKill,
135                                      uint64_t Imm);
136    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
137                                    const TargetRegisterClass *RC,
138                                    uint64_t Imm);
139    virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
140                                     const TargetRegisterClass *RC,
141                                     uint64_t Imm1, uint64_t Imm2);
142
143    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
144                                                unsigned Op0, bool Op0IsKill,
145                                                uint32_t Idx);
146
147    // Backend specific FastISel code.
148    virtual bool TargetSelectInstruction(const Instruction *I);
149    virtual unsigned TargetMaterializeConstant(const Constant *C);
150    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
151
152  #include "ARMGenFastISel.inc"
153
154    // Instruction selection routines.
155  private:
156    bool SelectLoad(const Instruction *I);
157    bool SelectStore(const Instruction *I);
158    bool SelectBranch(const Instruction *I);
159    bool SelectCmp(const Instruction *I);
160    bool SelectFPExt(const Instruction *I);
161    bool SelectFPTrunc(const Instruction *I);
162    bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
163    bool SelectSIToFP(const Instruction *I);
164    bool SelectFPToSI(const Instruction *I);
165    bool SelectSDiv(const Instruction *I);
166    bool SelectSRem(const Instruction *I);
167    bool SelectCall(const Instruction *I);
168    bool SelectSelect(const Instruction *I);
169    bool SelectRet(const Instruction *I);
170    bool SelectIntCast(const Instruction *I);
171
172    // Utility routines.
173  private:
174    bool isTypeLegal(Type *Ty, MVT &VT);
175    bool isLoadTypeLegal(Type *Ty, MVT &VT);
176    bool ARMEmitCmp(Type *Ty, const Value *Src1Value, const Value *Src2Value);
177    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
178    bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
179    bool ARMComputeAddress(const Value *Obj, Address &Addr);
180    void ARMSimplifyAddress(Address &Addr, EVT VT);
181    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
182    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
183    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
184    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
185    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
186    unsigned ARMSelectCallOp(const GlobalValue *GV);
187
188    // Call handling routines.
189  private:
190    bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
191                        unsigned &ResultReg);
192    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
193    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
194                         SmallVectorImpl<unsigned> &ArgRegs,
195                         SmallVectorImpl<MVT> &ArgVTs,
196                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
197                         SmallVectorImpl<unsigned> &RegArgs,
198                         CallingConv::ID CC,
199                         unsigned &NumBytes);
200    bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
201                    const Instruction *I, CallingConv::ID CC,
202                    unsigned &NumBytes);
203    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
204
205    // OptionalDef handling routines.
206  private:
207    bool isARMNEONPred(const MachineInstr *MI);
208    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
209    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
210    void AddLoadStoreOperands(EVT VT, Address &Addr,
211                              const MachineInstrBuilder &MIB,
212                              unsigned Flags);
213};
214
215} // end anonymous namespace
216
217#include "ARMGenCallingConv.inc"
218
219// DefinesOptionalPredicate - This is different from DefinesPredicate in that
220// we don't care about implicit defs here, just places we'll need to add a
221// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
222bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
223  const MCInstrDesc &MCID = MI->getDesc();
224  if (!MCID.hasOptionalDef())
225    return false;
226
227  // Look to see if our OptionalDef is defining CPSR or CCR.
228  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
229    const MachineOperand &MO = MI->getOperand(i);
230    if (!MO.isReg() || !MO.isDef()) continue;
231    if (MO.getReg() == ARM::CPSR)
232      *CPSR = true;
233  }
234  return true;
235}
236
237bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
238  const MCInstrDesc &MCID = MI->getDesc();
239
240  // If we're a thumb2 or not NEON function we were handled via isPredicable.
241  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
242       AFI->isThumb2Function())
243    return false;
244
245  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
246    if (MCID.OpInfo[i].isPredicate())
247      return true;
248
249  return false;
250}
251
252// If the machine is predicable go ahead and add the predicate operands, if
253// it needs default CC operands add those.
254// TODO: If we want to support thumb1 then we'll need to deal with optional
255// CPSR defs that need to be added before the remaining operands. See s_cc_out
256// for descriptions why.
257const MachineInstrBuilder &
258ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
259  MachineInstr *MI = &*MIB;
260
261  // Do we use a predicate? or...
262  // Are we NEON in ARM mode and have a predicate operand? If so, I know
263  // we're not predicable but add it anyways.
264  if (TII.isPredicable(MI) || isARMNEONPred(MI))
265    AddDefaultPred(MIB);
266
267  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
268  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
269  bool CPSR = false;
270  if (DefinesOptionalPredicate(MI, &CPSR)) {
271    if (CPSR)
272      AddDefaultT1CC(MIB);
273    else
274      AddDefaultCC(MIB);
275  }
276  return MIB;
277}
278
279unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
280                                    const TargetRegisterClass* RC) {
281  unsigned ResultReg = createResultReg(RC);
282  const MCInstrDesc &II = TII.get(MachineInstOpcode);
283
284  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
285  return ResultReg;
286}
287
288unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
289                                     const TargetRegisterClass *RC,
290                                     unsigned Op0, bool Op0IsKill) {
291  unsigned ResultReg = createResultReg(RC);
292  const MCInstrDesc &II = TII.get(MachineInstOpcode);
293
294  if (II.getNumDefs() >= 1)
295    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
296                   .addReg(Op0, Op0IsKill * RegState::Kill));
297  else {
298    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
299                   .addReg(Op0, Op0IsKill * RegState::Kill));
300    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
301                   TII.get(TargetOpcode::COPY), ResultReg)
302                   .addReg(II.ImplicitDefs[0]));
303  }
304  return ResultReg;
305}
306
307unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
308                                      const TargetRegisterClass *RC,
309                                      unsigned Op0, bool Op0IsKill,
310                                      unsigned Op1, bool Op1IsKill) {
311  unsigned ResultReg = createResultReg(RC);
312  const MCInstrDesc &II = TII.get(MachineInstOpcode);
313
314  if (II.getNumDefs() >= 1)
315    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
316                   .addReg(Op0, Op0IsKill * RegState::Kill)
317                   .addReg(Op1, Op1IsKill * RegState::Kill));
318  else {
319    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
320                   .addReg(Op0, Op0IsKill * RegState::Kill)
321                   .addReg(Op1, Op1IsKill * RegState::Kill));
322    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
323                           TII.get(TargetOpcode::COPY), ResultReg)
324                   .addReg(II.ImplicitDefs[0]));
325  }
326  return ResultReg;
327}
328
329unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
330                                       const TargetRegisterClass *RC,
331                                       unsigned Op0, bool Op0IsKill,
332                                       unsigned Op1, bool Op1IsKill,
333                                       unsigned Op2, bool Op2IsKill) {
334  unsigned ResultReg = createResultReg(RC);
335  const MCInstrDesc &II = TII.get(MachineInstOpcode);
336
337  if (II.getNumDefs() >= 1)
338    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
339                   .addReg(Op0, Op0IsKill * RegState::Kill)
340                   .addReg(Op1, Op1IsKill * RegState::Kill)
341                   .addReg(Op2, Op2IsKill * RegState::Kill));
342  else {
343    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
344                   .addReg(Op0, Op0IsKill * RegState::Kill)
345                   .addReg(Op1, Op1IsKill * RegState::Kill)
346                   .addReg(Op2, Op2IsKill * RegState::Kill));
347    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
348                           TII.get(TargetOpcode::COPY), ResultReg)
349                   .addReg(II.ImplicitDefs[0]));
350  }
351  return ResultReg;
352}
353
354unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
355                                      const TargetRegisterClass *RC,
356                                      unsigned Op0, bool Op0IsKill,
357                                      uint64_t Imm) {
358  unsigned ResultReg = createResultReg(RC);
359  const MCInstrDesc &II = TII.get(MachineInstOpcode);
360
361  if (II.getNumDefs() >= 1)
362    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
363                   .addReg(Op0, Op0IsKill * RegState::Kill)
364                   .addImm(Imm));
365  else {
366    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
367                   .addReg(Op0, Op0IsKill * RegState::Kill)
368                   .addImm(Imm));
369    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
370                           TII.get(TargetOpcode::COPY), ResultReg)
371                   .addReg(II.ImplicitDefs[0]));
372  }
373  return ResultReg;
374}
375
376unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
377                                      const TargetRegisterClass *RC,
378                                      unsigned Op0, bool Op0IsKill,
379                                      const ConstantFP *FPImm) {
380  unsigned ResultReg = createResultReg(RC);
381  const MCInstrDesc &II = TII.get(MachineInstOpcode);
382
383  if (II.getNumDefs() >= 1)
384    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
385                   .addReg(Op0, Op0IsKill * RegState::Kill)
386                   .addFPImm(FPImm));
387  else {
388    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
389                   .addReg(Op0, Op0IsKill * RegState::Kill)
390                   .addFPImm(FPImm));
391    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
392                           TII.get(TargetOpcode::COPY), ResultReg)
393                   .addReg(II.ImplicitDefs[0]));
394  }
395  return ResultReg;
396}
397
398unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
399                                       const TargetRegisterClass *RC,
400                                       unsigned Op0, bool Op0IsKill,
401                                       unsigned Op1, bool Op1IsKill,
402                                       uint64_t Imm) {
403  unsigned ResultReg = createResultReg(RC);
404  const MCInstrDesc &II = TII.get(MachineInstOpcode);
405
406  if (II.getNumDefs() >= 1)
407    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
408                   .addReg(Op0, Op0IsKill * RegState::Kill)
409                   .addReg(Op1, Op1IsKill * RegState::Kill)
410                   .addImm(Imm));
411  else {
412    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
413                   .addReg(Op0, Op0IsKill * RegState::Kill)
414                   .addReg(Op1, Op1IsKill * RegState::Kill)
415                   .addImm(Imm));
416    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
417                           TII.get(TargetOpcode::COPY), ResultReg)
418                   .addReg(II.ImplicitDefs[0]));
419  }
420  return ResultReg;
421}
422
423unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
424                                     const TargetRegisterClass *RC,
425                                     uint64_t Imm) {
426  unsigned ResultReg = createResultReg(RC);
427  const MCInstrDesc &II = TII.get(MachineInstOpcode);
428
429  if (II.getNumDefs() >= 1)
430    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
431                   .addImm(Imm));
432  else {
433    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
434                   .addImm(Imm));
435    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
436                           TII.get(TargetOpcode::COPY), ResultReg)
437                   .addReg(II.ImplicitDefs[0]));
438  }
439  return ResultReg;
440}
441
442unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
443                                      const TargetRegisterClass *RC,
444                                      uint64_t Imm1, uint64_t Imm2) {
445  unsigned ResultReg = createResultReg(RC);
446  const MCInstrDesc &II = TII.get(MachineInstOpcode);
447
448  if (II.getNumDefs() >= 1)
449    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
450                    .addImm(Imm1).addImm(Imm2));
451  else {
452    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
453                    .addImm(Imm1).addImm(Imm2));
454    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
455                            TII.get(TargetOpcode::COPY),
456                            ResultReg)
457                    .addReg(II.ImplicitDefs[0]));
458  }
459  return ResultReg;
460}
461
462unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
463                                                 unsigned Op0, bool Op0IsKill,
464                                                 uint32_t Idx) {
465  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
466  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
467         "Cannot yet extract from physregs");
468  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
469                         DL, TII.get(TargetOpcode::COPY), ResultReg)
470                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
471  return ResultReg;
472}
473
474// TODO: Don't worry about 64-bit now, but when this is fixed remove the
475// checks from the various callers.
476unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
477  if (VT == MVT::f64) return 0;
478
479  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
480  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
481                          TII.get(ARM::VMOVRS), MoveReg)
482                  .addReg(SrcReg));
483  return MoveReg;
484}
485
486unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
487  if (VT == MVT::i64) return 0;
488
489  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
490  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
491                          TII.get(ARM::VMOVSR), MoveReg)
492                  .addReg(SrcReg));
493  return MoveReg;
494}
495
496// For double width floating point we need to materialize two constants
497// (the high and the low) into integer registers then use a move to get
498// the combined constant into an FP reg.
499unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
500  const APFloat Val = CFP->getValueAPF();
501  bool is64bit = VT == MVT::f64;
502
503  // This checks to see if we can use VFP3 instructions to materialize
504  // a constant, otherwise we have to go through the constant pool.
505  if (TLI.isFPImmLegal(Val, VT)) {
506    int Imm;
507    unsigned Opc;
508    if (is64bit) {
509      Imm = ARM_AM::getFP64Imm(Val);
510      Opc = ARM::FCONSTD;
511    } else {
512      Imm = ARM_AM::getFP32Imm(Val);
513      Opc = ARM::FCONSTS;
514    }
515    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
516    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
517                            DestReg)
518                    .addImm(Imm));
519    return DestReg;
520  }
521
522  // Require VFP2 for loading fp constants.
523  if (!Subtarget->hasVFP2()) return false;
524
525  // MachineConstantPool wants an explicit alignment.
526  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
527  if (Align == 0) {
528    // TODO: Figure out if this is correct.
529    Align = TD.getTypeAllocSize(CFP->getType());
530  }
531  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
532  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
533  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
534
535  // The extra reg is for addrmode5.
536  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
537                          DestReg)
538                  .addConstantPoolIndex(Idx)
539                  .addReg(0));
540  return DestReg;
541}
542
543unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
544
545  // For now 32-bit only.
546  if (VT != MVT::i32) return false;
547
548  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
549
550  // If we can do this in a single instruction without a constant pool entry
551  // do so now.
552  const ConstantInt *CI = cast<ConstantInt>(C);
553  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
554    unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
555    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
556                            TII.get(Opc), DestReg)
557                    .addImm(CI->getSExtValue()));
558    return DestReg;
559  }
560
561  // MachineConstantPool wants an explicit alignment.
562  unsigned Align = TD.getPrefTypeAlignment(C->getType());
563  if (Align == 0) {
564    // TODO: Figure out if this is correct.
565    Align = TD.getTypeAllocSize(C->getType());
566  }
567  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
568
569  if (isThumb)
570    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
571                            TII.get(ARM::t2LDRpci), DestReg)
572                    .addConstantPoolIndex(Idx));
573  else
574    // The extra immediate is for addrmode2.
575    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
576                            TII.get(ARM::LDRcp), DestReg)
577                    .addConstantPoolIndex(Idx)
578                    .addImm(0));
579
580  return DestReg;
581}
582
583unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
584  // For now 32-bit only.
585  if (VT != MVT::i32) return 0;
586
587  Reloc::Model RelocM = TM.getRelocationModel();
588
589  // TODO: Need more magic for ARM PIC.
590  if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
591
592  // MachineConstantPool wants an explicit alignment.
593  unsigned Align = TD.getPrefTypeAlignment(GV->getType());
594  if (Align == 0) {
595    // TODO: Figure out if this is correct.
596    Align = TD.getTypeAllocSize(GV->getType());
597  }
598
599  // Grab index.
600  unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
601  unsigned Id = AFI->createPICLabelUId();
602  ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
603                                                              ARMCP::CPValue,
604                                                              PCAdj);
605  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
606
607  // Load value.
608  MachineInstrBuilder MIB;
609  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
610  if (isThumb) {
611    unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
612    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
613          .addConstantPoolIndex(Idx);
614    if (RelocM == Reloc::PIC_)
615      MIB.addImm(Id);
616  } else {
617    // The extra immediate is for addrmode2.
618    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
619                  DestReg)
620          .addConstantPoolIndex(Idx)
621          .addImm(0);
622  }
623  AddOptionalDefs(MIB);
624
625  if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
626    unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
627    if (isThumb)
628      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
629                    TII.get(ARM::t2LDRi12), NewDestReg)
630            .addReg(DestReg)
631            .addImm(0);
632    else
633      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
634                    NewDestReg)
635            .addReg(DestReg)
636            .addImm(0);
637    DestReg = NewDestReg;
638    AddOptionalDefs(MIB);
639  }
640
641  return DestReg;
642}
643
644unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
645  EVT VT = TLI.getValueType(C->getType(), true);
646
647  // Only handle simple types.
648  if (!VT.isSimple()) return 0;
649
650  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
651    return ARMMaterializeFP(CFP, VT);
652  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
653    return ARMMaterializeGV(GV, VT);
654  else if (isa<ConstantInt>(C))
655    return ARMMaterializeInt(C, VT);
656
657  return 0;
658}
659
660unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
661  // Don't handle dynamic allocas.
662  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
663
664  MVT VT;
665  if (!isLoadTypeLegal(AI->getType(), VT)) return false;
666
667  DenseMap<const AllocaInst*, int>::iterator SI =
668    FuncInfo.StaticAllocaMap.find(AI);
669
670  // This will get lowered later into the correct offsets and registers
671  // via rewriteXFrameIndex.
672  if (SI != FuncInfo.StaticAllocaMap.end()) {
673    TargetRegisterClass* RC = TLI.getRegClassFor(VT);
674    unsigned ResultReg = createResultReg(RC);
675    unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
676    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
677                            TII.get(Opc), ResultReg)
678                            .addFrameIndex(SI->second)
679                            .addImm(0));
680    return ResultReg;
681  }
682
683  return 0;
684}
685
686bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
687  EVT evt = TLI.getValueType(Ty, true);
688
689  // Only handle simple types.
690  if (evt == MVT::Other || !evt.isSimple()) return false;
691  VT = evt.getSimpleVT();
692
693  // Handle all legal types, i.e. a register that will directly hold this
694  // value.
695  return TLI.isTypeLegal(VT);
696}
697
698bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
699  if (isTypeLegal(Ty, VT)) return true;
700
701  // If this is a type than can be sign or zero-extended to a basic operation
702  // go ahead and accept it now.
703  if (VT == MVT::i8 || VT == MVT::i16)
704    return true;
705
706  return false;
707}
708
709// Computes the address to get to an object.
710bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
711  // Some boilerplate from the X86 FastISel.
712  const User *U = NULL;
713  unsigned Opcode = Instruction::UserOp1;
714  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
715    // Don't walk into other basic blocks unless the object is an alloca from
716    // another block, otherwise it may not have a virtual register assigned.
717    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
718        FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
719      Opcode = I->getOpcode();
720      U = I;
721    }
722  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
723    Opcode = C->getOpcode();
724    U = C;
725  }
726
727  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
728    if (Ty->getAddressSpace() > 255)
729      // Fast instruction selection doesn't support the special
730      // address spaces.
731      return false;
732
733  switch (Opcode) {
734    default:
735    break;
736    case Instruction::BitCast: {
737      // Look through bitcasts.
738      return ARMComputeAddress(U->getOperand(0), Addr);
739    }
740    case Instruction::IntToPtr: {
741      // Look past no-op inttoptrs.
742      if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
743        return ARMComputeAddress(U->getOperand(0), Addr);
744      break;
745    }
746    case Instruction::PtrToInt: {
747      // Look past no-op ptrtoints.
748      if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
749        return ARMComputeAddress(U->getOperand(0), Addr);
750      break;
751    }
752    case Instruction::GetElementPtr: {
753      Address SavedAddr = Addr;
754      int TmpOffset = Addr.Offset;
755
756      // Iterate through the GEP folding the constants into offsets where
757      // we can.
758      gep_type_iterator GTI = gep_type_begin(U);
759      for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
760           i != e; ++i, ++GTI) {
761        const Value *Op = *i;
762        if (StructType *STy = dyn_cast<StructType>(*GTI)) {
763          const StructLayout *SL = TD.getStructLayout(STy);
764          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
765          TmpOffset += SL->getElementOffset(Idx);
766        } else {
767          uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
768          for (;;) {
769            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
770              // Constant-offset addressing.
771              TmpOffset += CI->getSExtValue() * S;
772              break;
773            }
774            if (isa<AddOperator>(Op) &&
775                (!isa<Instruction>(Op) ||
776                 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
777                 == FuncInfo.MBB) &&
778                isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
779              // An add (in the same block) with a constant operand. Fold the
780              // constant.
781              ConstantInt *CI =
782              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
783              TmpOffset += CI->getSExtValue() * S;
784              // Iterate on the other operand.
785              Op = cast<AddOperator>(Op)->getOperand(0);
786              continue;
787            }
788            // Unsupported
789            goto unsupported_gep;
790          }
791        }
792      }
793
794      // Try to grab the base operand now.
795      Addr.Offset = TmpOffset;
796      if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
797
798      // We failed, restore everything and try the other options.
799      Addr = SavedAddr;
800
801      unsupported_gep:
802      break;
803    }
804    case Instruction::Alloca: {
805      const AllocaInst *AI = cast<AllocaInst>(Obj);
806      DenseMap<const AllocaInst*, int>::iterator SI =
807        FuncInfo.StaticAllocaMap.find(AI);
808      if (SI != FuncInfo.StaticAllocaMap.end()) {
809        Addr.BaseType = Address::FrameIndexBase;
810        Addr.Base.FI = SI->second;
811        return true;
812      }
813      break;
814    }
815  }
816
817  // Materialize the global variable's address into a reg which can
818  // then be used later to load the variable.
819  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
820    unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
821    if (Tmp == 0) return false;
822
823    Addr.Base.Reg = Tmp;
824    return true;
825  }
826
827  // Try to get this in a register if nothing else has worked.
828  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
829  return Addr.Base.Reg != 0;
830}
831
832void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
833
834  assert(VT.isSimple() && "Non-simple types are invalid here!");
835
836  bool needsLowering = false;
837  switch (VT.getSimpleVT().SimpleTy) {
838    default:
839      assert(false && "Unhandled load/store type!");
840    case MVT::i1:
841    case MVT::i8:
842    case MVT::i16:
843    case MVT::i32:
844      // Integer loads/stores handle 12-bit offsets.
845      needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
846      break;
847    case MVT::f32:
848    case MVT::f64:
849      // Floating point operands handle 8-bit offsets.
850      needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
851      break;
852  }
853
854  // If this is a stack pointer and the offset needs to be simplified then
855  // put the alloca address into a register, set the base type back to
856  // register and continue. This should almost never happen.
857  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
858    TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
859                              ARM::GPRRegisterClass;
860    unsigned ResultReg = createResultReg(RC);
861    unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
862    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
863                            TII.get(Opc), ResultReg)
864                            .addFrameIndex(Addr.Base.FI)
865                            .addImm(0));
866    Addr.Base.Reg = ResultReg;
867    Addr.BaseType = Address::RegBase;
868  }
869
870  // Since the offset is too large for the load/store instruction
871  // get the reg+offset into a register.
872  if (needsLowering) {
873    Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
874                                 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
875    Addr.Offset = 0;
876  }
877}
878
879void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
880                                       const MachineInstrBuilder &MIB,
881                                       unsigned Flags) {
882  // addrmode5 output depends on the selection dag addressing dividing the
883  // offset by 4 that it then later multiplies. Do this here as well.
884  if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
885      VT.getSimpleVT().SimpleTy == MVT::f64)
886    Addr.Offset /= 4;
887
888  // Frame base works a bit differently. Handle it separately.
889  if (Addr.BaseType == Address::FrameIndexBase) {
890    int FI = Addr.Base.FI;
891    int Offset = Addr.Offset;
892    MachineMemOperand *MMO =
893          FuncInfo.MF->getMachineMemOperand(
894                                  MachinePointerInfo::getFixedStack(FI, Offset),
895                                  Flags,
896                                  MFI.getObjectSize(FI),
897                                  MFI.getObjectAlignment(FI));
898    // Now add the rest of the operands.
899    MIB.addFrameIndex(FI);
900
901    // ARM halfword load/stores need an additional operand.
902    if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
903
904    MIB.addImm(Addr.Offset);
905    MIB.addMemOperand(MMO);
906  } else {
907    // Now add the rest of the operands.
908    MIB.addReg(Addr.Base.Reg);
909
910    // ARM halfword load/stores need an additional operand.
911    if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
912
913    MIB.addImm(Addr.Offset);
914  }
915  AddOptionalDefs(MIB);
916}
917
918bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
919
920  assert(VT.isSimple() && "Non-simple types are invalid here!");
921  unsigned Opc;
922  TargetRegisterClass *RC;
923  switch (VT.getSimpleVT().SimpleTy) {
924    // This is mostly going to be Neon/vector support.
925    default: return false;
926    case MVT::i16:
927      Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
928      RC = ARM::GPRRegisterClass;
929      break;
930    case MVT::i8:
931      Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
932      RC = ARM::GPRRegisterClass;
933      break;
934    case MVT::i32:
935      Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
936      RC = ARM::GPRRegisterClass;
937      break;
938    case MVT::f32:
939      Opc = ARM::VLDRS;
940      RC = TLI.getRegClassFor(VT);
941      break;
942    case MVT::f64:
943      Opc = ARM::VLDRD;
944      RC = TLI.getRegClassFor(VT);
945      break;
946  }
947  // Simplify this down to something we can handle.
948  ARMSimplifyAddress(Addr, VT);
949
950  // Create the base instruction, then add the operands.
951  ResultReg = createResultReg(RC);
952  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
953                                    TII.get(Opc), ResultReg);
954  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad);
955  return true;
956}
957
958bool ARMFastISel::SelectLoad(const Instruction *I) {
959  // Atomic loads need special handling.
960  if (cast<LoadInst>(I)->isAtomic())
961    return false;
962
963  // Verify we have a legal type before going any further.
964  MVT VT;
965  if (!isLoadTypeLegal(I->getType(), VT))
966    return false;
967
968  // See if we can handle this address.
969  Address Addr;
970  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
971
972  unsigned ResultReg;
973  if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
974  UpdateValueMap(I, ResultReg);
975  return true;
976}
977
978bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
979  unsigned StrOpc;
980  switch (VT.getSimpleVT().SimpleTy) {
981    // This is mostly going to be Neon/vector support.
982    default: return false;
983    case MVT::i1: {
984      unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
985                                               ARM::GPRRegisterClass);
986      unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
987      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
988                              TII.get(Opc), Res)
989                      .addReg(SrcReg).addImm(1));
990      SrcReg = Res;
991    } // Fallthrough here.
992    case MVT::i8:
993      StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
994      break;
995    case MVT::i16:
996      StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
997      break;
998    case MVT::i32:
999      StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
1000      break;
1001    case MVT::f32:
1002      if (!Subtarget->hasVFP2()) return false;
1003      StrOpc = ARM::VSTRS;
1004      break;
1005    case MVT::f64:
1006      if (!Subtarget->hasVFP2()) return false;
1007      StrOpc = ARM::VSTRD;
1008      break;
1009  }
1010  // Simplify this down to something we can handle.
1011  ARMSimplifyAddress(Addr, VT);
1012
1013  // Create the base instruction, then add the operands.
1014  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1015                                    TII.get(StrOpc))
1016                            .addReg(SrcReg, getKillRegState(true));
1017  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore);
1018  return true;
1019}
1020
1021bool ARMFastISel::SelectStore(const Instruction *I) {
1022  Value *Op0 = I->getOperand(0);
1023  unsigned SrcReg = 0;
1024
1025  // Atomic stores need special handling.
1026  if (cast<StoreInst>(I)->isAtomic())
1027    return false;
1028
1029  // Verify we have a legal type before going any further.
1030  MVT VT;
1031  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1032    return false;
1033
1034  // Get the value to be stored into a register.
1035  SrcReg = getRegForValue(Op0);
1036  if (SrcReg == 0) return false;
1037
1038  // See if we can handle this address.
1039  Address Addr;
1040  if (!ARMComputeAddress(I->getOperand(1), Addr))
1041    return false;
1042
1043  if (!ARMEmitStore(VT, SrcReg, Addr)) return false;
1044  return true;
1045}
1046
1047static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1048  switch (Pred) {
1049    // Needs two compares...
1050    case CmpInst::FCMP_ONE:
1051    case CmpInst::FCMP_UEQ:
1052    default:
1053      // AL is our "false" for now. The other two need more compares.
1054      return ARMCC::AL;
1055    case CmpInst::ICMP_EQ:
1056    case CmpInst::FCMP_OEQ:
1057      return ARMCC::EQ;
1058    case CmpInst::ICMP_SGT:
1059    case CmpInst::FCMP_OGT:
1060      return ARMCC::GT;
1061    case CmpInst::ICMP_SGE:
1062    case CmpInst::FCMP_OGE:
1063      return ARMCC::GE;
1064    case CmpInst::ICMP_UGT:
1065    case CmpInst::FCMP_UGT:
1066      return ARMCC::HI;
1067    case CmpInst::FCMP_OLT:
1068      return ARMCC::MI;
1069    case CmpInst::ICMP_ULE:
1070    case CmpInst::FCMP_OLE:
1071      return ARMCC::LS;
1072    case CmpInst::FCMP_ORD:
1073      return ARMCC::VC;
1074    case CmpInst::FCMP_UNO:
1075      return ARMCC::VS;
1076    case CmpInst::FCMP_UGE:
1077      return ARMCC::PL;
1078    case CmpInst::ICMP_SLT:
1079    case CmpInst::FCMP_ULT:
1080      return ARMCC::LT;
1081    case CmpInst::ICMP_SLE:
1082    case CmpInst::FCMP_ULE:
1083      return ARMCC::LE;
1084    case CmpInst::FCMP_UNE:
1085    case CmpInst::ICMP_NE:
1086      return ARMCC::NE;
1087    case CmpInst::ICMP_UGE:
1088      return ARMCC::HS;
1089    case CmpInst::ICMP_ULT:
1090      return ARMCC::LO;
1091  }
1092}
1093
1094bool ARMFastISel::SelectBranch(const Instruction *I) {
1095  const BranchInst *BI = cast<BranchInst>(I);
1096  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1097  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1098
1099  // Simple branch support.
1100
1101  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1102  // behavior.
1103  // TODO: Factor this out.
1104  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1105    MVT SourceVT;
1106    Type *Ty = CI->getOperand(0)->getType();
1107    if (CI->hasOneUse() && (CI->getParent() == I->getParent())
1108        && isTypeLegal(Ty, SourceVT)) {
1109      bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1110      if (isFloat && !Subtarget->hasVFP2())
1111        return false;
1112
1113      unsigned CmpOpc;
1114      switch (SourceVT.SimpleTy) {
1115        default: return false;
1116        // TODO: Verify compares.
1117        case MVT::f32:
1118          CmpOpc = ARM::VCMPES;
1119          break;
1120        case MVT::f64:
1121          CmpOpc = ARM::VCMPED;
1122          break;
1123        case MVT::i32:
1124          CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1125          break;
1126      }
1127
1128      // Get the compare predicate.
1129      // Try to take advantage of fallthrough opportunities.
1130      CmpInst::Predicate Predicate = CI->getPredicate();
1131      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1132        std::swap(TBB, FBB);
1133        Predicate = CmpInst::getInversePredicate(Predicate);
1134      }
1135
1136      ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1137
1138      // We may not handle every CC for now.
1139      if (ARMPred == ARMCC::AL) return false;
1140
1141      unsigned Arg1 = getRegForValue(CI->getOperand(0));
1142      if (Arg1 == 0) return false;
1143
1144      unsigned Arg2 = getRegForValue(CI->getOperand(1));
1145      if (Arg2 == 0) return false;
1146
1147      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1148                              TII.get(CmpOpc))
1149                      .addReg(Arg1).addReg(Arg2));
1150
1151      // For floating point we need to move the result to a comparison register
1152      // that we can then use for branches.
1153      if (isFloat)
1154        AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1155                                TII.get(ARM::FMSTAT)));
1156
1157      unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1158      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1159      .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1160      FastEmitBranch(FBB, DL);
1161      FuncInfo.MBB->addSuccessor(TBB);
1162      return true;
1163    }
1164  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1165    MVT SourceVT;
1166    if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1167        (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1168      unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1169      unsigned OpReg = getRegForValue(TI->getOperand(0));
1170      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1171                              TII.get(TstOpc))
1172                      .addReg(OpReg).addImm(1));
1173
1174      unsigned CCMode = ARMCC::NE;
1175      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1176        std::swap(TBB, FBB);
1177        CCMode = ARMCC::EQ;
1178      }
1179
1180      unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1181      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1182      .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1183
1184      FastEmitBranch(FBB, DL);
1185      FuncInfo.MBB->addSuccessor(TBB);
1186      return true;
1187    }
1188  }
1189
1190  unsigned CmpReg = getRegForValue(BI->getCondition());
1191  if (CmpReg == 0) return false;
1192
1193  // We've been divorced from our compare!  Our block was split, and
1194  // now our compare lives in a predecessor block.  We musn't
1195  // re-compare here, as the children of the compare aren't guaranteed
1196  // live across the block boundary (we *could* check for this).
1197  // Regardless, the compare has been done in the predecessor block,
1198  // and it left a value for us in a virtual register.  Ergo, we test
1199  // the one-bit value left in the virtual register.
1200  unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1201  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1202                  .addReg(CmpReg).addImm(1));
1203
1204  unsigned CCMode = ARMCC::NE;
1205  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1206    std::swap(TBB, FBB);
1207    CCMode = ARMCC::EQ;
1208  }
1209
1210  unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1211  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1212                  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1213  FastEmitBranch(FBB, DL);
1214  FuncInfo.MBB->addSuccessor(TBB);
1215  return true;
1216}
1217
1218bool ARMFastISel::ARMEmitCmp(Type *Ty, const Value *Src1Value,
1219                             const Value *Src2Value) {
1220  MVT VT;
1221  if (!isTypeLegal(Ty, VT))
1222    return false;
1223
1224  if ((Ty->isFloatTy() || Ty->isDoubleTy()) && !Subtarget->hasVFP2())
1225    return false;
1226
1227  unsigned CmpOpc;
1228  switch (VT.SimpleTy) {
1229    default: return false;
1230    // TODO: Verify compares.
1231    case MVT::f32:
1232      CmpOpc = ARM::VCMPES;
1233      break;
1234    case MVT::f64:
1235      CmpOpc = ARM::VCMPED;
1236      break;
1237    case MVT::i32:
1238      CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1239      break;
1240  }
1241
1242  unsigned Src1 = getRegForValue(Src1Value);
1243  if (Src1 == 0) return false;
1244
1245  unsigned Src2 = getRegForValue(Src2Value);
1246  if (Src2 == 0) return false;
1247
1248  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1249                  .addReg(Src1).addReg(Src2));
1250  return true;
1251}
1252
1253bool ARMFastISel::SelectCmp(const Instruction *I) {
1254  const CmpInst *CI = cast<CmpInst>(I);
1255
1256  // Get the compare predicate.
1257  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1258
1259  // We may not handle every CC for now.
1260  if (ARMPred == ARMCC::AL) return false;
1261
1262  // Emit the compare.
1263  Type *Ty = CI->getOperand(0)->getType();
1264  if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
1265    return false;
1266
1267  // For floating point we need to move the result to a comparison register
1268  // that we can then use for branches.
1269  bool isFloat = Ty->isFloatTy() || Ty->isDoubleTy();
1270  if (isFloat)
1271    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1272                            TII.get(ARM::FMSTAT)));
1273
1274  // Now set a register based on the comparison. Explicitly set the predicates
1275  // here.
1276  unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1277  TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1278                                    : ARM::GPRRegisterClass;
1279  unsigned DestReg = createResultReg(RC);
1280  Constant *Zero
1281    = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1282  unsigned ZeroReg = TargetMaterializeConstant(Zero);
1283  unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
1284  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1285          .addReg(ZeroReg).addImm(1)
1286          .addImm(ARMPred).addReg(CondReg);
1287
1288  UpdateValueMap(I, DestReg);
1289  return true;
1290}
1291
1292bool ARMFastISel::SelectFPExt(const Instruction *I) {
1293  // Make sure we have VFP and that we're extending float to double.
1294  if (!Subtarget->hasVFP2()) return false;
1295
1296  Value *V = I->getOperand(0);
1297  if (!I->getType()->isDoubleTy() ||
1298      !V->getType()->isFloatTy()) return false;
1299
1300  unsigned Op = getRegForValue(V);
1301  if (Op == 0) return false;
1302
1303  unsigned Result = createResultReg(ARM::DPRRegisterClass);
1304  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1305                          TII.get(ARM::VCVTDS), Result)
1306                  .addReg(Op));
1307  UpdateValueMap(I, Result);
1308  return true;
1309}
1310
1311bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1312  // Make sure we have VFP and that we're truncating double to float.
1313  if (!Subtarget->hasVFP2()) return false;
1314
1315  Value *V = I->getOperand(0);
1316  if (!(I->getType()->isFloatTy() &&
1317        V->getType()->isDoubleTy())) return false;
1318
1319  unsigned Op = getRegForValue(V);
1320  if (Op == 0) return false;
1321
1322  unsigned Result = createResultReg(ARM::SPRRegisterClass);
1323  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1324                          TII.get(ARM::VCVTSD), Result)
1325                  .addReg(Op));
1326  UpdateValueMap(I, Result);
1327  return true;
1328}
1329
1330bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1331  // Make sure we have VFP.
1332  if (!Subtarget->hasVFP2()) return false;
1333
1334  MVT DstVT;
1335  Type *Ty = I->getType();
1336  if (!isTypeLegal(Ty, DstVT))
1337    return false;
1338
1339  // FIXME: Handle sign-extension where necessary.
1340  if (!I->getOperand(0)->getType()->isIntegerTy(32))
1341    return false;
1342
1343  unsigned Op = getRegForValue(I->getOperand(0));
1344  if (Op == 0) return false;
1345
1346  // The conversion routine works on fp-reg to fp-reg and the operand above
1347  // was an integer, move it to the fp registers if possible.
1348  unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1349  if (FP == 0) return false;
1350
1351  unsigned Opc;
1352  if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1353  else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1354  else return false;
1355
1356  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1357  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1358                          ResultReg)
1359                  .addReg(FP));
1360  UpdateValueMap(I, ResultReg);
1361  return true;
1362}
1363
1364bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1365  // Make sure we have VFP.
1366  if (!Subtarget->hasVFP2()) return false;
1367
1368  MVT DstVT;
1369  Type *RetTy = I->getType();
1370  if (!isTypeLegal(RetTy, DstVT))
1371    return false;
1372
1373  unsigned Op = getRegForValue(I->getOperand(0));
1374  if (Op == 0) return false;
1375
1376  unsigned Opc;
1377  Type *OpTy = I->getOperand(0)->getType();
1378  if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1379  else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1380  else return false;
1381
1382  // f64->s32 or f32->s32 both need an intermediate f32 reg.
1383  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1384  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1385                          ResultReg)
1386                  .addReg(Op));
1387
1388  // This result needs to be in an integer register, but the conversion only
1389  // takes place in fp-regs.
1390  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1391  if (IntReg == 0) return false;
1392
1393  UpdateValueMap(I, IntReg);
1394  return true;
1395}
1396
1397bool ARMFastISel::SelectSelect(const Instruction *I) {
1398  MVT VT;
1399  if (!isTypeLegal(I->getType(), VT))
1400    return false;
1401
1402  // Things need to be register sized for register moves.
1403  if (VT != MVT::i32) return false;
1404  const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1405
1406  unsigned CondReg = getRegForValue(I->getOperand(0));
1407  if (CondReg == 0) return false;
1408  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1409  if (Op1Reg == 0) return false;
1410  unsigned Op2Reg = getRegForValue(I->getOperand(2));
1411  if (Op2Reg == 0) return false;
1412
1413  unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1414  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1415                  .addReg(CondReg).addImm(1));
1416  unsigned ResultReg = createResultReg(RC);
1417  unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1418  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1419    .addReg(Op1Reg).addReg(Op2Reg)
1420    .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1421  UpdateValueMap(I, ResultReg);
1422  return true;
1423}
1424
1425bool ARMFastISel::SelectSDiv(const Instruction *I) {
1426  MVT VT;
1427  Type *Ty = I->getType();
1428  if (!isTypeLegal(Ty, VT))
1429    return false;
1430
1431  // If we have integer div support we should have selected this automagically.
1432  // In case we have a real miss go ahead and return false and we'll pick
1433  // it up later.
1434  if (Subtarget->hasDivide()) return false;
1435
1436  // Otherwise emit a libcall.
1437  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1438  if (VT == MVT::i8)
1439    LC = RTLIB::SDIV_I8;
1440  else if (VT == MVT::i16)
1441    LC = RTLIB::SDIV_I16;
1442  else if (VT == MVT::i32)
1443    LC = RTLIB::SDIV_I32;
1444  else if (VT == MVT::i64)
1445    LC = RTLIB::SDIV_I64;
1446  else if (VT == MVT::i128)
1447    LC = RTLIB::SDIV_I128;
1448  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1449
1450  return ARMEmitLibcall(I, LC);
1451}
1452
1453bool ARMFastISel::SelectSRem(const Instruction *I) {
1454  MVT VT;
1455  Type *Ty = I->getType();
1456  if (!isTypeLegal(Ty, VT))
1457    return false;
1458
1459  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1460  if (VT == MVT::i8)
1461    LC = RTLIB::SREM_I8;
1462  else if (VT == MVT::i16)
1463    LC = RTLIB::SREM_I16;
1464  else if (VT == MVT::i32)
1465    LC = RTLIB::SREM_I32;
1466  else if (VT == MVT::i64)
1467    LC = RTLIB::SREM_I64;
1468  else if (VT == MVT::i128)
1469    LC = RTLIB::SREM_I128;
1470  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1471
1472  return ARMEmitLibcall(I, LC);
1473}
1474
1475bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1476  EVT VT  = TLI.getValueType(I->getType(), true);
1477
1478  // We can get here in the case when we want to use NEON for our fp
1479  // operations, but can't figure out how to. Just use the vfp instructions
1480  // if we have them.
1481  // FIXME: It'd be nice to use NEON instructions.
1482  Type *Ty = I->getType();
1483  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1484  if (isFloat && !Subtarget->hasVFP2())
1485    return false;
1486
1487  unsigned Op1 = getRegForValue(I->getOperand(0));
1488  if (Op1 == 0) return false;
1489
1490  unsigned Op2 = getRegForValue(I->getOperand(1));
1491  if (Op2 == 0) return false;
1492
1493  unsigned Opc;
1494  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1495  switch (ISDOpcode) {
1496    default: return false;
1497    case ISD::FADD:
1498      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1499      break;
1500    case ISD::FSUB:
1501      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1502      break;
1503    case ISD::FMUL:
1504      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1505      break;
1506  }
1507  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1508  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1509                          TII.get(Opc), ResultReg)
1510                  .addReg(Op1).addReg(Op2));
1511  UpdateValueMap(I, ResultReg);
1512  return true;
1513}
1514
1515// Call Handling Code
1516
1517bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1518                                 EVT SrcVT, unsigned &ResultReg) {
1519  unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1520                           Src, /*TODO: Kill=*/false);
1521
1522  if (RR != 0) {
1523    ResultReg = RR;
1524    return true;
1525  } else
1526    return false;
1527}
1528
1529// This is largely taken directly from CCAssignFnForNode - we don't support
1530// varargs in FastISel so that part has been removed.
1531// TODO: We may not support all of this.
1532CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1533  switch (CC) {
1534  default:
1535    llvm_unreachable("Unsupported calling convention");
1536  case CallingConv::Fast:
1537    // Ignore fastcc. Silence compiler warnings.
1538    (void)RetFastCC_ARM_APCS;
1539    (void)FastCC_ARM_APCS;
1540    // Fallthrough
1541  case CallingConv::C:
1542    // Use target triple & subtarget features to do actual dispatch.
1543    if (Subtarget->isAAPCS_ABI()) {
1544      if (Subtarget->hasVFP2() &&
1545          FloatABIType == FloatABI::Hard)
1546        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1547      else
1548        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1549    } else
1550        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1551  case CallingConv::ARM_AAPCS_VFP:
1552    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1553  case CallingConv::ARM_AAPCS:
1554    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1555  case CallingConv::ARM_APCS:
1556    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1557  }
1558}
1559
1560bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1561                                  SmallVectorImpl<unsigned> &ArgRegs,
1562                                  SmallVectorImpl<MVT> &ArgVTs,
1563                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1564                                  SmallVectorImpl<unsigned> &RegArgs,
1565                                  CallingConv::ID CC,
1566                                  unsigned &NumBytes) {
1567  SmallVector<CCValAssign, 16> ArgLocs;
1568  CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1569  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1570
1571  // Get a count of how many bytes are to be pushed on the stack.
1572  NumBytes = CCInfo.getNextStackOffset();
1573
1574  // Issue CALLSEQ_START
1575  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1576  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1577                          TII.get(AdjStackDown))
1578                  .addImm(NumBytes));
1579
1580  // Process the args.
1581  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1582    CCValAssign &VA = ArgLocs[i];
1583    unsigned Arg = ArgRegs[VA.getValNo()];
1584    MVT ArgVT = ArgVTs[VA.getValNo()];
1585
1586    // We don't handle NEON/vector parameters yet.
1587    if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1588      return false;
1589
1590    // Handle arg promotion, etc.
1591    switch (VA.getLocInfo()) {
1592      case CCValAssign::Full: break;
1593      case CCValAssign::SExt: {
1594        bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1595                                         Arg, ArgVT, Arg);
1596        assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
1597        Emitted = true;
1598        ArgVT = VA.getLocVT();
1599        break;
1600      }
1601      case CCValAssign::ZExt: {
1602        bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1603                                         Arg, ArgVT, Arg);
1604        assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
1605        Emitted = true;
1606        ArgVT = VA.getLocVT();
1607        break;
1608      }
1609      case CCValAssign::AExt: {
1610        bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1611                                         Arg, ArgVT, Arg);
1612        if (!Emitted)
1613          Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1614                                      Arg, ArgVT, Arg);
1615        if (!Emitted)
1616          Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1617                                      Arg, ArgVT, Arg);
1618
1619        assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
1620        ArgVT = VA.getLocVT();
1621        break;
1622      }
1623      case CCValAssign::BCvt: {
1624        unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1625                                 /*TODO: Kill=*/false);
1626        assert(BC != 0 && "Failed to emit a bitcast!");
1627        Arg = BC;
1628        ArgVT = VA.getLocVT();
1629        break;
1630      }
1631      default: llvm_unreachable("Unknown arg promotion!");
1632    }
1633
1634    // Now copy/store arg to correct locations.
1635    if (VA.isRegLoc() && !VA.needsCustom()) {
1636      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1637              VA.getLocReg())
1638      .addReg(Arg);
1639      RegArgs.push_back(VA.getLocReg());
1640    } else if (VA.needsCustom()) {
1641      // TODO: We need custom lowering for vector (v2f64) args.
1642      if (VA.getLocVT() != MVT::f64) return false;
1643
1644      CCValAssign &NextVA = ArgLocs[++i];
1645
1646      // TODO: Only handle register args for now.
1647      if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1648
1649      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1650                              TII.get(ARM::VMOVRRD), VA.getLocReg())
1651                      .addReg(NextVA.getLocReg(), RegState::Define)
1652                      .addReg(Arg));
1653      RegArgs.push_back(VA.getLocReg());
1654      RegArgs.push_back(NextVA.getLocReg());
1655    } else {
1656      assert(VA.isMemLoc());
1657      // Need to store on the stack.
1658      Address Addr;
1659      Addr.BaseType = Address::RegBase;
1660      Addr.Base.Reg = ARM::SP;
1661      Addr.Offset = VA.getLocMemOffset();
1662
1663      if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1664    }
1665  }
1666  return true;
1667}
1668
1669bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1670                             const Instruction *I, CallingConv::ID CC,
1671                             unsigned &NumBytes) {
1672  // Issue CALLSEQ_END
1673  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1674  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1675                          TII.get(AdjStackUp))
1676                  .addImm(NumBytes).addImm(0));
1677
1678  // Now the return value.
1679  if (RetVT != MVT::isVoid) {
1680    SmallVector<CCValAssign, 16> RVLocs;
1681    CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1682    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1683
1684    // Copy all of the result registers out of their specified physreg.
1685    if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1686      // For this move we copy into two registers and then move into the
1687      // double fp reg we want.
1688      EVT DestVT = RVLocs[0].getValVT();
1689      TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1690      unsigned ResultReg = createResultReg(DstRC);
1691      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1692                              TII.get(ARM::VMOVDRR), ResultReg)
1693                      .addReg(RVLocs[0].getLocReg())
1694                      .addReg(RVLocs[1].getLocReg()));
1695
1696      UsedRegs.push_back(RVLocs[0].getLocReg());
1697      UsedRegs.push_back(RVLocs[1].getLocReg());
1698
1699      // Finally update the result.
1700      UpdateValueMap(I, ResultReg);
1701    } else {
1702      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1703      EVT CopyVT = RVLocs[0].getValVT();
1704      TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1705
1706      unsigned ResultReg = createResultReg(DstRC);
1707      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1708              ResultReg).addReg(RVLocs[0].getLocReg());
1709      UsedRegs.push_back(RVLocs[0].getLocReg());
1710
1711      // Finally update the result.
1712      UpdateValueMap(I, ResultReg);
1713    }
1714  }
1715
1716  return true;
1717}
1718
1719bool ARMFastISel::SelectRet(const Instruction *I) {
1720  const ReturnInst *Ret = cast<ReturnInst>(I);
1721  const Function &F = *I->getParent()->getParent();
1722
1723  if (!FuncInfo.CanLowerReturn)
1724    return false;
1725
1726  if (F.isVarArg())
1727    return false;
1728
1729  CallingConv::ID CC = F.getCallingConv();
1730  if (Ret->getNumOperands() > 0) {
1731    SmallVector<ISD::OutputArg, 4> Outs;
1732    GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1733                  Outs, TLI);
1734
1735    // Analyze operands of the call, assigning locations to each operand.
1736    SmallVector<CCValAssign, 16> ValLocs;
1737    CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
1738    CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1739
1740    const Value *RV = Ret->getOperand(0);
1741    unsigned Reg = getRegForValue(RV);
1742    if (Reg == 0)
1743      return false;
1744
1745    // Only handle a single return value for now.
1746    if (ValLocs.size() != 1)
1747      return false;
1748
1749    CCValAssign &VA = ValLocs[0];
1750
1751    // Don't bother handling odd stuff for now.
1752    // FIXME: Should be able to handle i1, i8, and/or i16 return types.
1753    if (VA.getLocInfo() != CCValAssign::Full)
1754      return false;
1755    // Only handle register returns for now.
1756    if (!VA.isRegLoc())
1757      return false;
1758    // TODO: For now, don't try to handle cases where getLocInfo()
1759    // says Full but the types don't match.
1760    if (TLI.getValueType(RV->getType()) != VA.getValVT())
1761      return false;
1762
1763    // Make the copy.
1764    unsigned SrcReg = Reg + VA.getValNo();
1765    unsigned DstReg = VA.getLocReg();
1766    const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1767    // Avoid a cross-class copy. This is very unlikely.
1768    if (!SrcRC->contains(DstReg))
1769      return false;
1770    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1771            DstReg).addReg(SrcReg);
1772
1773    // Mark the register as live out of the function.
1774    MRI.addLiveOut(VA.getLocReg());
1775  }
1776
1777  unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1778  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1779                          TII.get(RetOpc)));
1780  return true;
1781}
1782
1783unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1784
1785  // Darwin needs the r9 versions of the opcodes.
1786  bool isDarwin = Subtarget->isTargetDarwin();
1787  if (isThumb) {
1788    return isDarwin ? ARM::tBLr9 : ARM::tBL;
1789  } else  {
1790    return isDarwin ? ARM::BLr9 : ARM::BL;
1791  }
1792}
1793
1794// A quick function that will emit a call for a named libcall in F with the
1795// vector of passed arguments for the Instruction in I. We can assume that we
1796// can emit a call for any libcall we can produce. This is an abridged version
1797// of the full call infrastructure since we won't need to worry about things
1798// like computed function pointers or strange arguments at call sites.
1799// TODO: Try to unify this and the normal call bits for ARM, then try to unify
1800// with X86.
1801bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1802  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1803
1804  // Handle *simple* calls for now.
1805  Type *RetTy = I->getType();
1806  MVT RetVT;
1807  if (RetTy->isVoidTy())
1808    RetVT = MVT::isVoid;
1809  else if (!isTypeLegal(RetTy, RetVT))
1810    return false;
1811
1812  // TODO: For now if we have long calls specified we don't handle the call.
1813  if (EnableARMLongCalls) return false;
1814
1815  // Set up the argument vectors.
1816  SmallVector<Value*, 8> Args;
1817  SmallVector<unsigned, 8> ArgRegs;
1818  SmallVector<MVT, 8> ArgVTs;
1819  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1820  Args.reserve(I->getNumOperands());
1821  ArgRegs.reserve(I->getNumOperands());
1822  ArgVTs.reserve(I->getNumOperands());
1823  ArgFlags.reserve(I->getNumOperands());
1824  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1825    Value *Op = I->getOperand(i);
1826    unsigned Arg = getRegForValue(Op);
1827    if (Arg == 0) return false;
1828
1829    Type *ArgTy = Op->getType();
1830    MVT ArgVT;
1831    if (!isTypeLegal(ArgTy, ArgVT)) return false;
1832
1833    ISD::ArgFlagsTy Flags;
1834    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1835    Flags.setOrigAlign(OriginalAlignment);
1836
1837    Args.push_back(Op);
1838    ArgRegs.push_back(Arg);
1839    ArgVTs.push_back(ArgVT);
1840    ArgFlags.push_back(Flags);
1841  }
1842
1843  // Handle the arguments now that we've gotten them.
1844  SmallVector<unsigned, 4> RegArgs;
1845  unsigned NumBytes;
1846  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1847    return false;
1848
1849  // Issue the call, BLr9 for darwin, BL otherwise.
1850  // TODO: Turn this into the table of arm call ops.
1851  MachineInstrBuilder MIB;
1852  unsigned CallOpc = ARMSelectCallOp(NULL);
1853  if(isThumb)
1854    // Explicitly adding the predicate here.
1855    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1856                         TII.get(CallOpc)))
1857                         .addExternalSymbol(TLI.getLibcallName(Call));
1858  else
1859    // Explicitly adding the predicate here.
1860    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1861                         TII.get(CallOpc))
1862          .addExternalSymbol(TLI.getLibcallName(Call)));
1863
1864  // Add implicit physical register uses to the call.
1865  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1866    MIB.addReg(RegArgs[i]);
1867
1868  // Finish off the call including any return values.
1869  SmallVector<unsigned, 4> UsedRegs;
1870  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1871
1872  // Set all unused physreg defs as dead.
1873  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1874
1875  return true;
1876}
1877
1878bool ARMFastISel::SelectCall(const Instruction *I) {
1879  const CallInst *CI = cast<CallInst>(I);
1880  const Value *Callee = CI->getCalledValue();
1881
1882  // Can't handle inline asm or worry about intrinsics yet.
1883  if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1884
1885  // Only handle global variable Callees.
1886  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1887  if (!GV)
1888    return false;
1889
1890  // Check the calling convention.
1891  ImmutableCallSite CS(CI);
1892  CallingConv::ID CC = CS.getCallingConv();
1893
1894  // TODO: Avoid some calling conventions?
1895
1896  // Let SDISel handle vararg functions.
1897  PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1898  FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1899  if (FTy->isVarArg())
1900    return false;
1901
1902  // Handle *simple* calls for now.
1903  Type *RetTy = I->getType();
1904  MVT RetVT;
1905  if (RetTy->isVoidTy())
1906    RetVT = MVT::isVoid;
1907  else if (!isTypeLegal(RetTy, RetVT))
1908    return false;
1909
1910  // TODO: For now if we have long calls specified we don't handle the call.
1911  if (EnableARMLongCalls) return false;
1912
1913  // Set up the argument vectors.
1914  SmallVector<Value*, 8> Args;
1915  SmallVector<unsigned, 8> ArgRegs;
1916  SmallVector<MVT, 8> ArgVTs;
1917  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1918  Args.reserve(CS.arg_size());
1919  ArgRegs.reserve(CS.arg_size());
1920  ArgVTs.reserve(CS.arg_size());
1921  ArgFlags.reserve(CS.arg_size());
1922  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1923       i != e; ++i) {
1924    unsigned Arg = getRegForValue(*i);
1925
1926    if (Arg == 0)
1927      return false;
1928    ISD::ArgFlagsTy Flags;
1929    unsigned AttrInd = i - CS.arg_begin() + 1;
1930    if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1931      Flags.setSExt();
1932    if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1933      Flags.setZExt();
1934
1935         // FIXME: Only handle *easy* calls for now.
1936    if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1937        CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1938        CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1939        CS.paramHasAttr(AttrInd, Attribute::ByVal))
1940      return false;
1941
1942    Type *ArgTy = (*i)->getType();
1943    MVT ArgVT;
1944    // FIXME: Should be able to handle i1, i8, and/or i16 parameters.
1945    if (!isTypeLegal(ArgTy, ArgVT))
1946      return false;
1947    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1948    Flags.setOrigAlign(OriginalAlignment);
1949
1950    Args.push_back(*i);
1951    ArgRegs.push_back(Arg);
1952    ArgVTs.push_back(ArgVT);
1953    ArgFlags.push_back(Flags);
1954  }
1955
1956  // Handle the arguments now that we've gotten them.
1957  SmallVector<unsigned, 4> RegArgs;
1958  unsigned NumBytes;
1959  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1960    return false;
1961
1962  // Issue the call, BLr9 for darwin, BL otherwise.
1963  // TODO: Turn this into the table of arm call ops.
1964  MachineInstrBuilder MIB;
1965  unsigned CallOpc = ARMSelectCallOp(GV);
1966  // Explicitly adding the predicate here.
1967  if(isThumb)
1968    // Explicitly adding the predicate here.
1969    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1970                         TII.get(CallOpc)))
1971          .addGlobalAddress(GV, 0, 0);
1972  else
1973    // Explicitly adding the predicate here.
1974    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1975                         TII.get(CallOpc))
1976          .addGlobalAddress(GV, 0, 0));
1977
1978  // Add implicit physical register uses to the call.
1979  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1980    MIB.addReg(RegArgs[i]);
1981
1982  // Finish off the call including any return values.
1983  SmallVector<unsigned, 4> UsedRegs;
1984  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1985
1986  // Set all unused physreg defs as dead.
1987  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1988
1989  return true;
1990
1991}
1992
1993bool ARMFastISel::SelectIntCast(const Instruction *I) {
1994  // On ARM, in general, integer casts don't involve legal types; this code
1995  // handles promotable integers.  The high bits for a type smaller than
1996  // the register size are assumed to be undefined.
1997  Type *DestTy = I->getType();
1998  Value *Op = I->getOperand(0);
1999  Type *SrcTy = Op->getType();
2000
2001  EVT SrcVT, DestVT;
2002  SrcVT = TLI.getValueType(SrcTy, true);
2003  DestVT = TLI.getValueType(DestTy, true);
2004
2005  if (isa<TruncInst>(I)) {
2006    if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2007      return false;
2008    if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2009      return false;
2010
2011    unsigned SrcReg = getRegForValue(Op);
2012    if (!SrcReg) return false;
2013
2014    // Because the high bits are undefined, a truncate doesn't generate
2015    // any code.
2016    UpdateValueMap(I, SrcReg);
2017    return true;
2018  }
2019  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2020    return false;
2021
2022  unsigned Opc;
2023  bool isZext = isa<ZExtInst>(I);
2024  bool isBoolZext = false;
2025  if (!SrcVT.isSimple())
2026    return false;
2027  switch (SrcVT.getSimpleVT().SimpleTy) {
2028  default: return false;
2029  case MVT::i16:
2030    if (!Subtarget->hasV6Ops()) return false;
2031    if (isZext)
2032      Opc = isThumb ? ARM::t2UXTH : ARM::UXTH;
2033    else
2034      Opc = isThumb ? ARM::t2SXTH : ARM::SXTH;
2035    break;
2036  case MVT::i8:
2037    if (!Subtarget->hasV6Ops()) return false;
2038    if (isZext)
2039      Opc = isThumb ? ARM::t2UXTB : ARM::UXTB;
2040    else
2041      Opc = isThumb ? ARM::t2SXTB : ARM::SXTB;
2042    break;
2043  case MVT::i1:
2044    if (isZext) {
2045      Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
2046      isBoolZext = true;
2047      break;
2048    }
2049    return false;
2050  }
2051
2052  // FIXME: We could save an instruction in many cases by special-casing
2053  // load instructions.
2054  unsigned SrcReg = getRegForValue(Op);
2055  if (!SrcReg) return false;
2056
2057  unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2058  MachineInstrBuilder MIB;
2059  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
2060        .addReg(SrcReg);
2061  if (isBoolZext)
2062    MIB.addImm(1);
2063  else
2064    MIB.addImm(0);
2065  AddOptionalDefs(MIB);
2066  UpdateValueMap(I, DestReg);
2067  return true;
2068}
2069
2070// TODO: SoftFP support.
2071bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2072
2073  switch (I->getOpcode()) {
2074    case Instruction::Load:
2075      return SelectLoad(I);
2076    case Instruction::Store:
2077      return SelectStore(I);
2078    case Instruction::Br:
2079      return SelectBranch(I);
2080    case Instruction::ICmp:
2081    case Instruction::FCmp:
2082      return SelectCmp(I);
2083    case Instruction::FPExt:
2084      return SelectFPExt(I);
2085    case Instruction::FPTrunc:
2086      return SelectFPTrunc(I);
2087    case Instruction::SIToFP:
2088      return SelectSIToFP(I);
2089    case Instruction::FPToSI:
2090      return SelectFPToSI(I);
2091    case Instruction::FAdd:
2092      return SelectBinaryOp(I, ISD::FADD);
2093    case Instruction::FSub:
2094      return SelectBinaryOp(I, ISD::FSUB);
2095    case Instruction::FMul:
2096      return SelectBinaryOp(I, ISD::FMUL);
2097    case Instruction::SDiv:
2098      return SelectSDiv(I);
2099    case Instruction::SRem:
2100      return SelectSRem(I);
2101    case Instruction::Call:
2102      return SelectCall(I);
2103    case Instruction::Select:
2104      return SelectSelect(I);
2105    case Instruction::Ret:
2106      return SelectRet(I);
2107    case Instruction::Trunc:
2108    case Instruction::ZExt:
2109    case Instruction::SExt:
2110      return SelectIntCast(I);
2111    default: break;
2112  }
2113  return false;
2114}
2115
2116namespace llvm {
2117  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2118    // Completely untested on non-darwin.
2119    const TargetMachine &TM = funcInfo.MF->getTarget();
2120
2121    // Darwin and thumb1 only for now.
2122    const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2123    if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2124        !DisableARMFastISel)
2125      return new ARMFastISel(funcInfo);
2126    return 0;
2127  }
2128}
2129