ARMFastISel.cpp revision 9eff1e33f616ad2d0134740ac4595ed2e79e3d74 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMRegisterInfo.h"
20#include "ARMTargetMachine.h"
21#include "ARMSubtarget.h"
22#include "ARMConstantPoolValue.h"
23#include "MCTargetDesc/ARMAddressingModes.h"
24#include "llvm/CallingConv.h"
25#include "llvm/DerivedTypes.h"
26#include "llvm/GlobalVariable.h"
27#include "llvm/Instructions.h"
28#include "llvm/IntrinsicInst.h"
29#include "llvm/Module.h"
30#include "llvm/Operator.h"
31#include "llvm/CodeGen/Analysis.h"
32#include "llvm/CodeGen/FastISel.h"
33#include "llvm/CodeGen/FunctionLoweringInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineModuleInfo.h"
36#include "llvm/CodeGen/MachineConstantPool.h"
37#include "llvm/CodeGen/MachineFrameInfo.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/MachineRegisterInfo.h"
40#include "llvm/Support/CallSite.h"
41#include "llvm/Support/CommandLine.h"
42#include "llvm/Support/ErrorHandling.h"
43#include "llvm/Support/GetElementPtrTypeIterator.h"
44#include "llvm/Target/TargetData.h"
45#include "llvm/Target/TargetInstrInfo.h"
46#include "llvm/Target/TargetLowering.h"
47#include "llvm/Target/TargetMachine.h"
48#include "llvm/Target/TargetOptions.h"
49using namespace llvm;
50
51static cl::opt<bool>
52DisableARMFastISel("disable-arm-fast-isel",
53                    cl::desc("Turn off experimental ARM fast-isel support"),
54                    cl::init(false), cl::Hidden);
55
56extern cl::opt<bool> EnableARMLongCalls;
57
58namespace {
59
60  // All possible address modes, plus some.
61  typedef struct Address {
62    enum {
63      RegBase,
64      FrameIndexBase
65    } BaseType;
66
67    union {
68      unsigned Reg;
69      int FI;
70    } Base;
71
72    int Offset;
73
74    // Innocuous defaults for our address.
75    Address()
76     : BaseType(RegBase), Offset(0) {
77       Base.Reg = 0;
78     }
79  } Address;
80
81class ARMFastISel : public FastISel {
82
83  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
84  /// make the right decision when generating code for different targets.
85  const ARMSubtarget *Subtarget;
86  const TargetMachine &TM;
87  const TargetInstrInfo &TII;
88  const TargetLowering &TLI;
89  ARMFunctionInfo *AFI;
90
91  // Convenience variables to avoid some queries.
92  bool isThumb2;
93  LLVMContext *Context;
94
95  public:
96    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
97    : FastISel(funcInfo),
98      TM(funcInfo.MF->getTarget()),
99      TII(*TM.getInstrInfo()),
100      TLI(*TM.getTargetLowering()) {
101      Subtarget = &TM.getSubtarget<ARMSubtarget>();
102      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
103      isThumb2 = AFI->isThumbFunction();
104      Context = &funcInfo.Fn->getContext();
105    }
106
107    // Code from FastISel.cpp.
108    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
109                                   const TargetRegisterClass *RC);
110    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
111                                    const TargetRegisterClass *RC,
112                                    unsigned Op0, bool Op0IsKill);
113    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
114                                     const TargetRegisterClass *RC,
115                                     unsigned Op0, bool Op0IsKill,
116                                     unsigned Op1, bool Op1IsKill);
117    virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
118                                      const TargetRegisterClass *RC,
119                                      unsigned Op0, bool Op0IsKill,
120                                      unsigned Op1, bool Op1IsKill,
121                                      unsigned Op2, bool Op2IsKill);
122    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
123                                     const TargetRegisterClass *RC,
124                                     unsigned Op0, bool Op0IsKill,
125                                     uint64_t Imm);
126    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
127                                     const TargetRegisterClass *RC,
128                                     unsigned Op0, bool Op0IsKill,
129                                     const ConstantFP *FPImm);
130    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
131                                      const TargetRegisterClass *RC,
132                                      unsigned Op0, bool Op0IsKill,
133                                      unsigned Op1, bool Op1IsKill,
134                                      uint64_t Imm);
135    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
136                                    const TargetRegisterClass *RC,
137                                    uint64_t Imm);
138    virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
139                                     const TargetRegisterClass *RC,
140                                     uint64_t Imm1, uint64_t Imm2);
141
142    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
143                                                unsigned Op0, bool Op0IsKill,
144                                                uint32_t Idx);
145
146    // Backend specific FastISel code.
147    virtual bool TargetSelectInstruction(const Instruction *I);
148    virtual unsigned TargetMaterializeConstant(const Constant *C);
149    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
150    virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
151                               const LoadInst *LI);
152
153  #include "ARMGenFastISel.inc"
154
155    // Instruction selection routines.
156  private:
157    bool SelectLoad(const Instruction *I);
158    bool SelectStore(const Instruction *I);
159    bool SelectBranch(const Instruction *I);
160    bool SelectCmp(const Instruction *I);
161    bool SelectFPExt(const Instruction *I);
162    bool SelectFPTrunc(const Instruction *I);
163    bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
164    bool SelectSIToFP(const Instruction *I);
165    bool SelectFPToSI(const Instruction *I);
166    bool SelectSDiv(const Instruction *I);
167    bool SelectSRem(const Instruction *I);
168    bool SelectCall(const Instruction *I, const char *IntrMemName);
169    bool SelectIntrinsicCall(const IntrinsicInst &I);
170    bool SelectSelect(const Instruction *I);
171    bool SelectRet(const Instruction *I);
172    bool SelectTrunc(const Instruction *I);
173    bool SelectIntExt(const Instruction *I);
174
175    // Utility routines.
176  private:
177    bool isTypeLegal(Type *Ty, MVT &VT);
178    bool isLoadTypeLegal(Type *Ty, MVT &VT);
179    bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
180                    bool isZExt);
181    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, bool isZExt,
182                     bool allocReg);
183
184    bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, unsigned Alignment = 0);
185    bool ARMComputeAddress(const Value *Obj, Address &Addr);
186    void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
187    bool ARMIsMemCpySmall(uint64_t Len);
188    bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len);
189    unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
190    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
191    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
192    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
193    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
194    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
195    unsigned ARMSelectCallOp(const GlobalValue *GV);
196
197    // Call handling routines.
198  private:
199    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
200    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
201                         SmallVectorImpl<unsigned> &ArgRegs,
202                         SmallVectorImpl<MVT> &ArgVTs,
203                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
204                         SmallVectorImpl<unsigned> &RegArgs,
205                         CallingConv::ID CC,
206                         unsigned &NumBytes);
207    bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
208                    const Instruction *I, CallingConv::ID CC,
209                    unsigned &NumBytes);
210    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
211
212    // OptionalDef handling routines.
213  private:
214    bool isARMNEONPred(const MachineInstr *MI);
215    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
216    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
217    void AddLoadStoreOperands(EVT VT, Address &Addr,
218                              const MachineInstrBuilder &MIB,
219                              unsigned Flags, bool useAM3);
220};
221
222} // end anonymous namespace
223
224#include "ARMGenCallingConv.inc"
225
226// DefinesOptionalPredicate - This is different from DefinesPredicate in that
227// we don't care about implicit defs here, just places we'll need to add a
228// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
229bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
230  const MCInstrDesc &MCID = MI->getDesc();
231  if (!MCID.hasOptionalDef())
232    return false;
233
234  // Look to see if our OptionalDef is defining CPSR or CCR.
235  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236    const MachineOperand &MO = MI->getOperand(i);
237    if (!MO.isReg() || !MO.isDef()) continue;
238    if (MO.getReg() == ARM::CPSR)
239      *CPSR = true;
240  }
241  return true;
242}
243
244bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
245  const MCInstrDesc &MCID = MI->getDesc();
246
247  // If we're a thumb2 or not NEON function we were handled via isPredicable.
248  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
249       AFI->isThumb2Function())
250    return false;
251
252  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
253    if (MCID.OpInfo[i].isPredicate())
254      return true;
255
256  return false;
257}
258
259// If the machine is predicable go ahead and add the predicate operands, if
260// it needs default CC operands add those.
261// TODO: If we want to support thumb1 then we'll need to deal with optional
262// CPSR defs that need to be added before the remaining operands. See s_cc_out
263// for descriptions why.
264const MachineInstrBuilder &
265ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
266  MachineInstr *MI = &*MIB;
267
268  // Do we use a predicate? or...
269  // Are we NEON in ARM mode and have a predicate operand? If so, I know
270  // we're not predicable but add it anyways.
271  if (TII.isPredicable(MI) || isARMNEONPred(MI))
272    AddDefaultPred(MIB);
273
274  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
275  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
276  bool CPSR = false;
277  if (DefinesOptionalPredicate(MI, &CPSR)) {
278    if (CPSR)
279      AddDefaultT1CC(MIB);
280    else
281      AddDefaultCC(MIB);
282  }
283  return MIB;
284}
285
286unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
287                                    const TargetRegisterClass* RC) {
288  unsigned ResultReg = createResultReg(RC);
289  const MCInstrDesc &II = TII.get(MachineInstOpcode);
290
291  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
292  return ResultReg;
293}
294
295unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
296                                     const TargetRegisterClass *RC,
297                                     unsigned Op0, bool Op0IsKill) {
298  unsigned ResultReg = createResultReg(RC);
299  const MCInstrDesc &II = TII.get(MachineInstOpcode);
300
301  if (II.getNumDefs() >= 1)
302    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
303                   .addReg(Op0, Op0IsKill * RegState::Kill));
304  else {
305    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
306                   .addReg(Op0, Op0IsKill * RegState::Kill));
307    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
308                   TII.get(TargetOpcode::COPY), ResultReg)
309                   .addReg(II.ImplicitDefs[0]));
310  }
311  return ResultReg;
312}
313
314unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
315                                      const TargetRegisterClass *RC,
316                                      unsigned Op0, bool Op0IsKill,
317                                      unsigned Op1, bool Op1IsKill) {
318  unsigned ResultReg = createResultReg(RC);
319  const MCInstrDesc &II = TII.get(MachineInstOpcode);
320
321  if (II.getNumDefs() >= 1)
322    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
323                   .addReg(Op0, Op0IsKill * RegState::Kill)
324                   .addReg(Op1, Op1IsKill * RegState::Kill));
325  else {
326    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
327                   .addReg(Op0, Op0IsKill * RegState::Kill)
328                   .addReg(Op1, Op1IsKill * RegState::Kill));
329    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
330                           TII.get(TargetOpcode::COPY), ResultReg)
331                   .addReg(II.ImplicitDefs[0]));
332  }
333  return ResultReg;
334}
335
336unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
337                                       const TargetRegisterClass *RC,
338                                       unsigned Op0, bool Op0IsKill,
339                                       unsigned Op1, bool Op1IsKill,
340                                       unsigned Op2, bool Op2IsKill) {
341  unsigned ResultReg = createResultReg(RC);
342  const MCInstrDesc &II = TII.get(MachineInstOpcode);
343
344  if (II.getNumDefs() >= 1)
345    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
346                   .addReg(Op0, Op0IsKill * RegState::Kill)
347                   .addReg(Op1, Op1IsKill * RegState::Kill)
348                   .addReg(Op2, Op2IsKill * RegState::Kill));
349  else {
350    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
351                   .addReg(Op0, Op0IsKill * RegState::Kill)
352                   .addReg(Op1, Op1IsKill * RegState::Kill)
353                   .addReg(Op2, Op2IsKill * RegState::Kill));
354    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
355                           TII.get(TargetOpcode::COPY), ResultReg)
356                   .addReg(II.ImplicitDefs[0]));
357  }
358  return ResultReg;
359}
360
361unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
362                                      const TargetRegisterClass *RC,
363                                      unsigned Op0, bool Op0IsKill,
364                                      uint64_t Imm) {
365  unsigned ResultReg = createResultReg(RC);
366  const MCInstrDesc &II = TII.get(MachineInstOpcode);
367
368  if (II.getNumDefs() >= 1)
369    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
370                   .addReg(Op0, Op0IsKill * RegState::Kill)
371                   .addImm(Imm));
372  else {
373    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
374                   .addReg(Op0, Op0IsKill * RegState::Kill)
375                   .addImm(Imm));
376    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
377                           TII.get(TargetOpcode::COPY), ResultReg)
378                   .addReg(II.ImplicitDefs[0]));
379  }
380  return ResultReg;
381}
382
383unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
384                                      const TargetRegisterClass *RC,
385                                      unsigned Op0, bool Op0IsKill,
386                                      const ConstantFP *FPImm) {
387  unsigned ResultReg = createResultReg(RC);
388  const MCInstrDesc &II = TII.get(MachineInstOpcode);
389
390  if (II.getNumDefs() >= 1)
391    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
392                   .addReg(Op0, Op0IsKill * RegState::Kill)
393                   .addFPImm(FPImm));
394  else {
395    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
396                   .addReg(Op0, Op0IsKill * RegState::Kill)
397                   .addFPImm(FPImm));
398    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
399                           TII.get(TargetOpcode::COPY), ResultReg)
400                   .addReg(II.ImplicitDefs[0]));
401  }
402  return ResultReg;
403}
404
405unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
406                                       const TargetRegisterClass *RC,
407                                       unsigned Op0, bool Op0IsKill,
408                                       unsigned Op1, bool Op1IsKill,
409                                       uint64_t Imm) {
410  unsigned ResultReg = createResultReg(RC);
411  const MCInstrDesc &II = TII.get(MachineInstOpcode);
412
413  if (II.getNumDefs() >= 1)
414    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
415                   .addReg(Op0, Op0IsKill * RegState::Kill)
416                   .addReg(Op1, Op1IsKill * RegState::Kill)
417                   .addImm(Imm));
418  else {
419    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
420                   .addReg(Op0, Op0IsKill * RegState::Kill)
421                   .addReg(Op1, Op1IsKill * RegState::Kill)
422                   .addImm(Imm));
423    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
424                           TII.get(TargetOpcode::COPY), ResultReg)
425                   .addReg(II.ImplicitDefs[0]));
426  }
427  return ResultReg;
428}
429
430unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
431                                     const TargetRegisterClass *RC,
432                                     uint64_t Imm) {
433  unsigned ResultReg = createResultReg(RC);
434  const MCInstrDesc &II = TII.get(MachineInstOpcode);
435
436  if (II.getNumDefs() >= 1)
437    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
438                   .addImm(Imm));
439  else {
440    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
441                   .addImm(Imm));
442    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
443                           TII.get(TargetOpcode::COPY), ResultReg)
444                   .addReg(II.ImplicitDefs[0]));
445  }
446  return ResultReg;
447}
448
449unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
450                                      const TargetRegisterClass *RC,
451                                      uint64_t Imm1, uint64_t Imm2) {
452  unsigned ResultReg = createResultReg(RC);
453  const MCInstrDesc &II = TII.get(MachineInstOpcode);
454
455  if (II.getNumDefs() >= 1)
456    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
457                    .addImm(Imm1).addImm(Imm2));
458  else {
459    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
460                    .addImm(Imm1).addImm(Imm2));
461    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
462                            TII.get(TargetOpcode::COPY),
463                            ResultReg)
464                    .addReg(II.ImplicitDefs[0]));
465  }
466  return ResultReg;
467}
468
469unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
470                                                 unsigned Op0, bool Op0IsKill,
471                                                 uint32_t Idx) {
472  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
473  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
474         "Cannot yet extract from physregs");
475  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
476                         DL, TII.get(TargetOpcode::COPY), ResultReg)
477                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
478  return ResultReg;
479}
480
481// TODO: Don't worry about 64-bit now, but when this is fixed remove the
482// checks from the various callers.
483unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
484  if (VT == MVT::f64) return 0;
485
486  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
487  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
488                          TII.get(ARM::VMOVRS), MoveReg)
489                  .addReg(SrcReg));
490  return MoveReg;
491}
492
493unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
494  if (VT == MVT::i64) return 0;
495
496  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
497  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
498                          TII.get(ARM::VMOVSR), MoveReg)
499                  .addReg(SrcReg));
500  return MoveReg;
501}
502
503// For double width floating point we need to materialize two constants
504// (the high and the low) into integer registers then use a move to get
505// the combined constant into an FP reg.
506unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
507  const APFloat Val = CFP->getValueAPF();
508  bool is64bit = VT == MVT::f64;
509
510  // This checks to see if we can use VFP3 instructions to materialize
511  // a constant, otherwise we have to go through the constant pool.
512  if (TLI.isFPImmLegal(Val, VT)) {
513    int Imm;
514    unsigned Opc;
515    if (is64bit) {
516      Imm = ARM_AM::getFP64Imm(Val);
517      Opc = ARM::FCONSTD;
518    } else {
519      Imm = ARM_AM::getFP32Imm(Val);
520      Opc = ARM::FCONSTS;
521    }
522    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
523    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
524                            DestReg)
525                    .addImm(Imm));
526    return DestReg;
527  }
528
529  // Require VFP2 for loading fp constants.
530  if (!Subtarget->hasVFP2()) return false;
531
532  // MachineConstantPool wants an explicit alignment.
533  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
534  if (Align == 0) {
535    // TODO: Figure out if this is correct.
536    Align = TD.getTypeAllocSize(CFP->getType());
537  }
538  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
539  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
540  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
541
542  // The extra reg is for addrmode5.
543  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
544                          DestReg)
545                  .addConstantPoolIndex(Idx)
546                  .addReg(0));
547  return DestReg;
548}
549
550unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
551
552  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
553    return false;
554
555  // If we can do this in a single instruction without a constant pool entry
556  // do so now.
557  const ConstantInt *CI = cast<ConstantInt>(C);
558  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
559    unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
560    unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
561    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
562                            TII.get(Opc), ImmReg)
563                    .addImm(CI->getZExtValue()));
564    return ImmReg;
565  }
566
567  // Use MVN to emit negative constants.
568  if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
569    unsigned Imm = (unsigned)~(CI->getSExtValue());
570    bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
571      (ARM_AM::getSOImmVal(Imm) != -1);
572    if (UseImm) {
573      unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
574      unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
575      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
576                              TII.get(Opc), ImmReg)
577                      .addImm(Imm));
578      return ImmReg;
579    }
580  }
581
582  // Load from constant pool.  For now 32-bit only.
583  if (VT != MVT::i32)
584    return false;
585
586  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
587
588  // MachineConstantPool wants an explicit alignment.
589  unsigned Align = TD.getPrefTypeAlignment(C->getType());
590  if (Align == 0) {
591    // TODO: Figure out if this is correct.
592    Align = TD.getTypeAllocSize(C->getType());
593  }
594  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
595
596  if (isThumb2)
597    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
598                            TII.get(ARM::t2LDRpci), DestReg)
599                    .addConstantPoolIndex(Idx));
600  else
601    // The extra immediate is for addrmode2.
602    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
603                            TII.get(ARM::LDRcp), DestReg)
604                    .addConstantPoolIndex(Idx)
605                    .addImm(0));
606
607  return DestReg;
608}
609
610unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
611  // For now 32-bit only.
612  if (VT != MVT::i32) return 0;
613
614  Reloc::Model RelocM = TM.getRelocationModel();
615
616  // TODO: Need more magic for ARM PIC.
617  if (!isThumb2 && (RelocM == Reloc::PIC_)) return 0;
618
619  // MachineConstantPool wants an explicit alignment.
620  unsigned Align = TD.getPrefTypeAlignment(GV->getType());
621  if (Align == 0) {
622    // TODO: Figure out if this is correct.
623    Align = TD.getTypeAllocSize(GV->getType());
624  }
625
626  // Grab index.
627  unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
628  unsigned Id = AFI->createPICLabelUId();
629  ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
630                                                              ARMCP::CPValue,
631                                                              PCAdj);
632  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
633
634  // Load value.
635  MachineInstrBuilder MIB;
636  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
637  if (isThumb2) {
638    unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
639    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
640          .addConstantPoolIndex(Idx);
641    if (RelocM == Reloc::PIC_)
642      MIB.addImm(Id);
643  } else {
644    // The extra immediate is for addrmode2.
645    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
646                  DestReg)
647          .addConstantPoolIndex(Idx)
648          .addImm(0);
649  }
650  AddOptionalDefs(MIB);
651
652  if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
653    unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
654    if (isThumb2)
655      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
656                    TII.get(ARM::t2LDRi12), NewDestReg)
657            .addReg(DestReg)
658            .addImm(0);
659    else
660      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
661                    NewDestReg)
662            .addReg(DestReg)
663            .addImm(0);
664    DestReg = NewDestReg;
665    AddOptionalDefs(MIB);
666  }
667
668  return DestReg;
669}
670
671unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
672  EVT VT = TLI.getValueType(C->getType(), true);
673
674  // Only handle simple types.
675  if (!VT.isSimple()) return 0;
676
677  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
678    return ARMMaterializeFP(CFP, VT);
679  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
680    return ARMMaterializeGV(GV, VT);
681  else if (isa<ConstantInt>(C))
682    return ARMMaterializeInt(C, VT);
683
684  return 0;
685}
686
687// TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
688
689unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
690  // Don't handle dynamic allocas.
691  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
692
693  MVT VT;
694  if (!isLoadTypeLegal(AI->getType(), VT)) return false;
695
696  DenseMap<const AllocaInst*, int>::iterator SI =
697    FuncInfo.StaticAllocaMap.find(AI);
698
699  // This will get lowered later into the correct offsets and registers
700  // via rewriteXFrameIndex.
701  if (SI != FuncInfo.StaticAllocaMap.end()) {
702    TargetRegisterClass* RC = TLI.getRegClassFor(VT);
703    unsigned ResultReg = createResultReg(RC);
704    unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
705    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
706                            TII.get(Opc), ResultReg)
707                            .addFrameIndex(SI->second)
708                            .addImm(0));
709    return ResultReg;
710  }
711
712  return 0;
713}
714
715bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
716  EVT evt = TLI.getValueType(Ty, true);
717
718  // Only handle simple types.
719  if (evt == MVT::Other || !evt.isSimple()) return false;
720  VT = evt.getSimpleVT();
721
722  // Handle all legal types, i.e. a register that will directly hold this
723  // value.
724  return TLI.isTypeLegal(VT);
725}
726
727bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
728  if (isTypeLegal(Ty, VT)) return true;
729
730  // If this is a type than can be sign or zero-extended to a basic operation
731  // go ahead and accept it now.
732  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
733    return true;
734
735  return false;
736}
737
738// Computes the address to get to an object.
739bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
740  // Some boilerplate from the X86 FastISel.
741  const User *U = NULL;
742  unsigned Opcode = Instruction::UserOp1;
743  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
744    // Don't walk into other basic blocks unless the object is an alloca from
745    // another block, otherwise it may not have a virtual register assigned.
746    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
747        FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
748      Opcode = I->getOpcode();
749      U = I;
750    }
751  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
752    Opcode = C->getOpcode();
753    U = C;
754  }
755
756  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
757    if (Ty->getAddressSpace() > 255)
758      // Fast instruction selection doesn't support the special
759      // address spaces.
760      return false;
761
762  switch (Opcode) {
763    default:
764    break;
765    case Instruction::BitCast: {
766      // Look through bitcasts.
767      return ARMComputeAddress(U->getOperand(0), Addr);
768    }
769    case Instruction::IntToPtr: {
770      // Look past no-op inttoptrs.
771      if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
772        return ARMComputeAddress(U->getOperand(0), Addr);
773      break;
774    }
775    case Instruction::PtrToInt: {
776      // Look past no-op ptrtoints.
777      if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
778        return ARMComputeAddress(U->getOperand(0), Addr);
779      break;
780    }
781    case Instruction::GetElementPtr: {
782      Address SavedAddr = Addr;
783      int TmpOffset = Addr.Offset;
784
785      // Iterate through the GEP folding the constants into offsets where
786      // we can.
787      gep_type_iterator GTI = gep_type_begin(U);
788      for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
789           i != e; ++i, ++GTI) {
790        const Value *Op = *i;
791        if (StructType *STy = dyn_cast<StructType>(*GTI)) {
792          const StructLayout *SL = TD.getStructLayout(STy);
793          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
794          TmpOffset += SL->getElementOffset(Idx);
795        } else {
796          uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
797          for (;;) {
798            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
799              // Constant-offset addressing.
800              TmpOffset += CI->getSExtValue() * S;
801              break;
802            }
803            if (isa<AddOperator>(Op) &&
804                (!isa<Instruction>(Op) ||
805                 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
806                 == FuncInfo.MBB) &&
807                isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
808              // An add (in the same block) with a constant operand. Fold the
809              // constant.
810              ConstantInt *CI =
811              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
812              TmpOffset += CI->getSExtValue() * S;
813              // Iterate on the other operand.
814              Op = cast<AddOperator>(Op)->getOperand(0);
815              continue;
816            }
817            // Unsupported
818            goto unsupported_gep;
819          }
820        }
821      }
822
823      // Try to grab the base operand now.
824      Addr.Offset = TmpOffset;
825      if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
826
827      // We failed, restore everything and try the other options.
828      Addr = SavedAddr;
829
830      unsupported_gep:
831      break;
832    }
833    case Instruction::Alloca: {
834      const AllocaInst *AI = cast<AllocaInst>(Obj);
835      DenseMap<const AllocaInst*, int>::iterator SI =
836        FuncInfo.StaticAllocaMap.find(AI);
837      if (SI != FuncInfo.StaticAllocaMap.end()) {
838        Addr.BaseType = Address::FrameIndexBase;
839        Addr.Base.FI = SI->second;
840        return true;
841      }
842      break;
843    }
844  }
845
846  // Materialize the global variable's address into a reg which can
847  // then be used later to load the variable.
848  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
849    unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
850    if (Tmp == 0) return false;
851
852    Addr.Base.Reg = Tmp;
853    return true;
854  }
855
856  // Try to get this in a register if nothing else has worked.
857  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
858  return Addr.Base.Reg != 0;
859}
860
861void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
862
863  assert(VT.isSimple() && "Non-simple types are invalid here!");
864
865  bool needsLowering = false;
866  switch (VT.getSimpleVT().SimpleTy) {
867    default:
868      assert(false && "Unhandled load/store type!");
869      break;
870    case MVT::i1:
871    case MVT::i8:
872    case MVT::i16:
873    case MVT::i32:
874      if (!useAM3) {
875        // Integer loads/stores handle 12-bit offsets.
876        needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
877        // Handle negative offsets.
878        if (needsLowering && isThumb2)
879          needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
880                            Addr.Offset > -256);
881      } else {
882        // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
883        needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
884      }
885      break;
886    case MVT::f32:
887    case MVT::f64:
888      // Floating point operands handle 8-bit offsets.
889      needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
890      break;
891  }
892
893  // If this is a stack pointer and the offset needs to be simplified then
894  // put the alloca address into a register, set the base type back to
895  // register and continue. This should almost never happen.
896  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
897    TargetRegisterClass *RC = isThumb2 ? ARM::tGPRRegisterClass :
898                              ARM::GPRRegisterClass;
899    unsigned ResultReg = createResultReg(RC);
900    unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
901    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
902                            TII.get(Opc), ResultReg)
903                            .addFrameIndex(Addr.Base.FI)
904                            .addImm(0));
905    Addr.Base.Reg = ResultReg;
906    Addr.BaseType = Address::RegBase;
907  }
908
909  // Since the offset is too large for the load/store instruction
910  // get the reg+offset into a register.
911  if (needsLowering) {
912    Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
913                                 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
914    Addr.Offset = 0;
915  }
916}
917
918void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
919                                       const MachineInstrBuilder &MIB,
920                                       unsigned Flags, bool useAM3) {
921  // addrmode5 output depends on the selection dag addressing dividing the
922  // offset by 4 that it then later multiplies. Do this here as well.
923  if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
924      VT.getSimpleVT().SimpleTy == MVT::f64)
925    Addr.Offset /= 4;
926
927  // Frame base works a bit differently. Handle it separately.
928  if (Addr.BaseType == Address::FrameIndexBase) {
929    int FI = Addr.Base.FI;
930    int Offset = Addr.Offset;
931    MachineMemOperand *MMO =
932          FuncInfo.MF->getMachineMemOperand(
933                                  MachinePointerInfo::getFixedStack(FI, Offset),
934                                  Flags,
935                                  MFI.getObjectSize(FI),
936                                  MFI.getObjectAlignment(FI));
937    // Now add the rest of the operands.
938    MIB.addFrameIndex(FI);
939
940    // ARM halfword load/stores and signed byte loads need an additional operand.
941    if (useAM3) {
942      signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
943      MIB.addReg(0);
944      MIB.addImm(Imm);
945    } else {
946      MIB.addImm(Addr.Offset);
947    }
948    MIB.addMemOperand(MMO);
949  } else {
950    // Now add the rest of the operands.
951    MIB.addReg(Addr.Base.Reg);
952
953    // ARM halfword load/stores and signed byte loads need an additional operand.
954    if (useAM3) {
955      signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
956      MIB.addReg(0);
957      MIB.addImm(Imm);
958    } else {
959      MIB.addImm(Addr.Offset);
960    }
961  }
962  AddOptionalDefs(MIB);
963}
964
965bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
966                              bool isZExt = true, bool allocReg = true) {
967  assert(VT.isSimple() && "Non-simple types are invalid here!");
968  unsigned Opc;
969  bool useAM3 = false;
970  TargetRegisterClass *RC;
971  switch (VT.getSimpleVT().SimpleTy) {
972    // This is mostly going to be Neon/vector support.
973    default: return false;
974    case MVT::i1:
975    case MVT::i8:
976      if (isThumb2) {
977        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
978          Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
979        else
980          Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
981      } else {
982        if (isZExt) {
983          Opc = ARM::LDRBi12;
984        } else {
985          Opc = ARM::LDRSB;
986          useAM3 = true;
987        }
988      }
989      RC = ARM::GPRRegisterClass;
990      break;
991    case MVT::i16:
992      if (isThumb2) {
993        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
994          Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
995        else
996          Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
997      } else {
998        Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
999        useAM3 = true;
1000      }
1001      RC = ARM::GPRRegisterClass;
1002      break;
1003    case MVT::i32:
1004      if (isThumb2) {
1005        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1006          Opc = ARM::t2LDRi8;
1007        else
1008          Opc = ARM::t2LDRi12;
1009      } else {
1010        Opc = ARM::LDRi12;
1011      }
1012      RC = ARM::GPRRegisterClass;
1013      break;
1014    case MVT::f32:
1015      Opc = ARM::VLDRS;
1016      RC = TLI.getRegClassFor(VT);
1017      break;
1018    case MVT::f64:
1019      Opc = ARM::VLDRD;
1020      RC = TLI.getRegClassFor(VT);
1021      break;
1022  }
1023  // Simplify this down to something we can handle.
1024  ARMSimplifyAddress(Addr, VT, useAM3);
1025
1026  // Create the base instruction, then add the operands.
1027  if (allocReg)
1028    ResultReg = createResultReg(RC);
1029  assert (ResultReg > 255 && "Expected an allocated virtual register.");
1030  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1031                                    TII.get(Opc), ResultReg);
1032  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1033  return true;
1034}
1035
1036bool ARMFastISel::SelectLoad(const Instruction *I) {
1037  // Atomic loads need special handling.
1038  if (cast<LoadInst>(I)->isAtomic())
1039    return false;
1040
1041  // Verify we have a legal type before going any further.
1042  MVT VT;
1043  if (!isLoadTypeLegal(I->getType(), VT))
1044    return false;
1045
1046  // See if we can handle this address.
1047  Address Addr;
1048  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1049
1050  unsigned ResultReg;
1051  if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
1052  UpdateValueMap(I, ResultReg);
1053  return true;
1054}
1055
1056bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, unsigned Alignment) {
1057  unsigned StrOpc;
1058  bool useAM3 = false;
1059  switch (VT.getSimpleVT().SimpleTy) {
1060    // This is mostly going to be Neon/vector support.
1061    default: return false;
1062    case MVT::i1: {
1063      unsigned Res = createResultReg(isThumb2 ? ARM::tGPRRegisterClass :
1064                                               ARM::GPRRegisterClass);
1065      unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1066      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1067                              TII.get(Opc), Res)
1068                      .addReg(SrcReg).addImm(1));
1069      SrcReg = Res;
1070    } // Fallthrough here.
1071    case MVT::i8:
1072      if (isThumb2) {
1073        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1074          StrOpc = ARM::t2STRBi8;
1075        else
1076          StrOpc = ARM::t2STRBi12;
1077      } else {
1078        StrOpc = ARM::STRBi12;
1079      }
1080      break;
1081    case MVT::i16:
1082      if (isThumb2) {
1083        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1084          StrOpc = ARM::t2STRHi8;
1085        else
1086          StrOpc = ARM::t2STRHi12;
1087      } else {
1088        StrOpc = ARM::STRH;
1089        useAM3 = true;
1090      }
1091      break;
1092    case MVT::i32:
1093      if (isThumb2) {
1094        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1095          StrOpc = ARM::t2STRi8;
1096        else
1097          StrOpc = ARM::t2STRi12;
1098      } else {
1099        StrOpc = ARM::STRi12;
1100      }
1101      break;
1102    case MVT::f32:
1103      if (!Subtarget->hasVFP2()) return false;
1104      StrOpc = ARM::VSTRS;
1105      // Unaligned stores need special handling.
1106      if (Alignment && Alignment < 4) {
1107        unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1108        AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1109                                TII.get(ARM::VMOVRS), MoveReg)
1110                        .addReg(SrcReg));
1111        SrcReg = MoveReg;
1112        VT = MVT::i32;
1113        StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1114      }
1115      break;
1116    case MVT::f64:
1117      if (!Subtarget->hasVFP2()) return false;
1118      // FIXME: Unaligned stores need special handling.
1119      if (Alignment && Alignment < 8) {
1120          return false;
1121      }
1122      StrOpc = ARM::VSTRD;
1123      break;
1124  }
1125  // Simplify this down to something we can handle.
1126  ARMSimplifyAddress(Addr, VT, useAM3);
1127
1128  // Create the base instruction, then add the operands.
1129  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1130                                    TII.get(StrOpc))
1131                            .addReg(SrcReg);
1132  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1133  return true;
1134}
1135
1136bool ARMFastISel::SelectStore(const Instruction *I) {
1137  Value *Op0 = I->getOperand(0);
1138  unsigned SrcReg = 0;
1139
1140  // Atomic stores need special handling.
1141  if (cast<StoreInst>(I)->isAtomic())
1142    return false;
1143
1144  // Verify we have a legal type before going any further.
1145  MVT VT;
1146  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1147    return false;
1148
1149  // Get the value to be stored into a register.
1150  SrcReg = getRegForValue(Op0);
1151  if (SrcReg == 0) return false;
1152
1153  // See if we can handle this address.
1154  Address Addr;
1155  if (!ARMComputeAddress(I->getOperand(1), Addr))
1156    return false;
1157
1158  if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1159    return false;
1160  return true;
1161}
1162
1163static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1164  switch (Pred) {
1165    // Needs two compares...
1166    case CmpInst::FCMP_ONE:
1167    case CmpInst::FCMP_UEQ:
1168    default:
1169      // AL is our "false" for now. The other two need more compares.
1170      return ARMCC::AL;
1171    case CmpInst::ICMP_EQ:
1172    case CmpInst::FCMP_OEQ:
1173      return ARMCC::EQ;
1174    case CmpInst::ICMP_SGT:
1175    case CmpInst::FCMP_OGT:
1176      return ARMCC::GT;
1177    case CmpInst::ICMP_SGE:
1178    case CmpInst::FCMP_OGE:
1179      return ARMCC::GE;
1180    case CmpInst::ICMP_UGT:
1181    case CmpInst::FCMP_UGT:
1182      return ARMCC::HI;
1183    case CmpInst::FCMP_OLT:
1184      return ARMCC::MI;
1185    case CmpInst::ICMP_ULE:
1186    case CmpInst::FCMP_OLE:
1187      return ARMCC::LS;
1188    case CmpInst::FCMP_ORD:
1189      return ARMCC::VC;
1190    case CmpInst::FCMP_UNO:
1191      return ARMCC::VS;
1192    case CmpInst::FCMP_UGE:
1193      return ARMCC::PL;
1194    case CmpInst::ICMP_SLT:
1195    case CmpInst::FCMP_ULT:
1196      return ARMCC::LT;
1197    case CmpInst::ICMP_SLE:
1198    case CmpInst::FCMP_ULE:
1199      return ARMCC::LE;
1200    case CmpInst::FCMP_UNE:
1201    case CmpInst::ICMP_NE:
1202      return ARMCC::NE;
1203    case CmpInst::ICMP_UGE:
1204      return ARMCC::HS;
1205    case CmpInst::ICMP_ULT:
1206      return ARMCC::LO;
1207  }
1208}
1209
1210bool ARMFastISel::SelectBranch(const Instruction *I) {
1211  const BranchInst *BI = cast<BranchInst>(I);
1212  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1213  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1214
1215  // Simple branch support.
1216
1217  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1218  // behavior.
1219  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1220    if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1221
1222      // Get the compare predicate.
1223      // Try to take advantage of fallthrough opportunities.
1224      CmpInst::Predicate Predicate = CI->getPredicate();
1225      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1226        std::swap(TBB, FBB);
1227        Predicate = CmpInst::getInversePredicate(Predicate);
1228      }
1229
1230      ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1231
1232      // We may not handle every CC for now.
1233      if (ARMPred == ARMCC::AL) return false;
1234
1235      // Emit the compare.
1236      if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1237        return false;
1238
1239      unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1240      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1241      .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1242      FastEmitBranch(FBB, DL);
1243      FuncInfo.MBB->addSuccessor(TBB);
1244      return true;
1245    }
1246  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1247    MVT SourceVT;
1248    if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1249        (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1250      unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1251      unsigned OpReg = getRegForValue(TI->getOperand(0));
1252      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1253                              TII.get(TstOpc))
1254                      .addReg(OpReg).addImm(1));
1255
1256      unsigned CCMode = ARMCC::NE;
1257      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1258        std::swap(TBB, FBB);
1259        CCMode = ARMCC::EQ;
1260      }
1261
1262      unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1263      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1264      .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1265
1266      FastEmitBranch(FBB, DL);
1267      FuncInfo.MBB->addSuccessor(TBB);
1268      return true;
1269    }
1270  } else if (const ConstantInt *CI =
1271             dyn_cast<ConstantInt>(BI->getCondition())) {
1272    uint64_t Imm = CI->getZExtValue();
1273    MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1274    FastEmitBranch(Target, DL);
1275    return true;
1276  }
1277
1278  unsigned CmpReg = getRegForValue(BI->getCondition());
1279  if (CmpReg == 0) return false;
1280
1281  // We've been divorced from our compare!  Our block was split, and
1282  // now our compare lives in a predecessor block.  We musn't
1283  // re-compare here, as the children of the compare aren't guaranteed
1284  // live across the block boundary (we *could* check for this).
1285  // Regardless, the compare has been done in the predecessor block,
1286  // and it left a value for us in a virtual register.  Ergo, we test
1287  // the one-bit value left in the virtual register.
1288  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1289  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1290                  .addReg(CmpReg).addImm(1));
1291
1292  unsigned CCMode = ARMCC::NE;
1293  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1294    std::swap(TBB, FBB);
1295    CCMode = ARMCC::EQ;
1296  }
1297
1298  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1299  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1300                  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1301  FastEmitBranch(FBB, DL);
1302  FuncInfo.MBB->addSuccessor(TBB);
1303  return true;
1304}
1305
1306bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1307                             bool isZExt) {
1308  Type *Ty = Src1Value->getType();
1309  EVT SrcVT = TLI.getValueType(Ty, true);
1310  if (!SrcVT.isSimple()) return false;
1311
1312  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1313  if (isFloat && !Subtarget->hasVFP2())
1314    return false;
1315
1316  // Check to see if the 2nd operand is a constant that we can encode directly
1317  // in the compare.
1318  int Imm = 0;
1319  bool UseImm = false;
1320  bool isNegativeImm = false;
1321  // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1322  // Thus, Src1Value may be a ConstantInt, but we're missing it.
1323  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1324    if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1325        SrcVT == MVT::i1) {
1326      const APInt &CIVal = ConstInt->getValue();
1327      Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1328      if (Imm < 0) {
1329        isNegativeImm = true;
1330        Imm = -Imm;
1331      }
1332      UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1333        (ARM_AM::getSOImmVal(Imm) != -1);
1334    }
1335  } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1336    if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1337      if (ConstFP->isZero() && !ConstFP->isNegative())
1338        UseImm = true;
1339  }
1340
1341  unsigned CmpOpc;
1342  bool isICmp = true;
1343  bool needsExt = false;
1344  switch (SrcVT.getSimpleVT().SimpleTy) {
1345    default: return false;
1346    // TODO: Verify compares.
1347    case MVT::f32:
1348      isICmp = false;
1349      CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1350      break;
1351    case MVT::f64:
1352      isICmp = false;
1353      CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1354      break;
1355    case MVT::i1:
1356    case MVT::i8:
1357    case MVT::i16:
1358      needsExt = true;
1359    // Intentional fall-through.
1360    case MVT::i32:
1361      if (isThumb2) {
1362        if (!UseImm)
1363          CmpOpc = ARM::t2CMPrr;
1364        else
1365          CmpOpc = isNegativeImm ? ARM::t2CMNzri : ARM::t2CMPri;
1366      } else {
1367        if (!UseImm)
1368          CmpOpc = ARM::CMPrr;
1369        else
1370          CmpOpc = isNegativeImm ? ARM::CMNzri : ARM::CMPri;
1371      }
1372      break;
1373  }
1374
1375  unsigned SrcReg1 = getRegForValue(Src1Value);
1376  if (SrcReg1 == 0) return false;
1377
1378  unsigned SrcReg2 = 0;
1379  if (!UseImm) {
1380    SrcReg2 = getRegForValue(Src2Value);
1381    if (SrcReg2 == 0) return false;
1382  }
1383
1384  // We have i1, i8, or i16, we need to either zero extend or sign extend.
1385  if (needsExt) {
1386    unsigned ResultReg;
1387    ResultReg = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1388    if (ResultReg == 0) return false;
1389    SrcReg1 = ResultReg;
1390    if (!UseImm) {
1391      ResultReg = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1392      if (ResultReg == 0) return false;
1393      SrcReg2 = ResultReg;
1394    }
1395  }
1396
1397  if (!UseImm) {
1398    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1399                            TII.get(CmpOpc))
1400                    .addReg(SrcReg1).addReg(SrcReg2));
1401  } else {
1402    MachineInstrBuilder MIB;
1403    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1404      .addReg(SrcReg1);
1405
1406    // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1407    if (isICmp)
1408      MIB.addImm(Imm);
1409    AddOptionalDefs(MIB);
1410  }
1411
1412  // For floating point we need to move the result to a comparison register
1413  // that we can then use for branches.
1414  if (Ty->isFloatTy() || Ty->isDoubleTy())
1415    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1416                            TII.get(ARM::FMSTAT)));
1417  return true;
1418}
1419
1420bool ARMFastISel::SelectCmp(const Instruction *I) {
1421  const CmpInst *CI = cast<CmpInst>(I);
1422  Type *Ty = CI->getOperand(0)->getType();
1423
1424  // Get the compare predicate.
1425  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1426
1427  // We may not handle every CC for now.
1428  if (ARMPred == ARMCC::AL) return false;
1429
1430  // Emit the compare.
1431  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1432    return false;
1433
1434  // Now set a register based on the comparison. Explicitly set the predicates
1435  // here.
1436  unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1437  TargetRegisterClass *RC = isThumb2 ? ARM::rGPRRegisterClass
1438                                    : ARM::GPRRegisterClass;
1439  unsigned DestReg = createResultReg(RC);
1440  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1441  unsigned ZeroReg = TargetMaterializeConstant(Zero);
1442  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1443  unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
1444  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1445          .addReg(ZeroReg).addImm(1)
1446          .addImm(ARMPred).addReg(CondReg);
1447
1448  UpdateValueMap(I, DestReg);
1449  return true;
1450}
1451
1452bool ARMFastISel::SelectFPExt(const Instruction *I) {
1453  // Make sure we have VFP and that we're extending float to double.
1454  if (!Subtarget->hasVFP2()) return false;
1455
1456  Value *V = I->getOperand(0);
1457  if (!I->getType()->isDoubleTy() ||
1458      !V->getType()->isFloatTy()) return false;
1459
1460  unsigned Op = getRegForValue(V);
1461  if (Op == 0) return false;
1462
1463  unsigned Result = createResultReg(ARM::DPRRegisterClass);
1464  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1465                          TII.get(ARM::VCVTDS), Result)
1466                  .addReg(Op));
1467  UpdateValueMap(I, Result);
1468  return true;
1469}
1470
1471bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1472  // Make sure we have VFP and that we're truncating double to float.
1473  if (!Subtarget->hasVFP2()) return false;
1474
1475  Value *V = I->getOperand(0);
1476  if (!(I->getType()->isFloatTy() &&
1477        V->getType()->isDoubleTy())) return false;
1478
1479  unsigned Op = getRegForValue(V);
1480  if (Op == 0) return false;
1481
1482  unsigned Result = createResultReg(ARM::SPRRegisterClass);
1483  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1484                          TII.get(ARM::VCVTSD), Result)
1485                  .addReg(Op));
1486  UpdateValueMap(I, Result);
1487  return true;
1488}
1489
1490bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1491  // Make sure we have VFP.
1492  if (!Subtarget->hasVFP2()) return false;
1493
1494  MVT DstVT;
1495  Type *Ty = I->getType();
1496  if (!isTypeLegal(Ty, DstVT))
1497    return false;
1498
1499  Value *Src = I->getOperand(0);
1500  EVT SrcVT = TLI.getValueType(Src->getType(), true);
1501  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1502    return false;
1503
1504  unsigned SrcReg = getRegForValue(Src);
1505  if (SrcReg == 0) return false;
1506
1507  // Handle sign-extension.
1508  if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1509    EVT DestVT = MVT::i32;
1510    unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, /*isZExt*/ false);
1511    if (ResultReg == 0) return false;
1512    SrcReg = ResultReg;
1513  }
1514
1515  // The conversion routine works on fp-reg to fp-reg and the operand above
1516  // was an integer, move it to the fp registers if possible.
1517  unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1518  if (FP == 0) return false;
1519
1520  unsigned Opc;
1521  if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1522  else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1523  else return false;
1524
1525  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1526  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1527                          ResultReg)
1528                  .addReg(FP));
1529  UpdateValueMap(I, ResultReg);
1530  return true;
1531}
1532
1533bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1534  // Make sure we have VFP.
1535  if (!Subtarget->hasVFP2()) return false;
1536
1537  MVT DstVT;
1538  Type *RetTy = I->getType();
1539  if (!isTypeLegal(RetTy, DstVT))
1540    return false;
1541
1542  unsigned Op = getRegForValue(I->getOperand(0));
1543  if (Op == 0) return false;
1544
1545  unsigned Opc;
1546  Type *OpTy = I->getOperand(0)->getType();
1547  if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1548  else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1549  else return false;
1550
1551  // f64->s32 or f32->s32 both need an intermediate f32 reg.
1552  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1553  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1554                          ResultReg)
1555                  .addReg(Op));
1556
1557  // This result needs to be in an integer register, but the conversion only
1558  // takes place in fp-regs.
1559  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1560  if (IntReg == 0) return false;
1561
1562  UpdateValueMap(I, IntReg);
1563  return true;
1564}
1565
1566bool ARMFastISel::SelectSelect(const Instruction *I) {
1567  MVT VT;
1568  if (!isTypeLegal(I->getType(), VT))
1569    return false;
1570
1571  // Things need to be register sized for register moves.
1572  if (VT != MVT::i32) return false;
1573  const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1574
1575  unsigned CondReg = getRegForValue(I->getOperand(0));
1576  if (CondReg == 0) return false;
1577  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1578  if (Op1Reg == 0) return false;
1579
1580  // Check to see if we can use an immediate in the conditional move.
1581  int Imm = 0;
1582  bool UseImm = false;
1583  bool isNegativeImm = false;
1584  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1585    assert (VT == MVT::i32 && "Expecting an i32.");
1586    Imm = (int)ConstInt->getValue().getZExtValue();
1587    if (Imm < 0) {
1588      isNegativeImm = true;
1589      Imm = ~Imm;
1590    }
1591    UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1592      (ARM_AM::getSOImmVal(Imm) != -1);
1593  }
1594
1595  unsigned Op2Reg = 0;
1596  if (!UseImm) {
1597    Op2Reg = getRegForValue(I->getOperand(2));
1598    if (Op2Reg == 0) return false;
1599  }
1600
1601  unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1602  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1603                  .addReg(CondReg).addImm(0));
1604
1605  unsigned MovCCOpc;
1606  if (!UseImm) {
1607    MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1608  } else {
1609    if (!isNegativeImm) {
1610      MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1611    } else {
1612      MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1613    }
1614  }
1615  unsigned ResultReg = createResultReg(RC);
1616  if (!UseImm)
1617    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1618    .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1619  else
1620    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1621    .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1622  UpdateValueMap(I, ResultReg);
1623  return true;
1624}
1625
1626bool ARMFastISel::SelectSDiv(const Instruction *I) {
1627  MVT VT;
1628  Type *Ty = I->getType();
1629  if (!isTypeLegal(Ty, VT))
1630    return false;
1631
1632  // If we have integer div support we should have selected this automagically.
1633  // In case we have a real miss go ahead and return false and we'll pick
1634  // it up later.
1635  if (Subtarget->hasDivide()) return false;
1636
1637  // Otherwise emit a libcall.
1638  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1639  if (VT == MVT::i8)
1640    LC = RTLIB::SDIV_I8;
1641  else if (VT == MVT::i16)
1642    LC = RTLIB::SDIV_I16;
1643  else if (VT == MVT::i32)
1644    LC = RTLIB::SDIV_I32;
1645  else if (VT == MVT::i64)
1646    LC = RTLIB::SDIV_I64;
1647  else if (VT == MVT::i128)
1648    LC = RTLIB::SDIV_I128;
1649  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1650
1651  return ARMEmitLibcall(I, LC);
1652}
1653
1654bool ARMFastISel::SelectSRem(const Instruction *I) {
1655  MVT VT;
1656  Type *Ty = I->getType();
1657  if (!isTypeLegal(Ty, VT))
1658    return false;
1659
1660  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1661  if (VT == MVT::i8)
1662    LC = RTLIB::SREM_I8;
1663  else if (VT == MVT::i16)
1664    LC = RTLIB::SREM_I16;
1665  else if (VT == MVT::i32)
1666    LC = RTLIB::SREM_I32;
1667  else if (VT == MVT::i64)
1668    LC = RTLIB::SREM_I64;
1669  else if (VT == MVT::i128)
1670    LC = RTLIB::SREM_I128;
1671  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1672
1673  return ARMEmitLibcall(I, LC);
1674}
1675
1676bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1677  EVT VT  = TLI.getValueType(I->getType(), true);
1678
1679  // We can get here in the case when we want to use NEON for our fp
1680  // operations, but can't figure out how to. Just use the vfp instructions
1681  // if we have them.
1682  // FIXME: It'd be nice to use NEON instructions.
1683  Type *Ty = I->getType();
1684  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1685  if (isFloat && !Subtarget->hasVFP2())
1686    return false;
1687
1688  unsigned Opc;
1689  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1690  switch (ISDOpcode) {
1691    default: return false;
1692    case ISD::FADD:
1693      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1694      break;
1695    case ISD::FSUB:
1696      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1697      break;
1698    case ISD::FMUL:
1699      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1700      break;
1701  }
1702  unsigned Op1 = getRegForValue(I->getOperand(0));
1703  if (Op1 == 0) return false;
1704
1705  unsigned Op2 = getRegForValue(I->getOperand(1));
1706  if (Op2 == 0) return false;
1707
1708  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1709  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1710                          TII.get(Opc), ResultReg)
1711                  .addReg(Op1).addReg(Op2));
1712  UpdateValueMap(I, ResultReg);
1713  return true;
1714}
1715
1716// Call Handling Code
1717
1718// This is largely taken directly from CCAssignFnForNode - we don't support
1719// varargs in FastISel so that part has been removed.
1720// TODO: We may not support all of this.
1721CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1722  switch (CC) {
1723  default:
1724    llvm_unreachable("Unsupported calling convention");
1725  case CallingConv::Fast:
1726    // Ignore fastcc. Silence compiler warnings.
1727    (void)RetFastCC_ARM_APCS;
1728    (void)FastCC_ARM_APCS;
1729    // Fallthrough
1730  case CallingConv::C:
1731    // Use target triple & subtarget features to do actual dispatch.
1732    if (Subtarget->isAAPCS_ABI()) {
1733      if (Subtarget->hasVFP2() &&
1734          TM.Options.FloatABIType == FloatABI::Hard)
1735        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1736      else
1737        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1738    } else
1739        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1740  case CallingConv::ARM_AAPCS_VFP:
1741    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1742  case CallingConv::ARM_AAPCS:
1743    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1744  case CallingConv::ARM_APCS:
1745    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1746  }
1747}
1748
1749bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1750                                  SmallVectorImpl<unsigned> &ArgRegs,
1751                                  SmallVectorImpl<MVT> &ArgVTs,
1752                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1753                                  SmallVectorImpl<unsigned> &RegArgs,
1754                                  CallingConv::ID CC,
1755                                  unsigned &NumBytes) {
1756  SmallVector<CCValAssign, 16> ArgLocs;
1757  CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1758  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1759
1760  // Get a count of how many bytes are to be pushed on the stack.
1761  NumBytes = CCInfo.getNextStackOffset();
1762
1763  // Issue CALLSEQ_START
1764  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1765  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1766                          TII.get(AdjStackDown))
1767                  .addImm(NumBytes));
1768
1769  // Process the args.
1770  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1771    CCValAssign &VA = ArgLocs[i];
1772    unsigned Arg = ArgRegs[VA.getValNo()];
1773    MVT ArgVT = ArgVTs[VA.getValNo()];
1774
1775    // We don't handle NEON/vector parameters yet.
1776    if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1777      return false;
1778
1779    // Handle arg promotion, etc.
1780    switch (VA.getLocInfo()) {
1781      case CCValAssign::Full: break;
1782      case CCValAssign::SExt: {
1783        MVT DestVT = VA.getLocVT();
1784        unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT,
1785                                           /*isZExt*/false);
1786        assert (ResultReg != 0 && "Failed to emit a sext");
1787        Arg = ResultReg;
1788        ArgVT = DestVT;
1789        break;
1790      }
1791      case CCValAssign::AExt:
1792        // Intentional fall-through.  Handle AExt and ZExt.
1793      case CCValAssign::ZExt: {
1794        MVT DestVT = VA.getLocVT();
1795        unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT,
1796                                           /*isZExt*/true);
1797        assert (ResultReg != 0 && "Failed to emit a sext");
1798        Arg = ResultReg;
1799        ArgVT = DestVT;
1800        break;
1801      }
1802      case CCValAssign::BCvt: {
1803        unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1804                                 /*TODO: Kill=*/false);
1805        assert(BC != 0 && "Failed to emit a bitcast!");
1806        Arg = BC;
1807        ArgVT = VA.getLocVT();
1808        break;
1809      }
1810      default: llvm_unreachable("Unknown arg promotion!");
1811    }
1812
1813    // Now copy/store arg to correct locations.
1814    if (VA.isRegLoc() && !VA.needsCustom()) {
1815      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1816              VA.getLocReg())
1817        .addReg(Arg);
1818      RegArgs.push_back(VA.getLocReg());
1819    } else if (VA.needsCustom()) {
1820      // TODO: We need custom lowering for vector (v2f64) args.
1821      if (VA.getLocVT() != MVT::f64) return false;
1822
1823      CCValAssign &NextVA = ArgLocs[++i];
1824
1825      // TODO: Only handle register args for now.
1826      if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1827
1828      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1829                              TII.get(ARM::VMOVRRD), VA.getLocReg())
1830                      .addReg(NextVA.getLocReg(), RegState::Define)
1831                      .addReg(Arg));
1832      RegArgs.push_back(VA.getLocReg());
1833      RegArgs.push_back(NextVA.getLocReg());
1834    } else {
1835      assert(VA.isMemLoc());
1836      // Need to store on the stack.
1837      Address Addr;
1838      Addr.BaseType = Address::RegBase;
1839      Addr.Base.Reg = ARM::SP;
1840      Addr.Offset = VA.getLocMemOffset();
1841
1842      if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1843    }
1844  }
1845  return true;
1846}
1847
1848bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1849                             const Instruction *I, CallingConv::ID CC,
1850                             unsigned &NumBytes) {
1851  // Issue CALLSEQ_END
1852  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1853  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1854                          TII.get(AdjStackUp))
1855                  .addImm(NumBytes).addImm(0));
1856
1857  // Now the return value.
1858  if (RetVT != MVT::isVoid) {
1859    SmallVector<CCValAssign, 16> RVLocs;
1860    CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1861    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1862
1863    // Copy all of the result registers out of their specified physreg.
1864    if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1865      // For this move we copy into two registers and then move into the
1866      // double fp reg we want.
1867      EVT DestVT = RVLocs[0].getValVT();
1868      TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1869      unsigned ResultReg = createResultReg(DstRC);
1870      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1871                              TII.get(ARM::VMOVDRR), ResultReg)
1872                      .addReg(RVLocs[0].getLocReg())
1873                      .addReg(RVLocs[1].getLocReg()));
1874
1875      UsedRegs.push_back(RVLocs[0].getLocReg());
1876      UsedRegs.push_back(RVLocs[1].getLocReg());
1877
1878      // Finally update the result.
1879      UpdateValueMap(I, ResultReg);
1880    } else {
1881      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1882      EVT CopyVT = RVLocs[0].getValVT();
1883
1884      // Special handling for extended integers.
1885      if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1886        CopyVT = MVT::i32;
1887
1888      TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1889
1890      unsigned ResultReg = createResultReg(DstRC);
1891      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1892              ResultReg).addReg(RVLocs[0].getLocReg());
1893      UsedRegs.push_back(RVLocs[0].getLocReg());
1894
1895      // Finally update the result.
1896      UpdateValueMap(I, ResultReg);
1897    }
1898  }
1899
1900  return true;
1901}
1902
1903bool ARMFastISel::SelectRet(const Instruction *I) {
1904  const ReturnInst *Ret = cast<ReturnInst>(I);
1905  const Function &F = *I->getParent()->getParent();
1906
1907  if (!FuncInfo.CanLowerReturn)
1908    return false;
1909
1910  if (F.isVarArg())
1911    return false;
1912
1913  CallingConv::ID CC = F.getCallingConv();
1914  if (Ret->getNumOperands() > 0) {
1915    SmallVector<ISD::OutputArg, 4> Outs;
1916    GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1917                  Outs, TLI);
1918
1919    // Analyze operands of the call, assigning locations to each operand.
1920    SmallVector<CCValAssign, 16> ValLocs;
1921    CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
1922    CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1923
1924    const Value *RV = Ret->getOperand(0);
1925    unsigned Reg = getRegForValue(RV);
1926    if (Reg == 0)
1927      return false;
1928
1929    // Only handle a single return value for now.
1930    if (ValLocs.size() != 1)
1931      return false;
1932
1933    CCValAssign &VA = ValLocs[0];
1934
1935    // Don't bother handling odd stuff for now.
1936    if (VA.getLocInfo() != CCValAssign::Full)
1937      return false;
1938    // Only handle register returns for now.
1939    if (!VA.isRegLoc())
1940      return false;
1941
1942    unsigned SrcReg = Reg + VA.getValNo();
1943    EVT RVVT = TLI.getValueType(RV->getType());
1944    EVT DestVT = VA.getValVT();
1945    // Special handling for extended integers.
1946    if (RVVT != DestVT) {
1947      if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1948        return false;
1949
1950      if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1951        return false;
1952
1953      assert(DestVT == MVT::i32 && "ARM should always ext to i32");
1954
1955      bool isZExt = Outs[0].Flags.isZExt();
1956      unsigned ResultReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, isZExt);
1957      if (ResultReg == 0) return false;
1958      SrcReg = ResultReg;
1959    }
1960
1961    // Make the copy.
1962    unsigned DstReg = VA.getLocReg();
1963    const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1964    // Avoid a cross-class copy. This is very unlikely.
1965    if (!SrcRC->contains(DstReg))
1966      return false;
1967    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1968            DstReg).addReg(SrcReg);
1969
1970    // Mark the register as live out of the function.
1971    MRI.addLiveOut(VA.getLocReg());
1972  }
1973
1974  unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
1975  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1976                          TII.get(RetOpc)));
1977  return true;
1978}
1979
1980unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1981
1982  // Darwin needs the r9 versions of the opcodes.
1983  bool isDarwin = Subtarget->isTargetDarwin();
1984  if (isThumb2) {
1985    return isDarwin ? ARM::tBLr9 : ARM::tBL;
1986  } else  {
1987    return isDarwin ? ARM::BLr9 : ARM::BL;
1988  }
1989}
1990
1991// A quick function that will emit a call for a named libcall in F with the
1992// vector of passed arguments for the Instruction in I. We can assume that we
1993// can emit a call for any libcall we can produce. This is an abridged version
1994// of the full call infrastructure since we won't need to worry about things
1995// like computed function pointers or strange arguments at call sites.
1996// TODO: Try to unify this and the normal call bits for ARM, then try to unify
1997// with X86.
1998bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1999  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2000
2001  // Handle *simple* calls for now.
2002  Type *RetTy = I->getType();
2003  MVT RetVT;
2004  if (RetTy->isVoidTy())
2005    RetVT = MVT::isVoid;
2006  else if (!isTypeLegal(RetTy, RetVT))
2007    return false;
2008
2009  // TODO: For now if we have long calls specified we don't handle the call.
2010  if (EnableARMLongCalls) return false;
2011
2012  // Set up the argument vectors.
2013  SmallVector<Value*, 8> Args;
2014  SmallVector<unsigned, 8> ArgRegs;
2015  SmallVector<MVT, 8> ArgVTs;
2016  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2017  Args.reserve(I->getNumOperands());
2018  ArgRegs.reserve(I->getNumOperands());
2019  ArgVTs.reserve(I->getNumOperands());
2020  ArgFlags.reserve(I->getNumOperands());
2021  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2022    Value *Op = I->getOperand(i);
2023    unsigned Arg = getRegForValue(Op);
2024    if (Arg == 0) return false;
2025
2026    Type *ArgTy = Op->getType();
2027    MVT ArgVT;
2028    if (!isTypeLegal(ArgTy, ArgVT)) return false;
2029
2030    ISD::ArgFlagsTy Flags;
2031    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2032    Flags.setOrigAlign(OriginalAlignment);
2033
2034    Args.push_back(Op);
2035    ArgRegs.push_back(Arg);
2036    ArgVTs.push_back(ArgVT);
2037    ArgFlags.push_back(Flags);
2038  }
2039
2040  // Handle the arguments now that we've gotten them.
2041  SmallVector<unsigned, 4> RegArgs;
2042  unsigned NumBytes;
2043  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
2044    return false;
2045
2046  // Issue the call, BLr9 for darwin, BL otherwise.
2047  // TODO: Turn this into the table of arm call ops.
2048  MachineInstrBuilder MIB;
2049  unsigned CallOpc = ARMSelectCallOp(NULL);
2050  if(isThumb2)
2051    // Explicitly adding the predicate here.
2052    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2053                         TII.get(CallOpc)))
2054                         .addExternalSymbol(TLI.getLibcallName(Call));
2055  else
2056    // Explicitly adding the predicate here.
2057    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2058                         TII.get(CallOpc))
2059          .addExternalSymbol(TLI.getLibcallName(Call)));
2060
2061  // Add implicit physical register uses to the call.
2062  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2063    MIB.addReg(RegArgs[i]);
2064
2065  // Finish off the call including any return values.
2066  SmallVector<unsigned, 4> UsedRegs;
2067  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
2068
2069  // Set all unused physreg defs as dead.
2070  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2071
2072  return true;
2073}
2074
2075bool ARMFastISel::SelectCall(const Instruction *I,
2076                             const char *IntrMemName = 0) {
2077  const CallInst *CI = cast<CallInst>(I);
2078  const Value *Callee = CI->getCalledValue();
2079
2080  // Can't handle inline asm.
2081  if (isa<InlineAsm>(Callee)) return false;
2082
2083  // Only handle global variable Callees.
2084  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2085  if (!GV)
2086    return false;
2087
2088  // Check the calling convention.
2089  ImmutableCallSite CS(CI);
2090  CallingConv::ID CC = CS.getCallingConv();
2091
2092  // TODO: Avoid some calling conventions?
2093
2094  // Let SDISel handle vararg functions.
2095  PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2096  FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2097  if (FTy->isVarArg())
2098    return false;
2099
2100  // Handle *simple* calls for now.
2101  Type *RetTy = I->getType();
2102  MVT RetVT;
2103  if (RetTy->isVoidTy())
2104    RetVT = MVT::isVoid;
2105  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2106           RetVT != MVT::i8  && RetVT != MVT::i1)
2107    return false;
2108
2109  // TODO: For now if we have long calls specified we don't handle the call.
2110  if (EnableARMLongCalls) return false;
2111
2112  // Set up the argument vectors.
2113  SmallVector<Value*, 8> Args;
2114  SmallVector<unsigned, 8> ArgRegs;
2115  SmallVector<MVT, 8> ArgVTs;
2116  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2117  Args.reserve(CS.arg_size());
2118  ArgRegs.reserve(CS.arg_size());
2119  ArgVTs.reserve(CS.arg_size());
2120  ArgFlags.reserve(CS.arg_size());
2121  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2122       i != e; ++i) {
2123    // If we're lowering a memory intrinsic instead of a regular call, skip the
2124    // last two arguments, which shouldn't be passed to the underlying function.
2125    if (IntrMemName && e-i <= 2)
2126      break;
2127
2128    ISD::ArgFlagsTy Flags;
2129    unsigned AttrInd = i - CS.arg_begin() + 1;
2130    if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2131      Flags.setSExt();
2132    if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2133      Flags.setZExt();
2134
2135    // FIXME: Only handle *easy* calls for now.
2136    if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2137        CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2138        CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2139        CS.paramHasAttr(AttrInd, Attribute::ByVal))
2140      return false;
2141
2142    Type *ArgTy = (*i)->getType();
2143    MVT ArgVT;
2144    if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2145        ArgVT != MVT::i1)
2146      return false;
2147
2148    unsigned Arg = getRegForValue(*i);
2149    if (Arg == 0)
2150      return false;
2151
2152    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2153    Flags.setOrigAlign(OriginalAlignment);
2154
2155    Args.push_back(*i);
2156    ArgRegs.push_back(Arg);
2157    ArgVTs.push_back(ArgVT);
2158    ArgFlags.push_back(Flags);
2159  }
2160
2161  // Handle the arguments now that we've gotten them.
2162  SmallVector<unsigned, 4> RegArgs;
2163  unsigned NumBytes;
2164  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
2165    return false;
2166
2167  // Issue the call, BLr9 for darwin, BL otherwise.
2168  // TODO: Turn this into the table of arm call ops.
2169  MachineInstrBuilder MIB;
2170  unsigned CallOpc = ARMSelectCallOp(GV);
2171  // Explicitly adding the predicate here.
2172  if(isThumb2) {
2173    // Explicitly adding the predicate here.
2174    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2175                                 TII.get(CallOpc)));
2176    if (!IntrMemName)
2177      MIB.addGlobalAddress(GV, 0, 0);
2178    else
2179      MIB.addExternalSymbol(IntrMemName, 0);
2180  } else {
2181    if (!IntrMemName)
2182      // Explicitly adding the predicate here.
2183      MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2184                                   TII.get(CallOpc))
2185            .addGlobalAddress(GV, 0, 0));
2186    else
2187      MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2188                                   TII.get(CallOpc))
2189            .addExternalSymbol(IntrMemName, 0));
2190  }
2191
2192  // Add implicit physical register uses to the call.
2193  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2194    MIB.addReg(RegArgs[i]);
2195
2196  // Finish off the call including any return values.
2197  SmallVector<unsigned, 4> UsedRegs;
2198  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
2199
2200  // Set all unused physreg defs as dead.
2201  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2202
2203  return true;
2204}
2205
2206bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2207  return Len <= 16;
2208}
2209
2210bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len) {
2211  // Make sure we don't bloat code by inlining very large memcpy's.
2212  if (!ARMIsMemCpySmall(Len))
2213    return false;
2214
2215  // We don't care about alignment here since we just emit integer accesses.
2216  while (Len) {
2217    MVT VT;
2218    if (Len >= 4)
2219      VT = MVT::i32;
2220    else if (Len >= 2)
2221      VT = MVT::i16;
2222    else {
2223      assert(Len == 1);
2224      VT = MVT::i8;
2225    }
2226
2227    bool RV;
2228    unsigned ResultReg;
2229    RV = ARMEmitLoad(VT, ResultReg, Src);
2230    assert (RV = true && "Should be able to handle this load.");
2231    RV = ARMEmitStore(VT, ResultReg, Dest);
2232    assert (RV = true && "Should be able to handle this store.");
2233
2234    unsigned Size = VT.getSizeInBits()/8;
2235    Len -= Size;
2236    Dest.Offset += Size;
2237    Src.Offset += Size;
2238  }
2239
2240  return true;
2241}
2242
2243bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2244  // FIXME: Handle more intrinsics.
2245  switch (I.getIntrinsicID()) {
2246  default: return false;
2247  case Intrinsic::memcpy:
2248  case Intrinsic::memmove: {
2249    const MemTransferInst &MTI = cast<MemTransferInst>(I);
2250    // Don't handle volatile.
2251    if (MTI.isVolatile())
2252      return false;
2253
2254    // Disable inlining for memmove before calls to ComputeAddress.  Otherwise,
2255    // we would emit dead code because we don't currently handle memmoves.
2256    bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2257    if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2258      // Small memcpy's are common enough that we want to do them without a call
2259      // if possible.
2260      uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2261      if (ARMIsMemCpySmall(Len)) {
2262        Address Dest, Src;
2263        if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2264            !ARMComputeAddress(MTI.getRawSource(), Src))
2265          return false;
2266        if (ARMTryEmitSmallMemCpy(Dest, Src, Len))
2267          return true;
2268      }
2269    }
2270
2271    if (!MTI.getLength()->getType()->isIntegerTy(32))
2272      return false;
2273
2274    if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2275      return false;
2276
2277    const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2278    return SelectCall(&I, IntrMemName);
2279  }
2280  case Intrinsic::memset: {
2281    const MemSetInst &MSI = cast<MemSetInst>(I);
2282    // Don't handle volatile.
2283    if (MSI.isVolatile())
2284      return false;
2285
2286    if (!MSI.getLength()->getType()->isIntegerTy(32))
2287      return false;
2288
2289    if (MSI.getDestAddressSpace() > 255)
2290      return false;
2291
2292    return SelectCall(&I, "memset");
2293  }
2294  }
2295  return false;
2296}
2297
2298bool ARMFastISel::SelectTrunc(const Instruction *I) {
2299  // The high bits for a type smaller than the register size are assumed to be
2300  // undefined.
2301  Value *Op = I->getOperand(0);
2302
2303  EVT SrcVT, DestVT;
2304  SrcVT = TLI.getValueType(Op->getType(), true);
2305  DestVT = TLI.getValueType(I->getType(), true);
2306
2307  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2308    return false;
2309  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2310    return false;
2311
2312  unsigned SrcReg = getRegForValue(Op);
2313  if (!SrcReg) return false;
2314
2315  // Because the high bits are undefined, a truncate doesn't generate
2316  // any code.
2317  UpdateValueMap(I, SrcReg);
2318  return true;
2319}
2320
2321unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
2322                                    bool isZExt) {
2323  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2324    return 0;
2325
2326  unsigned Opc;
2327  bool isBoolZext = false;
2328  if (!SrcVT.isSimple()) return 0;
2329  switch (SrcVT.getSimpleVT().SimpleTy) {
2330  default: return 0;
2331  case MVT::i16:
2332    if (!Subtarget->hasV6Ops()) return 0;
2333    if (isZExt)
2334      Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
2335    else
2336      Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
2337    break;
2338  case MVT::i8:
2339    if (!Subtarget->hasV6Ops()) return 0;
2340    if (isZExt)
2341      Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
2342    else
2343      Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
2344    break;
2345  case MVT::i1:
2346    if (isZExt) {
2347      Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
2348      isBoolZext = true;
2349      break;
2350    }
2351    return 0;
2352  }
2353
2354  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2355  MachineInstrBuilder MIB;
2356  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
2357        .addReg(SrcReg);
2358  if (isBoolZext)
2359    MIB.addImm(1);
2360  else
2361    MIB.addImm(0);
2362  AddOptionalDefs(MIB);
2363  return ResultReg;
2364}
2365
2366bool ARMFastISel::SelectIntExt(const Instruction *I) {
2367  // On ARM, in general, integer casts don't involve legal types; this code
2368  // handles promotable integers.
2369  Type *DestTy = I->getType();
2370  Value *Src = I->getOperand(0);
2371  Type *SrcTy = Src->getType();
2372
2373  EVT SrcVT, DestVT;
2374  SrcVT = TLI.getValueType(SrcTy, true);
2375  DestVT = TLI.getValueType(DestTy, true);
2376
2377  bool isZExt = isa<ZExtInst>(I);
2378  unsigned SrcReg = getRegForValue(Src);
2379  if (!SrcReg) return false;
2380
2381  unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2382  if (ResultReg == 0) return false;
2383  UpdateValueMap(I, ResultReg);
2384  return true;
2385}
2386
2387// TODO: SoftFP support.
2388bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2389
2390  switch (I->getOpcode()) {
2391    case Instruction::Load:
2392      return SelectLoad(I);
2393    case Instruction::Store:
2394      return SelectStore(I);
2395    case Instruction::Br:
2396      return SelectBranch(I);
2397    case Instruction::ICmp:
2398    case Instruction::FCmp:
2399      return SelectCmp(I);
2400    case Instruction::FPExt:
2401      return SelectFPExt(I);
2402    case Instruction::FPTrunc:
2403      return SelectFPTrunc(I);
2404    case Instruction::SIToFP:
2405      return SelectSIToFP(I);
2406    case Instruction::FPToSI:
2407      return SelectFPToSI(I);
2408    case Instruction::FAdd:
2409      return SelectBinaryOp(I, ISD::FADD);
2410    case Instruction::FSub:
2411      return SelectBinaryOp(I, ISD::FSUB);
2412    case Instruction::FMul:
2413      return SelectBinaryOp(I, ISD::FMUL);
2414    case Instruction::SDiv:
2415      return SelectSDiv(I);
2416    case Instruction::SRem:
2417      return SelectSRem(I);
2418    case Instruction::Call:
2419      if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2420        return SelectIntrinsicCall(*II);
2421      return SelectCall(I);
2422    case Instruction::Select:
2423      return SelectSelect(I);
2424    case Instruction::Ret:
2425      return SelectRet(I);
2426    case Instruction::Trunc:
2427      return SelectTrunc(I);
2428    case Instruction::ZExt:
2429    case Instruction::SExt:
2430      return SelectIntExt(I);
2431    default: break;
2432  }
2433  return false;
2434}
2435
2436/// TryToFoldLoad - The specified machine instr operand is a vreg, and that
2437/// vreg is being provided by the specified load instruction.  If possible,
2438/// try to fold the load as an operand to the instruction, returning true if
2439/// successful.
2440bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
2441                                const LoadInst *LI) {
2442  // Verify we have a legal type before going any further.
2443  MVT VT;
2444  if (!isLoadTypeLegal(LI->getType(), VT))
2445    return false;
2446
2447  // Combine load followed by zero- or sign-extend.
2448  // ldrb r1, [r0]       ldrb r1, [r0]
2449  // uxtb r2, r1     =>
2450  // mov  r3, r2         mov  r3, r1
2451  bool isZExt = true;
2452  switch(MI->getOpcode()) {
2453    default: return false;
2454    case ARM::SXTH:
2455    case ARM::t2SXTH:
2456      isZExt = false;
2457    case ARM::UXTH:
2458    case ARM::t2UXTH:
2459      if (VT != MVT::i16)
2460        return false;
2461    break;
2462    case ARM::SXTB:
2463    case ARM::t2SXTB:
2464      isZExt = false;
2465    case ARM::UXTB:
2466    case ARM::t2UXTB:
2467      if (VT != MVT::i8)
2468        return false;
2469    break;
2470  }
2471  // See if we can handle this address.
2472  Address Addr;
2473  if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2474
2475  unsigned ResultReg = MI->getOperand(0).getReg();
2476  if (!ARMEmitLoad(VT, ResultReg, Addr, isZExt, false))
2477    return false;
2478  MI->eraseFromParent();
2479  return true;
2480}
2481
2482namespace llvm {
2483  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2484    // Completely untested on non-darwin.
2485    const TargetMachine &TM = funcInfo.MF->getTarget();
2486
2487    // Darwin and thumb1 only for now.
2488    const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2489    if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2490        !DisableARMFastISel)
2491      return new ARMFastISel(funcInfo);
2492    return 0;
2493  }
2494}
2495