ARMFastISel.cpp revision ed42c5f778dd0128429e4feffe2c028b2352b534 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMRegisterInfo.h"
20#include "ARMTargetMachine.h"
21#include "ARMSubtarget.h"
22#include "ARMConstantPoolValue.h"
23#include "MCTargetDesc/ARMAddressingModes.h"
24#include "llvm/CallingConv.h"
25#include "llvm/DerivedTypes.h"
26#include "llvm/GlobalVariable.h"
27#include "llvm/Instructions.h"
28#include "llvm/IntrinsicInst.h"
29#include "llvm/Module.h"
30#include "llvm/Operator.h"
31#include "llvm/CodeGen/Analysis.h"
32#include "llvm/CodeGen/FastISel.h"
33#include "llvm/CodeGen/FunctionLoweringInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineModuleInfo.h"
36#include "llvm/CodeGen/MachineConstantPool.h"
37#include "llvm/CodeGen/MachineFrameInfo.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/MachineRegisterInfo.h"
40#include "llvm/Support/CallSite.h"
41#include "llvm/Support/CommandLine.h"
42#include "llvm/Support/ErrorHandling.h"
43#include "llvm/Support/GetElementPtrTypeIterator.h"
44#include "llvm/Target/TargetData.h"
45#include "llvm/Target/TargetInstrInfo.h"
46#include "llvm/Target/TargetLowering.h"
47#include "llvm/Target/TargetMachine.h"
48#include "llvm/Target/TargetOptions.h"
49using namespace llvm;
50
51static cl::opt<bool>
52DisableARMFastISel("disable-arm-fast-isel",
53                    cl::desc("Turn off experimental ARM fast-isel support"),
54                    cl::init(false), cl::Hidden);
55
56extern cl::opt<bool> EnableARMLongCalls;
57
58namespace {
59
60  // All possible address modes, plus some.
61  typedef struct Address {
62    enum {
63      RegBase,
64      FrameIndexBase
65    } BaseType;
66
67    union {
68      unsigned Reg;
69      int FI;
70    } Base;
71
72    int Offset;
73
74    // Innocuous defaults for our address.
75    Address()
76     : BaseType(RegBase), Offset(0) {
77       Base.Reg = 0;
78     }
79  } Address;
80
81class ARMFastISel : public FastISel {
82
83  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
84  /// make the right decision when generating code for different targets.
85  const ARMSubtarget *Subtarget;
86  const TargetMachine &TM;
87  const TargetInstrInfo &TII;
88  const TargetLowering &TLI;
89  ARMFunctionInfo *AFI;
90
91  // Convenience variables to avoid some queries.
92  bool isThumb2;
93  LLVMContext *Context;
94
95  public:
96    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
97    : FastISel(funcInfo),
98      TM(funcInfo.MF->getTarget()),
99      TII(*TM.getInstrInfo()),
100      TLI(*TM.getTargetLowering()) {
101      Subtarget = &TM.getSubtarget<ARMSubtarget>();
102      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
103      isThumb2 = AFI->isThumbFunction();
104      Context = &funcInfo.Fn->getContext();
105    }
106
107    // Code from FastISel.cpp.
108    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
109                                   const TargetRegisterClass *RC);
110    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
111                                    const TargetRegisterClass *RC,
112                                    unsigned Op0, bool Op0IsKill);
113    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
114                                     const TargetRegisterClass *RC,
115                                     unsigned Op0, bool Op0IsKill,
116                                     unsigned Op1, bool Op1IsKill);
117    virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
118                                      const TargetRegisterClass *RC,
119                                      unsigned Op0, bool Op0IsKill,
120                                      unsigned Op1, bool Op1IsKill,
121                                      unsigned Op2, bool Op2IsKill);
122    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
123                                     const TargetRegisterClass *RC,
124                                     unsigned Op0, bool Op0IsKill,
125                                     uint64_t Imm);
126    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
127                                     const TargetRegisterClass *RC,
128                                     unsigned Op0, bool Op0IsKill,
129                                     const ConstantFP *FPImm);
130    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
131                                      const TargetRegisterClass *RC,
132                                      unsigned Op0, bool Op0IsKill,
133                                      unsigned Op1, bool Op1IsKill,
134                                      uint64_t Imm);
135    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
136                                    const TargetRegisterClass *RC,
137                                    uint64_t Imm);
138    virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
139                                     const TargetRegisterClass *RC,
140                                     uint64_t Imm1, uint64_t Imm2);
141
142    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
143                                                unsigned Op0, bool Op0IsKill,
144                                                uint32_t Idx);
145
146    // Backend specific FastISel code.
147    virtual bool TargetSelectInstruction(const Instruction *I);
148    virtual unsigned TargetMaterializeConstant(const Constant *C);
149    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
150    virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
151                               const LoadInst *LI);
152
153  #include "ARMGenFastISel.inc"
154
155    // Instruction selection routines.
156  private:
157    bool SelectLoad(const Instruction *I);
158    bool SelectStore(const Instruction *I);
159    bool SelectBranch(const Instruction *I);
160    bool SelectCmp(const Instruction *I);
161    bool SelectFPExt(const Instruction *I);
162    bool SelectFPTrunc(const Instruction *I);
163    bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
164    bool SelectSIToFP(const Instruction *I);
165    bool SelectFPToSI(const Instruction *I);
166    bool SelectSDiv(const Instruction *I);
167    bool SelectSRem(const Instruction *I);
168    bool SelectCall(const Instruction *I, const char *IntrMemName);
169    bool SelectIntrinsicCall(const IntrinsicInst &I);
170    bool SelectSelect(const Instruction *I);
171    bool SelectRet(const Instruction *I);
172    bool SelectTrunc(const Instruction *I);
173    bool SelectIntExt(const Instruction *I);
174
175    // Utility routines.
176  private:
177    bool isTypeLegal(Type *Ty, MVT &VT);
178    bool isLoadTypeLegal(Type *Ty, MVT &VT);
179    bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
180                    bool isZExt);
181    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, bool isZExt,
182                     bool allocReg);
183
184    bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
185                      unsigned Alignment = 0);
186    bool ARMComputeAddress(const Value *Obj, Address &Addr);
187    void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
188    bool ARMIsMemCpySmall(uint64_t Len);
189    bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len);
190    unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
191    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
192    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
193    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
194    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
195    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
196    unsigned ARMSelectCallOp(const GlobalValue *GV);
197
198    // Call handling routines.
199  private:
200    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
201    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
202                         SmallVectorImpl<unsigned> &ArgRegs,
203                         SmallVectorImpl<MVT> &ArgVTs,
204                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
205                         SmallVectorImpl<unsigned> &RegArgs,
206                         CallingConv::ID CC,
207                         unsigned &NumBytes);
208    bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
209                    const Instruction *I, CallingConv::ID CC,
210                    unsigned &NumBytes);
211    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
212
213    // OptionalDef handling routines.
214  private:
215    bool isARMNEONPred(const MachineInstr *MI);
216    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
217    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
218    void AddLoadStoreOperands(EVT VT, Address &Addr,
219                              const MachineInstrBuilder &MIB,
220                              unsigned Flags, bool useAM3);
221};
222
223} // end anonymous namespace
224
225#include "ARMGenCallingConv.inc"
226
227// DefinesOptionalPredicate - This is different from DefinesPredicate in that
228// we don't care about implicit defs here, just places we'll need to add a
229// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
230bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
231  const MCInstrDesc &MCID = MI->getDesc();
232  if (!MCID.hasOptionalDef())
233    return false;
234
235  // Look to see if our OptionalDef is defining CPSR or CCR.
236  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
237    const MachineOperand &MO = MI->getOperand(i);
238    if (!MO.isReg() || !MO.isDef()) continue;
239    if (MO.getReg() == ARM::CPSR)
240      *CPSR = true;
241  }
242  return true;
243}
244
245bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
246  const MCInstrDesc &MCID = MI->getDesc();
247
248  // If we're a thumb2 or not NEON function we were handled via isPredicable.
249  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
250       AFI->isThumb2Function())
251    return false;
252
253  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
254    if (MCID.OpInfo[i].isPredicate())
255      return true;
256
257  return false;
258}
259
260// If the machine is predicable go ahead and add the predicate operands, if
261// it needs default CC operands add those.
262// TODO: If we want to support thumb1 then we'll need to deal with optional
263// CPSR defs that need to be added before the remaining operands. See s_cc_out
264// for descriptions why.
265const MachineInstrBuilder &
266ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
267  MachineInstr *MI = &*MIB;
268
269  // Do we use a predicate? or...
270  // Are we NEON in ARM mode and have a predicate operand? If so, I know
271  // we're not predicable but add it anyways.
272  if (TII.isPredicable(MI) || isARMNEONPred(MI))
273    AddDefaultPred(MIB);
274
275  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
276  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
277  bool CPSR = false;
278  if (DefinesOptionalPredicate(MI, &CPSR)) {
279    if (CPSR)
280      AddDefaultT1CC(MIB);
281    else
282      AddDefaultCC(MIB);
283  }
284  return MIB;
285}
286
287unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
288                                    const TargetRegisterClass* RC) {
289  unsigned ResultReg = createResultReg(RC);
290  const MCInstrDesc &II = TII.get(MachineInstOpcode);
291
292  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
293  return ResultReg;
294}
295
296unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
297                                     const TargetRegisterClass *RC,
298                                     unsigned Op0, bool Op0IsKill) {
299  unsigned ResultReg = createResultReg(RC);
300  const MCInstrDesc &II = TII.get(MachineInstOpcode);
301
302  if (II.getNumDefs() >= 1)
303    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
304                   .addReg(Op0, Op0IsKill * RegState::Kill));
305  else {
306    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
307                   .addReg(Op0, Op0IsKill * RegState::Kill));
308    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
309                   TII.get(TargetOpcode::COPY), ResultReg)
310                   .addReg(II.ImplicitDefs[0]));
311  }
312  return ResultReg;
313}
314
315unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
316                                      const TargetRegisterClass *RC,
317                                      unsigned Op0, bool Op0IsKill,
318                                      unsigned Op1, bool Op1IsKill) {
319  unsigned ResultReg = createResultReg(RC);
320  const MCInstrDesc &II = TII.get(MachineInstOpcode);
321
322  if (II.getNumDefs() >= 1)
323    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
324                   .addReg(Op0, Op0IsKill * RegState::Kill)
325                   .addReg(Op1, Op1IsKill * RegState::Kill));
326  else {
327    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
328                   .addReg(Op0, Op0IsKill * RegState::Kill)
329                   .addReg(Op1, Op1IsKill * RegState::Kill));
330    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
331                           TII.get(TargetOpcode::COPY), ResultReg)
332                   .addReg(II.ImplicitDefs[0]));
333  }
334  return ResultReg;
335}
336
337unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
338                                       const TargetRegisterClass *RC,
339                                       unsigned Op0, bool Op0IsKill,
340                                       unsigned Op1, bool Op1IsKill,
341                                       unsigned Op2, bool Op2IsKill) {
342  unsigned ResultReg = createResultReg(RC);
343  const MCInstrDesc &II = TII.get(MachineInstOpcode);
344
345  if (II.getNumDefs() >= 1)
346    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
347                   .addReg(Op0, Op0IsKill * RegState::Kill)
348                   .addReg(Op1, Op1IsKill * RegState::Kill)
349                   .addReg(Op2, Op2IsKill * RegState::Kill));
350  else {
351    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
352                   .addReg(Op0, Op0IsKill * RegState::Kill)
353                   .addReg(Op1, Op1IsKill * RegState::Kill)
354                   .addReg(Op2, Op2IsKill * RegState::Kill));
355    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
356                           TII.get(TargetOpcode::COPY), ResultReg)
357                   .addReg(II.ImplicitDefs[0]));
358  }
359  return ResultReg;
360}
361
362unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
363                                      const TargetRegisterClass *RC,
364                                      unsigned Op0, bool Op0IsKill,
365                                      uint64_t Imm) {
366  unsigned ResultReg = createResultReg(RC);
367  const MCInstrDesc &II = TII.get(MachineInstOpcode);
368
369  if (II.getNumDefs() >= 1)
370    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
371                   .addReg(Op0, Op0IsKill * RegState::Kill)
372                   .addImm(Imm));
373  else {
374    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
375                   .addReg(Op0, Op0IsKill * RegState::Kill)
376                   .addImm(Imm));
377    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
378                           TII.get(TargetOpcode::COPY), ResultReg)
379                   .addReg(II.ImplicitDefs[0]));
380  }
381  return ResultReg;
382}
383
384unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
385                                      const TargetRegisterClass *RC,
386                                      unsigned Op0, bool Op0IsKill,
387                                      const ConstantFP *FPImm) {
388  unsigned ResultReg = createResultReg(RC);
389  const MCInstrDesc &II = TII.get(MachineInstOpcode);
390
391  if (II.getNumDefs() >= 1)
392    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
393                   .addReg(Op0, Op0IsKill * RegState::Kill)
394                   .addFPImm(FPImm));
395  else {
396    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
397                   .addReg(Op0, Op0IsKill * RegState::Kill)
398                   .addFPImm(FPImm));
399    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
400                           TII.get(TargetOpcode::COPY), ResultReg)
401                   .addReg(II.ImplicitDefs[0]));
402  }
403  return ResultReg;
404}
405
406unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
407                                       const TargetRegisterClass *RC,
408                                       unsigned Op0, bool Op0IsKill,
409                                       unsigned Op1, bool Op1IsKill,
410                                       uint64_t Imm) {
411  unsigned ResultReg = createResultReg(RC);
412  const MCInstrDesc &II = TII.get(MachineInstOpcode);
413
414  if (II.getNumDefs() >= 1)
415    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
416                   .addReg(Op0, Op0IsKill * RegState::Kill)
417                   .addReg(Op1, Op1IsKill * RegState::Kill)
418                   .addImm(Imm));
419  else {
420    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
421                   .addReg(Op0, Op0IsKill * RegState::Kill)
422                   .addReg(Op1, Op1IsKill * RegState::Kill)
423                   .addImm(Imm));
424    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
425                           TII.get(TargetOpcode::COPY), ResultReg)
426                   .addReg(II.ImplicitDefs[0]));
427  }
428  return ResultReg;
429}
430
431unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
432                                     const TargetRegisterClass *RC,
433                                     uint64_t Imm) {
434  unsigned ResultReg = createResultReg(RC);
435  const MCInstrDesc &II = TII.get(MachineInstOpcode);
436
437  if (II.getNumDefs() >= 1)
438    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
439                   .addImm(Imm));
440  else {
441    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
442                   .addImm(Imm));
443    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
444                           TII.get(TargetOpcode::COPY), ResultReg)
445                   .addReg(II.ImplicitDefs[0]));
446  }
447  return ResultReg;
448}
449
450unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
451                                      const TargetRegisterClass *RC,
452                                      uint64_t Imm1, uint64_t Imm2) {
453  unsigned ResultReg = createResultReg(RC);
454  const MCInstrDesc &II = TII.get(MachineInstOpcode);
455
456  if (II.getNumDefs() >= 1)
457    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
458                    .addImm(Imm1).addImm(Imm2));
459  else {
460    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
461                    .addImm(Imm1).addImm(Imm2));
462    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
463                            TII.get(TargetOpcode::COPY),
464                            ResultReg)
465                    .addReg(II.ImplicitDefs[0]));
466  }
467  return ResultReg;
468}
469
470unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
471                                                 unsigned Op0, bool Op0IsKill,
472                                                 uint32_t Idx) {
473  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
474  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
475         "Cannot yet extract from physregs");
476  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
477                         DL, TII.get(TargetOpcode::COPY), ResultReg)
478                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
479  return ResultReg;
480}
481
482// TODO: Don't worry about 64-bit now, but when this is fixed remove the
483// checks from the various callers.
484unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
485  if (VT == MVT::f64) return 0;
486
487  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
488  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
489                          TII.get(ARM::VMOVRS), MoveReg)
490                  .addReg(SrcReg));
491  return MoveReg;
492}
493
494unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
495  if (VT == MVT::i64) return 0;
496
497  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
498  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
499                          TII.get(ARM::VMOVSR), MoveReg)
500                  .addReg(SrcReg));
501  return MoveReg;
502}
503
504// For double width floating point we need to materialize two constants
505// (the high and the low) into integer registers then use a move to get
506// the combined constant into an FP reg.
507unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
508  const APFloat Val = CFP->getValueAPF();
509  bool is64bit = VT == MVT::f64;
510
511  // This checks to see if we can use VFP3 instructions to materialize
512  // a constant, otherwise we have to go through the constant pool.
513  if (TLI.isFPImmLegal(Val, VT)) {
514    int Imm;
515    unsigned Opc;
516    if (is64bit) {
517      Imm = ARM_AM::getFP64Imm(Val);
518      Opc = ARM::FCONSTD;
519    } else {
520      Imm = ARM_AM::getFP32Imm(Val);
521      Opc = ARM::FCONSTS;
522    }
523    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
524    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
525                            DestReg)
526                    .addImm(Imm));
527    return DestReg;
528  }
529
530  // Require VFP2 for loading fp constants.
531  if (!Subtarget->hasVFP2()) return false;
532
533  // MachineConstantPool wants an explicit alignment.
534  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
535  if (Align == 0) {
536    // TODO: Figure out if this is correct.
537    Align = TD.getTypeAllocSize(CFP->getType());
538  }
539  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
540  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
541  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
542
543  // The extra reg is for addrmode5.
544  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
545                          DestReg)
546                  .addConstantPoolIndex(Idx)
547                  .addReg(0));
548  return DestReg;
549}
550
551unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
552
553  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
554    return false;
555
556  // If we can do this in a single instruction without a constant pool entry
557  // do so now.
558  const ConstantInt *CI = cast<ConstantInt>(C);
559  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
560    unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
561    unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
562    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
563                            TII.get(Opc), ImmReg)
564                    .addImm(CI->getZExtValue()));
565    return ImmReg;
566  }
567
568  // Use MVN to emit negative constants.
569  if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
570    unsigned Imm = (unsigned)~(CI->getSExtValue());
571    bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
572      (ARM_AM::getSOImmVal(Imm) != -1);
573    if (UseImm) {
574      unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
575      unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
576      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
577                              TII.get(Opc), ImmReg)
578                      .addImm(Imm));
579      return ImmReg;
580    }
581  }
582
583  // Load from constant pool.  For now 32-bit only.
584  if (VT != MVT::i32)
585    return false;
586
587  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
588
589  // MachineConstantPool wants an explicit alignment.
590  unsigned Align = TD.getPrefTypeAlignment(C->getType());
591  if (Align == 0) {
592    // TODO: Figure out if this is correct.
593    Align = TD.getTypeAllocSize(C->getType());
594  }
595  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
596
597  if (isThumb2)
598    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
599                            TII.get(ARM::t2LDRpci), DestReg)
600                    .addConstantPoolIndex(Idx));
601  else
602    // The extra immediate is for addrmode2.
603    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
604                            TII.get(ARM::LDRcp), DestReg)
605                    .addConstantPoolIndex(Idx)
606                    .addImm(0));
607
608  return DestReg;
609}
610
611unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
612  // For now 32-bit only.
613  if (VT != MVT::i32) return 0;
614
615  Reloc::Model RelocM = TM.getRelocationModel();
616
617  // TODO: Need more magic for ARM PIC.
618  if (!isThumb2 && (RelocM == Reloc::PIC_)) return 0;
619
620  // MachineConstantPool wants an explicit alignment.
621  unsigned Align = TD.getPrefTypeAlignment(GV->getType());
622  if (Align == 0) {
623    // TODO: Figure out if this is correct.
624    Align = TD.getTypeAllocSize(GV->getType());
625  }
626
627  // Grab index.
628  unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
629  unsigned Id = AFI->createPICLabelUId();
630  ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
631                                                              ARMCP::CPValue,
632                                                              PCAdj);
633  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
634
635  // Load value.
636  MachineInstrBuilder MIB;
637  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
638  if (isThumb2) {
639    unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
640    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
641          .addConstantPoolIndex(Idx);
642    if (RelocM == Reloc::PIC_)
643      MIB.addImm(Id);
644  } else {
645    // The extra immediate is for addrmode2.
646    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
647                  DestReg)
648          .addConstantPoolIndex(Idx)
649          .addImm(0);
650  }
651  AddOptionalDefs(MIB);
652
653  if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
654    unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
655    if (isThumb2)
656      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
657                    TII.get(ARM::t2LDRi12), NewDestReg)
658            .addReg(DestReg)
659            .addImm(0);
660    else
661      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
662                    NewDestReg)
663            .addReg(DestReg)
664            .addImm(0);
665    DestReg = NewDestReg;
666    AddOptionalDefs(MIB);
667  }
668
669  return DestReg;
670}
671
672unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
673  EVT VT = TLI.getValueType(C->getType(), true);
674
675  // Only handle simple types.
676  if (!VT.isSimple()) return 0;
677
678  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
679    return ARMMaterializeFP(CFP, VT);
680  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
681    return ARMMaterializeGV(GV, VT);
682  else if (isa<ConstantInt>(C))
683    return ARMMaterializeInt(C, VT);
684
685  return 0;
686}
687
688// TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
689
690unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
691  // Don't handle dynamic allocas.
692  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
693
694  MVT VT;
695  if (!isLoadTypeLegal(AI->getType(), VT)) return false;
696
697  DenseMap<const AllocaInst*, int>::iterator SI =
698    FuncInfo.StaticAllocaMap.find(AI);
699
700  // This will get lowered later into the correct offsets and registers
701  // via rewriteXFrameIndex.
702  if (SI != FuncInfo.StaticAllocaMap.end()) {
703    TargetRegisterClass* RC = TLI.getRegClassFor(VT);
704    unsigned ResultReg = createResultReg(RC);
705    unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
706    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
707                            TII.get(Opc), ResultReg)
708                            .addFrameIndex(SI->second)
709                            .addImm(0));
710    return ResultReg;
711  }
712
713  return 0;
714}
715
716bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
717  EVT evt = TLI.getValueType(Ty, true);
718
719  // Only handle simple types.
720  if (evt == MVT::Other || !evt.isSimple()) return false;
721  VT = evt.getSimpleVT();
722
723  // Handle all legal types, i.e. a register that will directly hold this
724  // value.
725  return TLI.isTypeLegal(VT);
726}
727
728bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
729  if (isTypeLegal(Ty, VT)) return true;
730
731  // If this is a type than can be sign or zero-extended to a basic operation
732  // go ahead and accept it now.
733  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
734    return true;
735
736  return false;
737}
738
739// Computes the address to get to an object.
740bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
741  // Some boilerplate from the X86 FastISel.
742  const User *U = NULL;
743  unsigned Opcode = Instruction::UserOp1;
744  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
745    // Don't walk into other basic blocks unless the object is an alloca from
746    // another block, otherwise it may not have a virtual register assigned.
747    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
748        FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
749      Opcode = I->getOpcode();
750      U = I;
751    }
752  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
753    Opcode = C->getOpcode();
754    U = C;
755  }
756
757  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
758    if (Ty->getAddressSpace() > 255)
759      // Fast instruction selection doesn't support the special
760      // address spaces.
761      return false;
762
763  switch (Opcode) {
764    default:
765    break;
766    case Instruction::BitCast: {
767      // Look through bitcasts.
768      return ARMComputeAddress(U->getOperand(0), Addr);
769    }
770    case Instruction::IntToPtr: {
771      // Look past no-op inttoptrs.
772      if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
773        return ARMComputeAddress(U->getOperand(0), Addr);
774      break;
775    }
776    case Instruction::PtrToInt: {
777      // Look past no-op ptrtoints.
778      if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
779        return ARMComputeAddress(U->getOperand(0), Addr);
780      break;
781    }
782    case Instruction::GetElementPtr: {
783      Address SavedAddr = Addr;
784      int TmpOffset = Addr.Offset;
785
786      // Iterate through the GEP folding the constants into offsets where
787      // we can.
788      gep_type_iterator GTI = gep_type_begin(U);
789      for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
790           i != e; ++i, ++GTI) {
791        const Value *Op = *i;
792        if (StructType *STy = dyn_cast<StructType>(*GTI)) {
793          const StructLayout *SL = TD.getStructLayout(STy);
794          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
795          TmpOffset += SL->getElementOffset(Idx);
796        } else {
797          uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
798          for (;;) {
799            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
800              // Constant-offset addressing.
801              TmpOffset += CI->getSExtValue() * S;
802              break;
803            }
804            if (isa<AddOperator>(Op) &&
805                (!isa<Instruction>(Op) ||
806                 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
807                 == FuncInfo.MBB) &&
808                isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
809              // An add (in the same block) with a constant operand. Fold the
810              // constant.
811              ConstantInt *CI =
812              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
813              TmpOffset += CI->getSExtValue() * S;
814              // Iterate on the other operand.
815              Op = cast<AddOperator>(Op)->getOperand(0);
816              continue;
817            }
818            // Unsupported
819            goto unsupported_gep;
820          }
821        }
822      }
823
824      // Try to grab the base operand now.
825      Addr.Offset = TmpOffset;
826      if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
827
828      // We failed, restore everything and try the other options.
829      Addr = SavedAddr;
830
831      unsupported_gep:
832      break;
833    }
834    case Instruction::Alloca: {
835      const AllocaInst *AI = cast<AllocaInst>(Obj);
836      DenseMap<const AllocaInst*, int>::iterator SI =
837        FuncInfo.StaticAllocaMap.find(AI);
838      if (SI != FuncInfo.StaticAllocaMap.end()) {
839        Addr.BaseType = Address::FrameIndexBase;
840        Addr.Base.FI = SI->second;
841        return true;
842      }
843      break;
844    }
845  }
846
847  // Materialize the global variable's address into a reg which can
848  // then be used later to load the variable.
849  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
850    unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
851    if (Tmp == 0) return false;
852
853    Addr.Base.Reg = Tmp;
854    return true;
855  }
856
857  // Try to get this in a register if nothing else has worked.
858  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
859  return Addr.Base.Reg != 0;
860}
861
862void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
863
864  assert(VT.isSimple() && "Non-simple types are invalid here!");
865
866  bool needsLowering = false;
867  switch (VT.getSimpleVT().SimpleTy) {
868    default:
869      assert(false && "Unhandled load/store type!");
870      break;
871    case MVT::i1:
872    case MVT::i8:
873    case MVT::i16:
874    case MVT::i32:
875      if (!useAM3) {
876        // Integer loads/stores handle 12-bit offsets.
877        needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
878        // Handle negative offsets.
879        if (needsLowering && isThumb2)
880          needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
881                            Addr.Offset > -256);
882      } else {
883        // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
884        needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
885      }
886      break;
887    case MVT::f32:
888    case MVT::f64:
889      // Floating point operands handle 8-bit offsets.
890      needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
891      break;
892  }
893
894  // If this is a stack pointer and the offset needs to be simplified then
895  // put the alloca address into a register, set the base type back to
896  // register and continue. This should almost never happen.
897  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
898    TargetRegisterClass *RC = isThumb2 ? ARM::tGPRRegisterClass :
899                              ARM::GPRRegisterClass;
900    unsigned ResultReg = createResultReg(RC);
901    unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
902    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
903                            TII.get(Opc), ResultReg)
904                            .addFrameIndex(Addr.Base.FI)
905                            .addImm(0));
906    Addr.Base.Reg = ResultReg;
907    Addr.BaseType = Address::RegBase;
908  }
909
910  // Since the offset is too large for the load/store instruction
911  // get the reg+offset into a register.
912  if (needsLowering) {
913    Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
914                                 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
915    Addr.Offset = 0;
916  }
917}
918
919void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
920                                       const MachineInstrBuilder &MIB,
921                                       unsigned Flags, bool useAM3) {
922  // addrmode5 output depends on the selection dag addressing dividing the
923  // offset by 4 that it then later multiplies. Do this here as well.
924  if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
925      VT.getSimpleVT().SimpleTy == MVT::f64)
926    Addr.Offset /= 4;
927
928  // Frame base works a bit differently. Handle it separately.
929  if (Addr.BaseType == Address::FrameIndexBase) {
930    int FI = Addr.Base.FI;
931    int Offset = Addr.Offset;
932    MachineMemOperand *MMO =
933          FuncInfo.MF->getMachineMemOperand(
934                                  MachinePointerInfo::getFixedStack(FI, Offset),
935                                  Flags,
936                                  MFI.getObjectSize(FI),
937                                  MFI.getObjectAlignment(FI));
938    // Now add the rest of the operands.
939    MIB.addFrameIndex(FI);
940
941    // ARM halfword load/stores and signed byte loads need an additional
942    // operand.
943    if (useAM3) {
944      signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
945      MIB.addReg(0);
946      MIB.addImm(Imm);
947    } else {
948      MIB.addImm(Addr.Offset);
949    }
950    MIB.addMemOperand(MMO);
951  } else {
952    // Now add the rest of the operands.
953    MIB.addReg(Addr.Base.Reg);
954
955    // ARM halfword load/stores and signed byte loads need an additional
956    // operand.
957    if (useAM3) {
958      signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
959      MIB.addReg(0);
960      MIB.addImm(Imm);
961    } else {
962      MIB.addImm(Addr.Offset);
963    }
964  }
965  AddOptionalDefs(MIB);
966}
967
968bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
969                              bool isZExt = true, bool allocReg = true) {
970  assert(VT.isSimple() && "Non-simple types are invalid here!");
971  unsigned Opc;
972  bool useAM3 = false;
973  TargetRegisterClass *RC;
974  switch (VT.getSimpleVT().SimpleTy) {
975    // This is mostly going to be Neon/vector support.
976    default: return false;
977    case MVT::i1:
978    case MVT::i8:
979      if (isThumb2) {
980        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
981          Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
982        else
983          Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
984      } else {
985        if (isZExt) {
986          Opc = ARM::LDRBi12;
987        } else {
988          Opc = ARM::LDRSB;
989          useAM3 = true;
990        }
991      }
992      RC = ARM::GPRRegisterClass;
993      break;
994    case MVT::i16:
995      if (isThumb2) {
996        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
997          Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
998        else
999          Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1000      } else {
1001        Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1002        useAM3 = true;
1003      }
1004      RC = ARM::GPRRegisterClass;
1005      break;
1006    case MVT::i32:
1007      if (isThumb2) {
1008        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1009          Opc = ARM::t2LDRi8;
1010        else
1011          Opc = ARM::t2LDRi12;
1012      } else {
1013        Opc = ARM::LDRi12;
1014      }
1015      RC = ARM::GPRRegisterClass;
1016      break;
1017    case MVT::f32:
1018      Opc = ARM::VLDRS;
1019      RC = TLI.getRegClassFor(VT);
1020      break;
1021    case MVT::f64:
1022      Opc = ARM::VLDRD;
1023      RC = TLI.getRegClassFor(VT);
1024      break;
1025  }
1026  // Simplify this down to something we can handle.
1027  ARMSimplifyAddress(Addr, VT, useAM3);
1028
1029  // Create the base instruction, then add the operands.
1030  if (allocReg)
1031    ResultReg = createResultReg(RC);
1032  assert (ResultReg > 255 && "Expected an allocated virtual register.");
1033  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1034                                    TII.get(Opc), ResultReg);
1035  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1036  return true;
1037}
1038
1039bool ARMFastISel::SelectLoad(const Instruction *I) {
1040  // Atomic loads need special handling.
1041  if (cast<LoadInst>(I)->isAtomic())
1042    return false;
1043
1044  // Verify we have a legal type before going any further.
1045  MVT VT;
1046  if (!isLoadTypeLegal(I->getType(), VT))
1047    return false;
1048
1049  // See if we can handle this address.
1050  Address Addr;
1051  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1052
1053  unsigned ResultReg;
1054  if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
1055  UpdateValueMap(I, ResultReg);
1056  return true;
1057}
1058
1059bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
1060                               unsigned Alignment) {
1061  unsigned StrOpc;
1062  bool useAM3 = false;
1063  switch (VT.getSimpleVT().SimpleTy) {
1064    // This is mostly going to be Neon/vector support.
1065    default: return false;
1066    case MVT::i1: {
1067      unsigned Res = createResultReg(isThumb2 ? ARM::tGPRRegisterClass :
1068                                               ARM::GPRRegisterClass);
1069      unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1070      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1071                              TII.get(Opc), Res)
1072                      .addReg(SrcReg).addImm(1));
1073      SrcReg = Res;
1074    } // Fallthrough here.
1075    case MVT::i8:
1076      if (isThumb2) {
1077        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1078          StrOpc = ARM::t2STRBi8;
1079        else
1080          StrOpc = ARM::t2STRBi12;
1081      } else {
1082        StrOpc = ARM::STRBi12;
1083      }
1084      break;
1085    case MVT::i16:
1086      if (isThumb2) {
1087        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1088          StrOpc = ARM::t2STRHi8;
1089        else
1090          StrOpc = ARM::t2STRHi12;
1091      } else {
1092        StrOpc = ARM::STRH;
1093        useAM3 = true;
1094      }
1095      break;
1096    case MVT::i32:
1097      if (isThumb2) {
1098        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1099          StrOpc = ARM::t2STRi8;
1100        else
1101          StrOpc = ARM::t2STRi12;
1102      } else {
1103        StrOpc = ARM::STRi12;
1104      }
1105      break;
1106    case MVT::f32:
1107      if (!Subtarget->hasVFP2()) return false;
1108      StrOpc = ARM::VSTRS;
1109      // Unaligned stores need special handling. Floats require word-alignment.
1110      if (Alignment && Alignment < 4) {
1111        unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1112        AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1113                                TII.get(ARM::VMOVRS), MoveReg)
1114                        .addReg(SrcReg));
1115        SrcReg = MoveReg;
1116        VT = MVT::i32;
1117        StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1118      }
1119      break;
1120    case MVT::f64:
1121      if (!Subtarget->hasVFP2()) return false;
1122      // FIXME: Unaligned stores need special handling.  Doublewords require
1123      // word-alignment.
1124      if (Alignment && Alignment < 4) {
1125          return false;
1126      }
1127      StrOpc = ARM::VSTRD;
1128      break;
1129  }
1130  // Simplify this down to something we can handle.
1131  ARMSimplifyAddress(Addr, VT, useAM3);
1132
1133  // Create the base instruction, then add the operands.
1134  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1135                                    TII.get(StrOpc))
1136                            .addReg(SrcReg);
1137  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1138  return true;
1139}
1140
1141bool ARMFastISel::SelectStore(const Instruction *I) {
1142  Value *Op0 = I->getOperand(0);
1143  unsigned SrcReg = 0;
1144
1145  // Atomic stores need special handling.
1146  if (cast<StoreInst>(I)->isAtomic())
1147    return false;
1148
1149  // Verify we have a legal type before going any further.
1150  MVT VT;
1151  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1152    return false;
1153
1154  // Get the value to be stored into a register.
1155  SrcReg = getRegForValue(Op0);
1156  if (SrcReg == 0) return false;
1157
1158  // See if we can handle this address.
1159  Address Addr;
1160  if (!ARMComputeAddress(I->getOperand(1), Addr))
1161    return false;
1162
1163  if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1164    return false;
1165  return true;
1166}
1167
1168static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1169  switch (Pred) {
1170    // Needs two compares...
1171    case CmpInst::FCMP_ONE:
1172    case CmpInst::FCMP_UEQ:
1173    default:
1174      // AL is our "false" for now. The other two need more compares.
1175      return ARMCC::AL;
1176    case CmpInst::ICMP_EQ:
1177    case CmpInst::FCMP_OEQ:
1178      return ARMCC::EQ;
1179    case CmpInst::ICMP_SGT:
1180    case CmpInst::FCMP_OGT:
1181      return ARMCC::GT;
1182    case CmpInst::ICMP_SGE:
1183    case CmpInst::FCMP_OGE:
1184      return ARMCC::GE;
1185    case CmpInst::ICMP_UGT:
1186    case CmpInst::FCMP_UGT:
1187      return ARMCC::HI;
1188    case CmpInst::FCMP_OLT:
1189      return ARMCC::MI;
1190    case CmpInst::ICMP_ULE:
1191    case CmpInst::FCMP_OLE:
1192      return ARMCC::LS;
1193    case CmpInst::FCMP_ORD:
1194      return ARMCC::VC;
1195    case CmpInst::FCMP_UNO:
1196      return ARMCC::VS;
1197    case CmpInst::FCMP_UGE:
1198      return ARMCC::PL;
1199    case CmpInst::ICMP_SLT:
1200    case CmpInst::FCMP_ULT:
1201      return ARMCC::LT;
1202    case CmpInst::ICMP_SLE:
1203    case CmpInst::FCMP_ULE:
1204      return ARMCC::LE;
1205    case CmpInst::FCMP_UNE:
1206    case CmpInst::ICMP_NE:
1207      return ARMCC::NE;
1208    case CmpInst::ICMP_UGE:
1209      return ARMCC::HS;
1210    case CmpInst::ICMP_ULT:
1211      return ARMCC::LO;
1212  }
1213}
1214
1215bool ARMFastISel::SelectBranch(const Instruction *I) {
1216  const BranchInst *BI = cast<BranchInst>(I);
1217  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1218  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1219
1220  // Simple branch support.
1221
1222  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1223  // behavior.
1224  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1225    if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1226
1227      // Get the compare predicate.
1228      // Try to take advantage of fallthrough opportunities.
1229      CmpInst::Predicate Predicate = CI->getPredicate();
1230      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1231        std::swap(TBB, FBB);
1232        Predicate = CmpInst::getInversePredicate(Predicate);
1233      }
1234
1235      ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1236
1237      // We may not handle every CC for now.
1238      if (ARMPred == ARMCC::AL) return false;
1239
1240      // Emit the compare.
1241      if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1242        return false;
1243
1244      unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1245      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1246      .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1247      FastEmitBranch(FBB, DL);
1248      FuncInfo.MBB->addSuccessor(TBB);
1249      return true;
1250    }
1251  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1252    MVT SourceVT;
1253    if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1254        (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1255      unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1256      unsigned OpReg = getRegForValue(TI->getOperand(0));
1257      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1258                              TII.get(TstOpc))
1259                      .addReg(OpReg).addImm(1));
1260
1261      unsigned CCMode = ARMCC::NE;
1262      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1263        std::swap(TBB, FBB);
1264        CCMode = ARMCC::EQ;
1265      }
1266
1267      unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1268      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1269      .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1270
1271      FastEmitBranch(FBB, DL);
1272      FuncInfo.MBB->addSuccessor(TBB);
1273      return true;
1274    }
1275  } else if (const ConstantInt *CI =
1276             dyn_cast<ConstantInt>(BI->getCondition())) {
1277    uint64_t Imm = CI->getZExtValue();
1278    MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1279    FastEmitBranch(Target, DL);
1280    return true;
1281  }
1282
1283  unsigned CmpReg = getRegForValue(BI->getCondition());
1284  if (CmpReg == 0) return false;
1285
1286  // We've been divorced from our compare!  Our block was split, and
1287  // now our compare lives in a predecessor block.  We musn't
1288  // re-compare here, as the children of the compare aren't guaranteed
1289  // live across the block boundary (we *could* check for this).
1290  // Regardless, the compare has been done in the predecessor block,
1291  // and it left a value for us in a virtual register.  Ergo, we test
1292  // the one-bit value left in the virtual register.
1293  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1294  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1295                  .addReg(CmpReg).addImm(1));
1296
1297  unsigned CCMode = ARMCC::NE;
1298  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1299    std::swap(TBB, FBB);
1300    CCMode = ARMCC::EQ;
1301  }
1302
1303  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1304  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1305                  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1306  FastEmitBranch(FBB, DL);
1307  FuncInfo.MBB->addSuccessor(TBB);
1308  return true;
1309}
1310
1311bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1312                             bool isZExt) {
1313  Type *Ty = Src1Value->getType();
1314  EVT SrcVT = TLI.getValueType(Ty, true);
1315  if (!SrcVT.isSimple()) return false;
1316
1317  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1318  if (isFloat && !Subtarget->hasVFP2())
1319    return false;
1320
1321  // Check to see if the 2nd operand is a constant that we can encode directly
1322  // in the compare.
1323  int Imm = 0;
1324  bool UseImm = false;
1325  bool isNegativeImm = false;
1326  // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1327  // Thus, Src1Value may be a ConstantInt, but we're missing it.
1328  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1329    if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1330        SrcVT == MVT::i1) {
1331      const APInt &CIVal = ConstInt->getValue();
1332      Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1333      if (Imm < 0) {
1334        isNegativeImm = true;
1335        Imm = -Imm;
1336      }
1337      UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1338        (ARM_AM::getSOImmVal(Imm) != -1);
1339    }
1340  } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1341    if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1342      if (ConstFP->isZero() && !ConstFP->isNegative())
1343        UseImm = true;
1344  }
1345
1346  unsigned CmpOpc;
1347  bool isICmp = true;
1348  bool needsExt = false;
1349  switch (SrcVT.getSimpleVT().SimpleTy) {
1350    default: return false;
1351    // TODO: Verify compares.
1352    case MVT::f32:
1353      isICmp = false;
1354      CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1355      break;
1356    case MVT::f64:
1357      isICmp = false;
1358      CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1359      break;
1360    case MVT::i1:
1361    case MVT::i8:
1362    case MVT::i16:
1363      needsExt = true;
1364    // Intentional fall-through.
1365    case MVT::i32:
1366      if (isThumb2) {
1367        if (!UseImm)
1368          CmpOpc = ARM::t2CMPrr;
1369        else
1370          CmpOpc = isNegativeImm ? ARM::t2CMNzri : ARM::t2CMPri;
1371      } else {
1372        if (!UseImm)
1373          CmpOpc = ARM::CMPrr;
1374        else
1375          CmpOpc = isNegativeImm ? ARM::CMNzri : ARM::CMPri;
1376      }
1377      break;
1378  }
1379
1380  unsigned SrcReg1 = getRegForValue(Src1Value);
1381  if (SrcReg1 == 0) return false;
1382
1383  unsigned SrcReg2 = 0;
1384  if (!UseImm) {
1385    SrcReg2 = getRegForValue(Src2Value);
1386    if (SrcReg2 == 0) return false;
1387  }
1388
1389  // We have i1, i8, or i16, we need to either zero extend or sign extend.
1390  if (needsExt) {
1391    unsigned ResultReg;
1392    ResultReg = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1393    if (ResultReg == 0) return false;
1394    SrcReg1 = ResultReg;
1395    if (!UseImm) {
1396      ResultReg = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1397      if (ResultReg == 0) return false;
1398      SrcReg2 = ResultReg;
1399    }
1400  }
1401
1402  if (!UseImm) {
1403    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1404                            TII.get(CmpOpc))
1405                    .addReg(SrcReg1).addReg(SrcReg2));
1406  } else {
1407    MachineInstrBuilder MIB;
1408    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1409      .addReg(SrcReg1);
1410
1411    // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1412    if (isICmp)
1413      MIB.addImm(Imm);
1414    AddOptionalDefs(MIB);
1415  }
1416
1417  // For floating point we need to move the result to a comparison register
1418  // that we can then use for branches.
1419  if (Ty->isFloatTy() || Ty->isDoubleTy())
1420    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1421                            TII.get(ARM::FMSTAT)));
1422  return true;
1423}
1424
1425bool ARMFastISel::SelectCmp(const Instruction *I) {
1426  const CmpInst *CI = cast<CmpInst>(I);
1427  Type *Ty = CI->getOperand(0)->getType();
1428
1429  // Get the compare predicate.
1430  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1431
1432  // We may not handle every CC for now.
1433  if (ARMPred == ARMCC::AL) return false;
1434
1435  // Emit the compare.
1436  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1437    return false;
1438
1439  // Now set a register based on the comparison. Explicitly set the predicates
1440  // here.
1441  unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1442  TargetRegisterClass *RC = isThumb2 ? ARM::rGPRRegisterClass
1443                                    : ARM::GPRRegisterClass;
1444  unsigned DestReg = createResultReg(RC);
1445  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1446  unsigned ZeroReg = TargetMaterializeConstant(Zero);
1447  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1448  unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
1449  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1450          .addReg(ZeroReg).addImm(1)
1451          .addImm(ARMPred).addReg(CondReg);
1452
1453  UpdateValueMap(I, DestReg);
1454  return true;
1455}
1456
1457bool ARMFastISel::SelectFPExt(const Instruction *I) {
1458  // Make sure we have VFP and that we're extending float to double.
1459  if (!Subtarget->hasVFP2()) return false;
1460
1461  Value *V = I->getOperand(0);
1462  if (!I->getType()->isDoubleTy() ||
1463      !V->getType()->isFloatTy()) return false;
1464
1465  unsigned Op = getRegForValue(V);
1466  if (Op == 0) return false;
1467
1468  unsigned Result = createResultReg(ARM::DPRRegisterClass);
1469  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1470                          TII.get(ARM::VCVTDS), Result)
1471                  .addReg(Op));
1472  UpdateValueMap(I, Result);
1473  return true;
1474}
1475
1476bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1477  // Make sure we have VFP and that we're truncating double to float.
1478  if (!Subtarget->hasVFP2()) return false;
1479
1480  Value *V = I->getOperand(0);
1481  if (!(I->getType()->isFloatTy() &&
1482        V->getType()->isDoubleTy())) return false;
1483
1484  unsigned Op = getRegForValue(V);
1485  if (Op == 0) return false;
1486
1487  unsigned Result = createResultReg(ARM::SPRRegisterClass);
1488  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1489                          TII.get(ARM::VCVTSD), Result)
1490                  .addReg(Op));
1491  UpdateValueMap(I, Result);
1492  return true;
1493}
1494
1495bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1496  // Make sure we have VFP.
1497  if (!Subtarget->hasVFP2()) return false;
1498
1499  MVT DstVT;
1500  Type *Ty = I->getType();
1501  if (!isTypeLegal(Ty, DstVT))
1502    return false;
1503
1504  Value *Src = I->getOperand(0);
1505  EVT SrcVT = TLI.getValueType(Src->getType(), true);
1506  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1507    return false;
1508
1509  unsigned SrcReg = getRegForValue(Src);
1510  if (SrcReg == 0) return false;
1511
1512  // Handle sign-extension.
1513  if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1514    EVT DestVT = MVT::i32;
1515    unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, /*isZExt*/ false);
1516    if (ResultReg == 0) return false;
1517    SrcReg = ResultReg;
1518  }
1519
1520  // The conversion routine works on fp-reg to fp-reg and the operand above
1521  // was an integer, move it to the fp registers if possible.
1522  unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1523  if (FP == 0) return false;
1524
1525  unsigned Opc;
1526  if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1527  else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1528  else return false;
1529
1530  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1531  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1532                          ResultReg)
1533                  .addReg(FP));
1534  UpdateValueMap(I, ResultReg);
1535  return true;
1536}
1537
1538bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1539  // Make sure we have VFP.
1540  if (!Subtarget->hasVFP2()) return false;
1541
1542  MVT DstVT;
1543  Type *RetTy = I->getType();
1544  if (!isTypeLegal(RetTy, DstVT))
1545    return false;
1546
1547  unsigned Op = getRegForValue(I->getOperand(0));
1548  if (Op == 0) return false;
1549
1550  unsigned Opc;
1551  Type *OpTy = I->getOperand(0)->getType();
1552  if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1553  else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1554  else return false;
1555
1556  // f64->s32 or f32->s32 both need an intermediate f32 reg.
1557  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1558  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1559                          ResultReg)
1560                  .addReg(Op));
1561
1562  // This result needs to be in an integer register, but the conversion only
1563  // takes place in fp-regs.
1564  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1565  if (IntReg == 0) return false;
1566
1567  UpdateValueMap(I, IntReg);
1568  return true;
1569}
1570
1571bool ARMFastISel::SelectSelect(const Instruction *I) {
1572  MVT VT;
1573  if (!isTypeLegal(I->getType(), VT))
1574    return false;
1575
1576  // Things need to be register sized for register moves.
1577  if (VT != MVT::i32) return false;
1578  const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1579
1580  unsigned CondReg = getRegForValue(I->getOperand(0));
1581  if (CondReg == 0) return false;
1582  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1583  if (Op1Reg == 0) return false;
1584
1585  // Check to see if we can use an immediate in the conditional move.
1586  int Imm = 0;
1587  bool UseImm = false;
1588  bool isNegativeImm = false;
1589  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1590    assert (VT == MVT::i32 && "Expecting an i32.");
1591    Imm = (int)ConstInt->getValue().getZExtValue();
1592    if (Imm < 0) {
1593      isNegativeImm = true;
1594      Imm = ~Imm;
1595    }
1596    UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1597      (ARM_AM::getSOImmVal(Imm) != -1);
1598  }
1599
1600  unsigned Op2Reg = 0;
1601  if (!UseImm) {
1602    Op2Reg = getRegForValue(I->getOperand(2));
1603    if (Op2Reg == 0) return false;
1604  }
1605
1606  unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1607  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1608                  .addReg(CondReg).addImm(0));
1609
1610  unsigned MovCCOpc;
1611  if (!UseImm) {
1612    MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1613  } else {
1614    if (!isNegativeImm) {
1615      MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1616    } else {
1617      MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1618    }
1619  }
1620  unsigned ResultReg = createResultReg(RC);
1621  if (!UseImm)
1622    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1623    .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1624  else
1625    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1626    .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1627  UpdateValueMap(I, ResultReg);
1628  return true;
1629}
1630
1631bool ARMFastISel::SelectSDiv(const Instruction *I) {
1632  MVT VT;
1633  Type *Ty = I->getType();
1634  if (!isTypeLegal(Ty, VT))
1635    return false;
1636
1637  // If we have integer div support we should have selected this automagically.
1638  // In case we have a real miss go ahead and return false and we'll pick
1639  // it up later.
1640  if (Subtarget->hasDivide()) return false;
1641
1642  // Otherwise emit a libcall.
1643  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1644  if (VT == MVT::i8)
1645    LC = RTLIB::SDIV_I8;
1646  else if (VT == MVT::i16)
1647    LC = RTLIB::SDIV_I16;
1648  else if (VT == MVT::i32)
1649    LC = RTLIB::SDIV_I32;
1650  else if (VT == MVT::i64)
1651    LC = RTLIB::SDIV_I64;
1652  else if (VT == MVT::i128)
1653    LC = RTLIB::SDIV_I128;
1654  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1655
1656  return ARMEmitLibcall(I, LC);
1657}
1658
1659bool ARMFastISel::SelectSRem(const Instruction *I) {
1660  MVT VT;
1661  Type *Ty = I->getType();
1662  if (!isTypeLegal(Ty, VT))
1663    return false;
1664
1665  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1666  if (VT == MVT::i8)
1667    LC = RTLIB::SREM_I8;
1668  else if (VT == MVT::i16)
1669    LC = RTLIB::SREM_I16;
1670  else if (VT == MVT::i32)
1671    LC = RTLIB::SREM_I32;
1672  else if (VT == MVT::i64)
1673    LC = RTLIB::SREM_I64;
1674  else if (VT == MVT::i128)
1675    LC = RTLIB::SREM_I128;
1676  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1677
1678  return ARMEmitLibcall(I, LC);
1679}
1680
1681bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1682  EVT VT  = TLI.getValueType(I->getType(), true);
1683
1684  // We can get here in the case when we want to use NEON for our fp
1685  // operations, but can't figure out how to. Just use the vfp instructions
1686  // if we have them.
1687  // FIXME: It'd be nice to use NEON instructions.
1688  Type *Ty = I->getType();
1689  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1690  if (isFloat && !Subtarget->hasVFP2())
1691    return false;
1692
1693  unsigned Opc;
1694  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1695  switch (ISDOpcode) {
1696    default: return false;
1697    case ISD::FADD:
1698      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1699      break;
1700    case ISD::FSUB:
1701      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1702      break;
1703    case ISD::FMUL:
1704      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1705      break;
1706  }
1707  unsigned Op1 = getRegForValue(I->getOperand(0));
1708  if (Op1 == 0) return false;
1709
1710  unsigned Op2 = getRegForValue(I->getOperand(1));
1711  if (Op2 == 0) return false;
1712
1713  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1714  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1715                          TII.get(Opc), ResultReg)
1716                  .addReg(Op1).addReg(Op2));
1717  UpdateValueMap(I, ResultReg);
1718  return true;
1719}
1720
1721// Call Handling Code
1722
1723// This is largely taken directly from CCAssignFnForNode - we don't support
1724// varargs in FastISel so that part has been removed.
1725// TODO: We may not support all of this.
1726CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1727  switch (CC) {
1728  default:
1729    llvm_unreachable("Unsupported calling convention");
1730  case CallingConv::Fast:
1731    // Ignore fastcc. Silence compiler warnings.
1732    (void)RetFastCC_ARM_APCS;
1733    (void)FastCC_ARM_APCS;
1734    // Fallthrough
1735  case CallingConv::C:
1736    // Use target triple & subtarget features to do actual dispatch.
1737    if (Subtarget->isAAPCS_ABI()) {
1738      if (Subtarget->hasVFP2() &&
1739          TM.Options.FloatABIType == FloatABI::Hard)
1740        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1741      else
1742        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1743    } else
1744        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1745  case CallingConv::ARM_AAPCS_VFP:
1746    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1747  case CallingConv::ARM_AAPCS:
1748    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1749  case CallingConv::ARM_APCS:
1750    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1751  }
1752}
1753
1754bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1755                                  SmallVectorImpl<unsigned> &ArgRegs,
1756                                  SmallVectorImpl<MVT> &ArgVTs,
1757                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1758                                  SmallVectorImpl<unsigned> &RegArgs,
1759                                  CallingConv::ID CC,
1760                                  unsigned &NumBytes) {
1761  SmallVector<CCValAssign, 16> ArgLocs;
1762  CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1763  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1764
1765  // Get a count of how many bytes are to be pushed on the stack.
1766  NumBytes = CCInfo.getNextStackOffset();
1767
1768  // Issue CALLSEQ_START
1769  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1770  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1771                          TII.get(AdjStackDown))
1772                  .addImm(NumBytes));
1773
1774  // Process the args.
1775  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1776    CCValAssign &VA = ArgLocs[i];
1777    unsigned Arg = ArgRegs[VA.getValNo()];
1778    MVT ArgVT = ArgVTs[VA.getValNo()];
1779
1780    // We don't handle NEON/vector parameters yet.
1781    if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1782      return false;
1783
1784    // Handle arg promotion, etc.
1785    switch (VA.getLocInfo()) {
1786      case CCValAssign::Full: break;
1787      case CCValAssign::SExt: {
1788        MVT DestVT = VA.getLocVT();
1789        unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT,
1790                                           /*isZExt*/false);
1791        assert (ResultReg != 0 && "Failed to emit a sext");
1792        Arg = ResultReg;
1793        ArgVT = DestVT;
1794        break;
1795      }
1796      case CCValAssign::AExt:
1797        // Intentional fall-through.  Handle AExt and ZExt.
1798      case CCValAssign::ZExt: {
1799        MVT DestVT = VA.getLocVT();
1800        unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT,
1801                                           /*isZExt*/true);
1802        assert (ResultReg != 0 && "Failed to emit a sext");
1803        Arg = ResultReg;
1804        ArgVT = DestVT;
1805        break;
1806      }
1807      case CCValAssign::BCvt: {
1808        unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1809                                 /*TODO: Kill=*/false);
1810        assert(BC != 0 && "Failed to emit a bitcast!");
1811        Arg = BC;
1812        ArgVT = VA.getLocVT();
1813        break;
1814      }
1815      default: llvm_unreachable("Unknown arg promotion!");
1816    }
1817
1818    // Now copy/store arg to correct locations.
1819    if (VA.isRegLoc() && !VA.needsCustom()) {
1820      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1821              VA.getLocReg())
1822        .addReg(Arg);
1823      RegArgs.push_back(VA.getLocReg());
1824    } else if (VA.needsCustom()) {
1825      // TODO: We need custom lowering for vector (v2f64) args.
1826      if (VA.getLocVT() != MVT::f64) return false;
1827
1828      CCValAssign &NextVA = ArgLocs[++i];
1829
1830      // TODO: Only handle register args for now.
1831      if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1832
1833      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1834                              TII.get(ARM::VMOVRRD), VA.getLocReg())
1835                      .addReg(NextVA.getLocReg(), RegState::Define)
1836                      .addReg(Arg));
1837      RegArgs.push_back(VA.getLocReg());
1838      RegArgs.push_back(NextVA.getLocReg());
1839    } else {
1840      assert(VA.isMemLoc());
1841      // Need to store on the stack.
1842      Address Addr;
1843      Addr.BaseType = Address::RegBase;
1844      Addr.Base.Reg = ARM::SP;
1845      Addr.Offset = VA.getLocMemOffset();
1846
1847      if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1848    }
1849  }
1850  return true;
1851}
1852
1853bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1854                             const Instruction *I, CallingConv::ID CC,
1855                             unsigned &NumBytes) {
1856  // Issue CALLSEQ_END
1857  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1858  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1859                          TII.get(AdjStackUp))
1860                  .addImm(NumBytes).addImm(0));
1861
1862  // Now the return value.
1863  if (RetVT != MVT::isVoid) {
1864    SmallVector<CCValAssign, 16> RVLocs;
1865    CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1866    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1867
1868    // Copy all of the result registers out of their specified physreg.
1869    if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1870      // For this move we copy into two registers and then move into the
1871      // double fp reg we want.
1872      EVT DestVT = RVLocs[0].getValVT();
1873      TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1874      unsigned ResultReg = createResultReg(DstRC);
1875      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1876                              TII.get(ARM::VMOVDRR), ResultReg)
1877                      .addReg(RVLocs[0].getLocReg())
1878                      .addReg(RVLocs[1].getLocReg()));
1879
1880      UsedRegs.push_back(RVLocs[0].getLocReg());
1881      UsedRegs.push_back(RVLocs[1].getLocReg());
1882
1883      // Finally update the result.
1884      UpdateValueMap(I, ResultReg);
1885    } else {
1886      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1887      EVT CopyVT = RVLocs[0].getValVT();
1888
1889      // Special handling for extended integers.
1890      if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1891        CopyVT = MVT::i32;
1892
1893      TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1894
1895      unsigned ResultReg = createResultReg(DstRC);
1896      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1897              ResultReg).addReg(RVLocs[0].getLocReg());
1898      UsedRegs.push_back(RVLocs[0].getLocReg());
1899
1900      // Finally update the result.
1901      UpdateValueMap(I, ResultReg);
1902    }
1903  }
1904
1905  return true;
1906}
1907
1908bool ARMFastISel::SelectRet(const Instruction *I) {
1909  const ReturnInst *Ret = cast<ReturnInst>(I);
1910  const Function &F = *I->getParent()->getParent();
1911
1912  if (!FuncInfo.CanLowerReturn)
1913    return false;
1914
1915  if (F.isVarArg())
1916    return false;
1917
1918  CallingConv::ID CC = F.getCallingConv();
1919  if (Ret->getNumOperands() > 0) {
1920    SmallVector<ISD::OutputArg, 4> Outs;
1921    GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1922                  Outs, TLI);
1923
1924    // Analyze operands of the call, assigning locations to each operand.
1925    SmallVector<CCValAssign, 16> ValLocs;
1926    CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
1927    CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1928
1929    const Value *RV = Ret->getOperand(0);
1930    unsigned Reg = getRegForValue(RV);
1931    if (Reg == 0)
1932      return false;
1933
1934    // Only handle a single return value for now.
1935    if (ValLocs.size() != 1)
1936      return false;
1937
1938    CCValAssign &VA = ValLocs[0];
1939
1940    // Don't bother handling odd stuff for now.
1941    if (VA.getLocInfo() != CCValAssign::Full)
1942      return false;
1943    // Only handle register returns for now.
1944    if (!VA.isRegLoc())
1945      return false;
1946
1947    unsigned SrcReg = Reg + VA.getValNo();
1948    EVT RVVT = TLI.getValueType(RV->getType());
1949    EVT DestVT = VA.getValVT();
1950    // Special handling for extended integers.
1951    if (RVVT != DestVT) {
1952      if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1953        return false;
1954
1955      if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1956        return false;
1957
1958      assert(DestVT == MVT::i32 && "ARM should always ext to i32");
1959
1960      bool isZExt = Outs[0].Flags.isZExt();
1961      unsigned ResultReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, isZExt);
1962      if (ResultReg == 0) return false;
1963      SrcReg = ResultReg;
1964    }
1965
1966    // Make the copy.
1967    unsigned DstReg = VA.getLocReg();
1968    const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1969    // Avoid a cross-class copy. This is very unlikely.
1970    if (!SrcRC->contains(DstReg))
1971      return false;
1972    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1973            DstReg).addReg(SrcReg);
1974
1975    // Mark the register as live out of the function.
1976    MRI.addLiveOut(VA.getLocReg());
1977  }
1978
1979  unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
1980  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1981                          TII.get(RetOpc)));
1982  return true;
1983}
1984
1985unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1986
1987  // Darwin needs the r9 versions of the opcodes.
1988  bool isDarwin = Subtarget->isTargetDarwin();
1989  if (isThumb2) {
1990    return isDarwin ? ARM::tBLr9 : ARM::tBL;
1991  } else  {
1992    return isDarwin ? ARM::BLr9 : ARM::BL;
1993  }
1994}
1995
1996// A quick function that will emit a call for a named libcall in F with the
1997// vector of passed arguments for the Instruction in I. We can assume that we
1998// can emit a call for any libcall we can produce. This is an abridged version
1999// of the full call infrastructure since we won't need to worry about things
2000// like computed function pointers or strange arguments at call sites.
2001// TODO: Try to unify this and the normal call bits for ARM, then try to unify
2002// with X86.
2003bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2004  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2005
2006  // Handle *simple* calls for now.
2007  Type *RetTy = I->getType();
2008  MVT RetVT;
2009  if (RetTy->isVoidTy())
2010    RetVT = MVT::isVoid;
2011  else if (!isTypeLegal(RetTy, RetVT))
2012    return false;
2013
2014  // TODO: For now if we have long calls specified we don't handle the call.
2015  if (EnableARMLongCalls) return false;
2016
2017  // Set up the argument vectors.
2018  SmallVector<Value*, 8> Args;
2019  SmallVector<unsigned, 8> ArgRegs;
2020  SmallVector<MVT, 8> ArgVTs;
2021  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2022  Args.reserve(I->getNumOperands());
2023  ArgRegs.reserve(I->getNumOperands());
2024  ArgVTs.reserve(I->getNumOperands());
2025  ArgFlags.reserve(I->getNumOperands());
2026  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2027    Value *Op = I->getOperand(i);
2028    unsigned Arg = getRegForValue(Op);
2029    if (Arg == 0) return false;
2030
2031    Type *ArgTy = Op->getType();
2032    MVT ArgVT;
2033    if (!isTypeLegal(ArgTy, ArgVT)) return false;
2034
2035    ISD::ArgFlagsTy Flags;
2036    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2037    Flags.setOrigAlign(OriginalAlignment);
2038
2039    Args.push_back(Op);
2040    ArgRegs.push_back(Arg);
2041    ArgVTs.push_back(ArgVT);
2042    ArgFlags.push_back(Flags);
2043  }
2044
2045  // Handle the arguments now that we've gotten them.
2046  SmallVector<unsigned, 4> RegArgs;
2047  unsigned NumBytes;
2048  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
2049    return false;
2050
2051  // Issue the call, BLr9 for darwin, BL otherwise.
2052  // TODO: Turn this into the table of arm call ops.
2053  MachineInstrBuilder MIB;
2054  unsigned CallOpc = ARMSelectCallOp(NULL);
2055  if(isThumb2)
2056    // Explicitly adding the predicate here.
2057    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2058                         TII.get(CallOpc)))
2059                         .addExternalSymbol(TLI.getLibcallName(Call));
2060  else
2061    // Explicitly adding the predicate here.
2062    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2063                         TII.get(CallOpc))
2064          .addExternalSymbol(TLI.getLibcallName(Call)));
2065
2066  // Add implicit physical register uses to the call.
2067  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2068    MIB.addReg(RegArgs[i]);
2069
2070  // Finish off the call including any return values.
2071  SmallVector<unsigned, 4> UsedRegs;
2072  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
2073
2074  // Set all unused physreg defs as dead.
2075  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2076
2077  return true;
2078}
2079
2080bool ARMFastISel::SelectCall(const Instruction *I,
2081                             const char *IntrMemName = 0) {
2082  const CallInst *CI = cast<CallInst>(I);
2083  const Value *Callee = CI->getCalledValue();
2084
2085  // Can't handle inline asm.
2086  if (isa<InlineAsm>(Callee)) return false;
2087
2088  // Only handle global variable Callees.
2089  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2090  if (!GV)
2091    return false;
2092
2093  // Check the calling convention.
2094  ImmutableCallSite CS(CI);
2095  CallingConv::ID CC = CS.getCallingConv();
2096
2097  // TODO: Avoid some calling conventions?
2098
2099  // Let SDISel handle vararg functions.
2100  PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2101  FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2102  if (FTy->isVarArg())
2103    return false;
2104
2105  // Handle *simple* calls for now.
2106  Type *RetTy = I->getType();
2107  MVT RetVT;
2108  if (RetTy->isVoidTy())
2109    RetVT = MVT::isVoid;
2110  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2111           RetVT != MVT::i8  && RetVT != MVT::i1)
2112    return false;
2113
2114  // TODO: For now if we have long calls specified we don't handle the call.
2115  if (EnableARMLongCalls) return false;
2116
2117  // Set up the argument vectors.
2118  SmallVector<Value*, 8> Args;
2119  SmallVector<unsigned, 8> ArgRegs;
2120  SmallVector<MVT, 8> ArgVTs;
2121  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2122  Args.reserve(CS.arg_size());
2123  ArgRegs.reserve(CS.arg_size());
2124  ArgVTs.reserve(CS.arg_size());
2125  ArgFlags.reserve(CS.arg_size());
2126  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2127       i != e; ++i) {
2128    // If we're lowering a memory intrinsic instead of a regular call, skip the
2129    // last two arguments, which shouldn't be passed to the underlying function.
2130    if (IntrMemName && e-i <= 2)
2131      break;
2132
2133    ISD::ArgFlagsTy Flags;
2134    unsigned AttrInd = i - CS.arg_begin() + 1;
2135    if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2136      Flags.setSExt();
2137    if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2138      Flags.setZExt();
2139
2140    // FIXME: Only handle *easy* calls for now.
2141    if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2142        CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2143        CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2144        CS.paramHasAttr(AttrInd, Attribute::ByVal))
2145      return false;
2146
2147    Type *ArgTy = (*i)->getType();
2148    MVT ArgVT;
2149    if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2150        ArgVT != MVT::i1)
2151      return false;
2152
2153    unsigned Arg = getRegForValue(*i);
2154    if (Arg == 0)
2155      return false;
2156
2157    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2158    Flags.setOrigAlign(OriginalAlignment);
2159
2160    Args.push_back(*i);
2161    ArgRegs.push_back(Arg);
2162    ArgVTs.push_back(ArgVT);
2163    ArgFlags.push_back(Flags);
2164  }
2165
2166  // Handle the arguments now that we've gotten them.
2167  SmallVector<unsigned, 4> RegArgs;
2168  unsigned NumBytes;
2169  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
2170    return false;
2171
2172  // Issue the call, BLr9 for darwin, BL otherwise.
2173  // TODO: Turn this into the table of arm call ops.
2174  MachineInstrBuilder MIB;
2175  unsigned CallOpc = ARMSelectCallOp(GV);
2176  // Explicitly adding the predicate here.
2177  if(isThumb2) {
2178    // Explicitly adding the predicate here.
2179    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2180                                 TII.get(CallOpc)));
2181    if (!IntrMemName)
2182      MIB.addGlobalAddress(GV, 0, 0);
2183    else
2184      MIB.addExternalSymbol(IntrMemName, 0);
2185  } else {
2186    if (!IntrMemName)
2187      // Explicitly adding the predicate here.
2188      MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2189                                   TII.get(CallOpc))
2190            .addGlobalAddress(GV, 0, 0));
2191    else
2192      MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2193                                   TII.get(CallOpc))
2194            .addExternalSymbol(IntrMemName, 0));
2195  }
2196
2197  // Add implicit physical register uses to the call.
2198  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2199    MIB.addReg(RegArgs[i]);
2200
2201  // Finish off the call including any return values.
2202  SmallVector<unsigned, 4> UsedRegs;
2203  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
2204
2205  // Set all unused physreg defs as dead.
2206  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2207
2208  return true;
2209}
2210
2211bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2212  return Len <= 16;
2213}
2214
2215bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len) {
2216  // Make sure we don't bloat code by inlining very large memcpy's.
2217  if (!ARMIsMemCpySmall(Len))
2218    return false;
2219
2220  // We don't care about alignment here since we just emit integer accesses.
2221  while (Len) {
2222    MVT VT;
2223    if (Len >= 4)
2224      VT = MVT::i32;
2225    else if (Len >= 2)
2226      VT = MVT::i16;
2227    else {
2228      assert(Len == 1);
2229      VT = MVT::i8;
2230    }
2231
2232    bool RV;
2233    unsigned ResultReg;
2234    RV = ARMEmitLoad(VT, ResultReg, Src);
2235    assert (RV = true && "Should be able to handle this load.");
2236    RV = ARMEmitStore(VT, ResultReg, Dest);
2237    assert (RV = true && "Should be able to handle this store.");
2238
2239    unsigned Size = VT.getSizeInBits()/8;
2240    Len -= Size;
2241    Dest.Offset += Size;
2242    Src.Offset += Size;
2243  }
2244
2245  return true;
2246}
2247
2248bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2249  // FIXME: Handle more intrinsics.
2250  switch (I.getIntrinsicID()) {
2251  default: return false;
2252  case Intrinsic::memcpy:
2253  case Intrinsic::memmove: {
2254    const MemTransferInst &MTI = cast<MemTransferInst>(I);
2255    // Don't handle volatile.
2256    if (MTI.isVolatile())
2257      return false;
2258
2259    // Disable inlining for memmove before calls to ComputeAddress.  Otherwise,
2260    // we would emit dead code because we don't currently handle memmoves.
2261    bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2262    if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2263      // Small memcpy's are common enough that we want to do them without a call
2264      // if possible.
2265      uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2266      if (ARMIsMemCpySmall(Len)) {
2267        Address Dest, Src;
2268        if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2269            !ARMComputeAddress(MTI.getRawSource(), Src))
2270          return false;
2271        if (ARMTryEmitSmallMemCpy(Dest, Src, Len))
2272          return true;
2273      }
2274    }
2275
2276    if (!MTI.getLength()->getType()->isIntegerTy(32))
2277      return false;
2278
2279    if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2280      return false;
2281
2282    const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2283    return SelectCall(&I, IntrMemName);
2284  }
2285  case Intrinsic::memset: {
2286    const MemSetInst &MSI = cast<MemSetInst>(I);
2287    // Don't handle volatile.
2288    if (MSI.isVolatile())
2289      return false;
2290
2291    if (!MSI.getLength()->getType()->isIntegerTy(32))
2292      return false;
2293
2294    if (MSI.getDestAddressSpace() > 255)
2295      return false;
2296
2297    return SelectCall(&I, "memset");
2298  }
2299  }
2300  return false;
2301}
2302
2303bool ARMFastISel::SelectTrunc(const Instruction *I) {
2304  // The high bits for a type smaller than the register size are assumed to be
2305  // undefined.
2306  Value *Op = I->getOperand(0);
2307
2308  EVT SrcVT, DestVT;
2309  SrcVT = TLI.getValueType(Op->getType(), true);
2310  DestVT = TLI.getValueType(I->getType(), true);
2311
2312  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2313    return false;
2314  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2315    return false;
2316
2317  unsigned SrcReg = getRegForValue(Op);
2318  if (!SrcReg) return false;
2319
2320  // Because the high bits are undefined, a truncate doesn't generate
2321  // any code.
2322  UpdateValueMap(I, SrcReg);
2323  return true;
2324}
2325
2326unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
2327                                    bool isZExt) {
2328  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2329    return 0;
2330
2331  unsigned Opc;
2332  bool isBoolZext = false;
2333  if (!SrcVT.isSimple()) return 0;
2334  switch (SrcVT.getSimpleVT().SimpleTy) {
2335  default: return 0;
2336  case MVT::i16:
2337    if (!Subtarget->hasV6Ops()) return 0;
2338    if (isZExt)
2339      Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
2340    else
2341      Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
2342    break;
2343  case MVT::i8:
2344    if (!Subtarget->hasV6Ops()) return 0;
2345    if (isZExt)
2346      Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
2347    else
2348      Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
2349    break;
2350  case MVT::i1:
2351    if (isZExt) {
2352      Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
2353      isBoolZext = true;
2354      break;
2355    }
2356    return 0;
2357  }
2358
2359  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2360  MachineInstrBuilder MIB;
2361  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
2362        .addReg(SrcReg);
2363  if (isBoolZext)
2364    MIB.addImm(1);
2365  else
2366    MIB.addImm(0);
2367  AddOptionalDefs(MIB);
2368  return ResultReg;
2369}
2370
2371bool ARMFastISel::SelectIntExt(const Instruction *I) {
2372  // On ARM, in general, integer casts don't involve legal types; this code
2373  // handles promotable integers.
2374  Type *DestTy = I->getType();
2375  Value *Src = I->getOperand(0);
2376  Type *SrcTy = Src->getType();
2377
2378  EVT SrcVT, DestVT;
2379  SrcVT = TLI.getValueType(SrcTy, true);
2380  DestVT = TLI.getValueType(DestTy, true);
2381
2382  bool isZExt = isa<ZExtInst>(I);
2383  unsigned SrcReg = getRegForValue(Src);
2384  if (!SrcReg) return false;
2385
2386  unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2387  if (ResultReg == 0) return false;
2388  UpdateValueMap(I, ResultReg);
2389  return true;
2390}
2391
2392// TODO: SoftFP support.
2393bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2394
2395  switch (I->getOpcode()) {
2396    case Instruction::Load:
2397      return SelectLoad(I);
2398    case Instruction::Store:
2399      return SelectStore(I);
2400    case Instruction::Br:
2401      return SelectBranch(I);
2402    case Instruction::ICmp:
2403    case Instruction::FCmp:
2404      return SelectCmp(I);
2405    case Instruction::FPExt:
2406      return SelectFPExt(I);
2407    case Instruction::FPTrunc:
2408      return SelectFPTrunc(I);
2409    case Instruction::SIToFP:
2410      return SelectSIToFP(I);
2411    case Instruction::FPToSI:
2412      return SelectFPToSI(I);
2413    case Instruction::FAdd:
2414      return SelectBinaryOp(I, ISD::FADD);
2415    case Instruction::FSub:
2416      return SelectBinaryOp(I, ISD::FSUB);
2417    case Instruction::FMul:
2418      return SelectBinaryOp(I, ISD::FMUL);
2419    case Instruction::SDiv:
2420      return SelectSDiv(I);
2421    case Instruction::SRem:
2422      return SelectSRem(I);
2423    case Instruction::Call:
2424      if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2425        return SelectIntrinsicCall(*II);
2426      return SelectCall(I);
2427    case Instruction::Select:
2428      return SelectSelect(I);
2429    case Instruction::Ret:
2430      return SelectRet(I);
2431    case Instruction::Trunc:
2432      return SelectTrunc(I);
2433    case Instruction::ZExt:
2434    case Instruction::SExt:
2435      return SelectIntExt(I);
2436    default: break;
2437  }
2438  return false;
2439}
2440
2441/// TryToFoldLoad - The specified machine instr operand is a vreg, and that
2442/// vreg is being provided by the specified load instruction.  If possible,
2443/// try to fold the load as an operand to the instruction, returning true if
2444/// successful.
2445bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
2446                                const LoadInst *LI) {
2447  // Verify we have a legal type before going any further.
2448  MVT VT;
2449  if (!isLoadTypeLegal(LI->getType(), VT))
2450    return false;
2451
2452  // Combine load followed by zero- or sign-extend.
2453  // ldrb r1, [r0]       ldrb r1, [r0]
2454  // uxtb r2, r1     =>
2455  // mov  r3, r2         mov  r3, r1
2456  bool isZExt = true;
2457  switch(MI->getOpcode()) {
2458    default: return false;
2459    case ARM::SXTH:
2460    case ARM::t2SXTH:
2461      isZExt = false;
2462    case ARM::UXTH:
2463    case ARM::t2UXTH:
2464      if (VT != MVT::i16)
2465        return false;
2466    break;
2467    case ARM::SXTB:
2468    case ARM::t2SXTB:
2469      isZExt = false;
2470    case ARM::UXTB:
2471    case ARM::t2UXTB:
2472      if (VT != MVT::i8)
2473        return false;
2474    break;
2475  }
2476  // See if we can handle this address.
2477  Address Addr;
2478  if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2479
2480  unsigned ResultReg = MI->getOperand(0).getReg();
2481  if (!ARMEmitLoad(VT, ResultReg, Addr, isZExt, false))
2482    return false;
2483  MI->eraseFromParent();
2484  return true;
2485}
2486
2487namespace llvm {
2488  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2489    // Completely untested on non-darwin.
2490    const TargetMachine &TM = funcInfo.MF->getTarget();
2491
2492    // Darwin and thumb1 only for now.
2493    const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2494    if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2495        !DisableARMFastISel)
2496      return new ARMFastISel(funcInfo);
2497    return 0;
2498  }
2499}
2500