ARMFastISel.cpp revision fa87d6675212d5ca04725b7e541156f58c4ab40b
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the ARM-specific support for the FastISel class. Some 11// of the target-specific code is generated by tablegen in the file 12// ARMGenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "ARM.h" 17#include "ARMBaseInstrInfo.h" 18#include "ARMCallingConv.h" 19#include "ARMRegisterInfo.h" 20#include "ARMTargetMachine.h" 21#include "ARMSubtarget.h" 22#include "ARMConstantPoolValue.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Instructions.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/Analysis.h" 30#include "llvm/CodeGen/FastISel.h" 31#include "llvm/CodeGen/FunctionLoweringInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineConstantPool.h" 35#include "llvm/CodeGen/MachineFrameInfo.h" 36#include "llvm/CodeGen/MachineMemOperand.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/PseudoSourceValue.h" 39#include "llvm/Support/CallSite.h" 40#include "llvm/Support/CommandLine.h" 41#include "llvm/Support/ErrorHandling.h" 42#include "llvm/Support/GetElementPtrTypeIterator.h" 43#include "llvm/Target/TargetData.h" 44#include "llvm/Target/TargetInstrInfo.h" 45#include "llvm/Target/TargetLowering.h" 46#include "llvm/Target/TargetMachine.h" 47#include "llvm/Target/TargetOptions.h" 48using namespace llvm; 49 50static cl::opt<bool> 51EnableARMFastISel("arm-fast-isel", 52 cl::desc("Turn on experimental ARM fast-isel support"), 53 cl::init(false), cl::Hidden); 54 55namespace { 56 57class ARMFastISel : public FastISel { 58 59 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 60 /// make the right decision when generating code for different targets. 61 const ARMSubtarget *Subtarget; 62 const TargetMachine &TM; 63 const TargetInstrInfo &TII; 64 const TargetLowering &TLI; 65 ARMFunctionInfo *AFI; 66 67 // Convenience variables to avoid some queries. 68 bool isThumb; 69 LLVMContext *Context; 70 71 public: 72 explicit ARMFastISel(FunctionLoweringInfo &funcInfo) 73 : FastISel(funcInfo), 74 TM(funcInfo.MF->getTarget()), 75 TII(*TM.getInstrInfo()), 76 TLI(*TM.getTargetLowering()) { 77 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 78 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>(); 79 isThumb = AFI->isThumbFunction(); 80 Context = &funcInfo.Fn->getContext(); 81 } 82 83 // Code from FastISel.cpp. 84 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode, 85 const TargetRegisterClass *RC); 86 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode, 87 const TargetRegisterClass *RC, 88 unsigned Op0, bool Op0IsKill); 89 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 90 const TargetRegisterClass *RC, 91 unsigned Op0, bool Op0IsKill, 92 unsigned Op1, bool Op1IsKill); 93 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 94 const TargetRegisterClass *RC, 95 unsigned Op0, bool Op0IsKill, 96 uint64_t Imm); 97 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode, 98 const TargetRegisterClass *RC, 99 unsigned Op0, bool Op0IsKill, 100 const ConstantFP *FPImm); 101 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode, 102 const TargetRegisterClass *RC, 103 uint64_t Imm); 104 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode, 105 const TargetRegisterClass *RC, 106 unsigned Op0, bool Op0IsKill, 107 unsigned Op1, bool Op1IsKill, 108 uint64_t Imm); 109 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT, 110 unsigned Op0, bool Op0IsKill, 111 uint32_t Idx); 112 113 // Backend specific FastISel code. 114 virtual bool TargetSelectInstruction(const Instruction *I); 115 virtual unsigned TargetMaterializeConstant(const Constant *C); 116 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI); 117 118 #include "ARMGenFastISel.inc" 119 120 // Instruction selection routines. 121 private: 122 virtual bool SelectLoad(const Instruction *I); 123 virtual bool SelectStore(const Instruction *I); 124 virtual bool SelectBranch(const Instruction *I); 125 virtual bool SelectCmp(const Instruction *I); 126 virtual bool SelectFPExt(const Instruction *I); 127 virtual bool SelectFPTrunc(const Instruction *I); 128 virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode); 129 virtual bool SelectSIToFP(const Instruction *I); 130 virtual bool SelectFPToSI(const Instruction *I); 131 virtual bool SelectSDiv(const Instruction *I); 132 virtual bool SelectSRem(const Instruction *I); 133 virtual bool SelectCall(const Instruction *I); 134 virtual bool SelectSelect(const Instruction *I); 135 136 // Utility routines. 137 private: 138 bool isTypeLegal(const Type *Ty, EVT &VT); 139 bool isLoadTypeLegal(const Type *Ty, EVT &VT); 140 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset); 141 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset); 142 bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset); 143 void ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT); 144 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT); 145 unsigned ARMMaterializeInt(const Constant *C, EVT VT); 146 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT); 147 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg); 148 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg); 149 150 // Call handling routines. 151 private: 152 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 153 unsigned &ResultReg); 154 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return); 155 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args, 156 SmallVectorImpl<unsigned> &ArgRegs, 157 SmallVectorImpl<EVT> &ArgVTs, 158 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 159 SmallVectorImpl<unsigned> &RegArgs, 160 CallingConv::ID CC, 161 unsigned &NumBytes); 162 bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 163 const Instruction *I, CallingConv::ID CC, 164 unsigned &NumBytes); 165 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call); 166 167 // OptionalDef handling routines. 168 private: 169 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); 170 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 171}; 172 173} // end anonymous namespace 174 175#include "ARMGenCallingConv.inc" 176 177// DefinesOptionalPredicate - This is different from DefinesPredicate in that 178// we don't care about implicit defs here, just places we'll need to add a 179// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR. 180bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { 181 const TargetInstrDesc &TID = MI->getDesc(); 182 if (!TID.hasOptionalDef()) 183 return false; 184 185 // Look to see if our OptionalDef is defining CPSR or CCR. 186 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 187 const MachineOperand &MO = MI->getOperand(i); 188 if (!MO.isReg() || !MO.isDef()) continue; 189 if (MO.getReg() == ARM::CPSR) 190 *CPSR = true; 191 } 192 return true; 193} 194 195// If the machine is predicable go ahead and add the predicate operands, if 196// it needs default CC operands add those. 197const MachineInstrBuilder & 198ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { 199 MachineInstr *MI = &*MIB; 200 201 // Do we use a predicate? 202 if (TII.isPredicable(MI)) 203 AddDefaultPred(MIB); 204 205 // Do we optionally set a predicate? Preds is size > 0 iff the predicate 206 // defines CPSR. All other OptionalDefines in ARM are the CCR register. 207 bool CPSR = false; 208 if (DefinesOptionalPredicate(MI, &CPSR)) { 209 if (CPSR) 210 AddDefaultT1CC(MIB); 211 else 212 AddDefaultCC(MIB); 213 } 214 return MIB; 215} 216 217unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode, 218 const TargetRegisterClass* RC) { 219 unsigned ResultReg = createResultReg(RC); 220 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 221 222 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)); 223 return ResultReg; 224} 225 226unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode, 227 const TargetRegisterClass *RC, 228 unsigned Op0, bool Op0IsKill) { 229 unsigned ResultReg = createResultReg(RC); 230 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 231 232 if (II.getNumDefs() >= 1) 233 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 234 .addReg(Op0, Op0IsKill * RegState::Kill)); 235 else { 236 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 237 .addReg(Op0, Op0IsKill * RegState::Kill)); 238 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 239 TII.get(TargetOpcode::COPY), ResultReg) 240 .addReg(II.ImplicitDefs[0])); 241 } 242 return ResultReg; 243} 244 245unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 246 const TargetRegisterClass *RC, 247 unsigned Op0, bool Op0IsKill, 248 unsigned Op1, bool Op1IsKill) { 249 unsigned ResultReg = createResultReg(RC); 250 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 251 252 if (II.getNumDefs() >= 1) 253 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 254 .addReg(Op0, Op0IsKill * RegState::Kill) 255 .addReg(Op1, Op1IsKill * RegState::Kill)); 256 else { 257 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 258 .addReg(Op0, Op0IsKill * RegState::Kill) 259 .addReg(Op1, Op1IsKill * RegState::Kill)); 260 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 261 TII.get(TargetOpcode::COPY), ResultReg) 262 .addReg(II.ImplicitDefs[0])); 263 } 264 return ResultReg; 265} 266 267unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 268 const TargetRegisterClass *RC, 269 unsigned Op0, bool Op0IsKill, 270 uint64_t Imm) { 271 unsigned ResultReg = createResultReg(RC); 272 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 273 274 if (II.getNumDefs() >= 1) 275 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 276 .addReg(Op0, Op0IsKill * RegState::Kill) 277 .addImm(Imm)); 278 else { 279 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 280 .addReg(Op0, Op0IsKill * RegState::Kill) 281 .addImm(Imm)); 282 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 283 TII.get(TargetOpcode::COPY), ResultReg) 284 .addReg(II.ImplicitDefs[0])); 285 } 286 return ResultReg; 287} 288 289unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 290 const TargetRegisterClass *RC, 291 unsigned Op0, bool Op0IsKill, 292 const ConstantFP *FPImm) { 293 unsigned ResultReg = createResultReg(RC); 294 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 295 296 if (II.getNumDefs() >= 1) 297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 298 .addReg(Op0, Op0IsKill * RegState::Kill) 299 .addFPImm(FPImm)); 300 else { 301 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 302 .addReg(Op0, Op0IsKill * RegState::Kill) 303 .addFPImm(FPImm)); 304 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 305 TII.get(TargetOpcode::COPY), ResultReg) 306 .addReg(II.ImplicitDefs[0])); 307 } 308 return ResultReg; 309} 310 311unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 312 const TargetRegisterClass *RC, 313 unsigned Op0, bool Op0IsKill, 314 unsigned Op1, bool Op1IsKill, 315 uint64_t Imm) { 316 unsigned ResultReg = createResultReg(RC); 317 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 318 319 if (II.getNumDefs() >= 1) 320 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 321 .addReg(Op0, Op0IsKill * RegState::Kill) 322 .addReg(Op1, Op1IsKill * RegState::Kill) 323 .addImm(Imm)); 324 else { 325 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 326 .addReg(Op0, Op0IsKill * RegState::Kill) 327 .addReg(Op1, Op1IsKill * RegState::Kill) 328 .addImm(Imm)); 329 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 330 TII.get(TargetOpcode::COPY), ResultReg) 331 .addReg(II.ImplicitDefs[0])); 332 } 333 return ResultReg; 334} 335 336unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode, 337 const TargetRegisterClass *RC, 338 uint64_t Imm) { 339 unsigned ResultReg = createResultReg(RC); 340 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 341 342 if (II.getNumDefs() >= 1) 343 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 344 .addImm(Imm)); 345 else { 346 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 347 .addImm(Imm)); 348 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 349 TII.get(TargetOpcode::COPY), ResultReg) 350 .addReg(II.ImplicitDefs[0])); 351 } 352 return ResultReg; 353} 354 355unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT, 356 unsigned Op0, bool Op0IsKill, 357 uint32_t Idx) { 358 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 359 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 360 "Cannot yet extract from physregs"); 361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 362 DL, TII.get(TargetOpcode::COPY), ResultReg) 363 .addReg(Op0, getKillRegState(Op0IsKill), Idx)); 364 return ResultReg; 365} 366 367// TODO: Don't worry about 64-bit now, but when this is fixed remove the 368// checks from the various callers. 369unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) { 370 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0; 371 372 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 373 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 374 TII.get(ARM::VMOVRS), MoveReg) 375 .addReg(SrcReg)); 376 return MoveReg; 377} 378 379unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) { 380 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0; 381 382 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 383 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 384 TII.get(ARM::VMOVSR), MoveReg) 385 .addReg(SrcReg)); 386 return MoveReg; 387} 388 389// For double width floating point we need to materialize two constants 390// (the high and the low) into integer registers then use a move to get 391// the combined constant into an FP reg. 392unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) { 393 const APFloat Val = CFP->getValueAPF(); 394 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64; 395 396 // This checks to see if we can use VFP3 instructions to materialize 397 // a constant, otherwise we have to go through the constant pool. 398 if (TLI.isFPImmLegal(Val, VT)) { 399 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS; 400 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 401 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 402 DestReg) 403 .addFPImm(CFP)); 404 return DestReg; 405 } 406 407 // Require VFP2 for loading fp constants. 408 if (!Subtarget->hasVFP2()) return false; 409 410 // MachineConstantPool wants an explicit alignment. 411 unsigned Align = TD.getPrefTypeAlignment(CFP->getType()); 412 if (Align == 0) { 413 // TODO: Figure out if this is correct. 414 Align = TD.getTypeAllocSize(CFP->getType()); 415 } 416 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align); 417 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 418 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; 419 420 // The extra reg is for addrmode5. 421 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 422 DestReg) 423 .addConstantPoolIndex(Idx) 424 .addReg(0)); 425 return DestReg; 426} 427 428unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) { 429 430 // For now 32-bit only. 431 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false; 432 433 // MachineConstantPool wants an explicit alignment. 434 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 435 if (Align == 0) { 436 // TODO: Figure out if this is correct. 437 Align = TD.getTypeAllocSize(C->getType()); 438 } 439 unsigned Idx = MCP.getConstantPoolIndex(C, Align); 440 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 441 442 if (isThumb) 443 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 444 TII.get(ARM::t2LDRpci), DestReg) 445 .addConstantPoolIndex(Idx)); 446 else 447 // The extra reg and immediate are for addrmode2. 448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 449 TII.get(ARM::LDRcp), DestReg) 450 .addConstantPoolIndex(Idx) 451 .addReg(0).addImm(0)); 452 453 return DestReg; 454} 455 456unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) { 457 // For now 32-bit only. 458 if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0; 459 460 Reloc::Model RelocM = TM.getRelocationModel(); 461 462 // TODO: No external globals for now. 463 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0; 464 465 // TODO: Need more magic for ARM PIC. 466 if (!isThumb && (RelocM == Reloc::PIC_)) return 0; 467 468 // MachineConstantPool wants an explicit alignment. 469 unsigned Align = TD.getPrefTypeAlignment(GV->getType()); 470 if (Align == 0) { 471 // TODO: Figure out if this is correct. 472 Align = TD.getTypeAllocSize(GV->getType()); 473 } 474 475 // Grab index. 476 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8); 477 unsigned Id = AFI->createConstPoolEntryUId(); 478 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id, 479 ARMCP::CPValue, PCAdj); 480 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align); 481 482 // Load value. 483 MachineInstrBuilder MIB; 484 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 485 if (isThumb) { 486 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; 487 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 488 .addConstantPoolIndex(Idx); 489 if (RelocM == Reloc::PIC_) 490 MIB.addImm(Id); 491 } else { 492 // The extra reg and immediate are for addrmode2. 493 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp), 494 DestReg) 495 .addConstantPoolIndex(Idx) 496 .addReg(0).addImm(0); 497 } 498 AddOptionalDefs(MIB); 499 return DestReg; 500} 501 502unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { 503 EVT VT = TLI.getValueType(C->getType(), true); 504 505 // Only handle simple types. 506 if (!VT.isSimple()) return 0; 507 508 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 509 return ARMMaterializeFP(CFP, VT); 510 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 511 return ARMMaterializeGV(GV, VT); 512 else if (isa<ConstantInt>(C)) 513 return ARMMaterializeInt(C, VT); 514 515 return 0; 516} 517 518unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) { 519 // Don't handle dynamic allocas. 520 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; 521 522 EVT VT; 523 if (!isLoadTypeLegal(AI->getType(), VT)) return false; 524 525 DenseMap<const AllocaInst*, int>::iterator SI = 526 FuncInfo.StaticAllocaMap.find(AI); 527 528 // This will get lowered later into the correct offsets and registers 529 // via rewriteXFrameIndex. 530 if (SI != FuncInfo.StaticAllocaMap.end()) { 531 TargetRegisterClass* RC = TLI.getRegClassFor(VT); 532 unsigned ResultReg = createResultReg(RC); 533 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; 534 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL, 535 TII.get(Opc), ResultReg) 536 .addFrameIndex(SI->second) 537 .addImm(0)); 538 return ResultReg; 539 } 540 541 return 0; 542} 543 544bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) { 545 VT = TLI.getValueType(Ty, true); 546 547 // Only handle simple types. 548 if (VT == MVT::Other || !VT.isSimple()) return false; 549 550 // Handle all legal types, i.e. a register that will directly hold this 551 // value. 552 return TLI.isTypeLegal(VT); 553} 554 555bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) { 556 if (isTypeLegal(Ty, VT)) return true; 557 558 // If this is a type than can be sign or zero-extended to a basic operation 559 // go ahead and accept it now. 560 if (VT == MVT::i8 || VT == MVT::i16) 561 return true; 562 563 return false; 564} 565 566// Computes the Reg+Offset to get to an object. 567bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base, 568 int &Offset) { 569 // Some boilerplate from the X86 FastISel. 570 const User *U = NULL; 571 unsigned Opcode = Instruction::UserOp1; 572 if (const Instruction *I = dyn_cast<Instruction>(Obj)) { 573 // Don't walk into other basic blocks; it's possible we haven't 574 // visited them yet, so the instructions may not yet be assigned 575 // virtual registers. 576 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB) 577 return false; 578 Opcode = I->getOpcode(); 579 U = I; 580 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) { 581 Opcode = C->getOpcode(); 582 U = C; 583 } 584 585 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType())) 586 if (Ty->getAddressSpace() > 255) 587 // Fast instruction selection doesn't support the special 588 // address spaces. 589 return false; 590 591 switch (Opcode) { 592 default: 593 break; 594 case Instruction::BitCast: { 595 // Look through bitcasts. 596 return ARMComputeRegOffset(U->getOperand(0), Base, Offset); 597 } 598 case Instruction::IntToPtr: { 599 // Look past no-op inttoptrs. 600 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 601 return ARMComputeRegOffset(U->getOperand(0), Base, Offset); 602 break; 603 } 604 case Instruction::PtrToInt: { 605 // Look past no-op ptrtoints. 606 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 607 return ARMComputeRegOffset(U->getOperand(0), Base, Offset); 608 break; 609 } 610 case Instruction::GetElementPtr: { 611 int SavedOffset = Offset; 612 unsigned SavedBase = Base; 613 int TmpOffset = Offset; 614 615 // Iterate through the GEP folding the constants into offsets where 616 // we can. 617 gep_type_iterator GTI = gep_type_begin(U); 618 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); 619 i != e; ++i, ++GTI) { 620 const Value *Op = *i; 621 if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 622 const StructLayout *SL = TD.getStructLayout(STy); 623 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 624 TmpOffset += SL->getElementOffset(Idx); 625 } else { 626 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 627 SmallVector<const Value *, 4> Worklist; 628 Worklist.push_back(Op); 629 do { 630 Op = Worklist.pop_back_val(); 631 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 632 // Constant-offset addressing. 633 TmpOffset += CI->getSExtValue() * S; 634 } else if (isa<AddOperator>(Op) && 635 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) { 636 // An add with a constant operand. Fold the constant. 637 ConstantInt *CI = 638 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 639 TmpOffset += CI->getSExtValue() * S; 640 // Add the other operand back to the work list. 641 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0)); 642 } else 643 goto unsupported_gep; 644 } while (!Worklist.empty()); 645 } 646 } 647 648 // Try to grab the base operand now. 649 Offset = TmpOffset; 650 if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true; 651 652 // We failed, restore everything and try the other options. 653 Offset = SavedOffset; 654 Base = SavedBase; 655 656 unsupported_gep: 657 break; 658 } 659 case Instruction::Alloca: { 660 const AllocaInst *AI = cast<AllocaInst>(Obj); 661 unsigned Reg = TargetMaterializeAlloca(AI); 662 663 if (Reg == 0) return false; 664 665 Base = Reg; 666 return true; 667 } 668 } 669 670 // Materialize the global variable's address into a reg which can 671 // then be used later to load the variable. 672 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) { 673 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType())); 674 if (Tmp == 0) return false; 675 676 Base = Tmp; 677 return true; 678 } 679 680 // Try to get this in a register if nothing else has worked. 681 if (Base == 0) Base = getRegForValue(Obj); 682 return Base != 0; 683} 684 685void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) { 686 687 assert (Base != ARM::SP && "How'd we get a stack pointer here?"); 688 689 // Since the offset may be too large for the load instruction 690 // get the reg+offset into a register. 691 if (Offset != 0) { 692 ARMCC::CondCodes Pred = ARMCC::AL; 693 unsigned PredReg = 0; 694 695 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass : 696 ARM::GPRRegisterClass; 697 unsigned BaseReg = createResultReg(RC); 698 699 if (!isThumb) 700 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 701 BaseReg, Base, Offset, Pred, PredReg, 702 static_cast<const ARMBaseInstrInfo&>(TII)); 703 else { 704 assert(AFI->isThumb2Function()); 705 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 706 BaseReg, Base, Offset, Pred, PredReg, 707 static_cast<const ARMBaseInstrInfo&>(TII)); 708 } 709 Offset = 0; 710 Base = BaseReg; 711 } 712} 713 714bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, 715 unsigned Base, int Offset) { 716 717 assert(VT.isSimple() && "Non-simple types are invalid here!"); 718 unsigned Opc; 719 TargetRegisterClass *RC; 720 bool isFloat = false; 721 switch (VT.getSimpleVT().SimpleTy) { 722 default: 723 // This is mostly going to be Neon/vector support. 724 return false; 725 case MVT::i16: 726 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH; 727 RC = ARM::GPRRegisterClass; 728 VT = MVT::i32; 729 break; 730 case MVT::i8: 731 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRB; 732 RC = ARM::GPRRegisterClass; 733 VT = MVT::i32; 734 break; 735 case MVT::i32: 736 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDR; 737 RC = ARM::GPRRegisterClass; 738 break; 739 case MVT::f32: 740 Opc = ARM::VLDRS; 741 RC = TLI.getRegClassFor(VT); 742 isFloat = true; 743 break; 744 case MVT::f64: 745 Opc = ARM::VLDRD; 746 RC = TLI.getRegClassFor(VT); 747 isFloat = true; 748 break; 749 } 750 751 ResultReg = createResultReg(RC); 752 753 // All SP loads should already have been lowered to another reg. 754 assert(Base != ARM::SP && "No stack stores this late!"); 755 756 // For now with the additions above the offset should be zero - thus we 757 // can always fit into an i12. 758 assert(Offset == 0 && "Offset should be zero at this point!"); 759 760 // The thumb and floating point instructions both take 2 operands, ARM takes 761 // another register. 762 if (isFloat || isThumb) 763 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 764 TII.get(Opc), ResultReg) 765 .addReg(Base).addImm(Offset)); 766 else 767 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 768 TII.get(Opc), ResultReg) 769 .addReg(Base).addReg(0).addImm(Offset)); 770 return true; 771} 772 773bool ARMFastISel::SelectLoad(const Instruction *I) { 774 // Verify we have a legal type before going any further. 775 EVT VT; 776 if (!isLoadTypeLegal(I->getType(), VT)) 777 return false; 778 779 // Our register and offset with innocuous defaults. 780 unsigned Base = 0; 781 int Offset = 0; 782 783 // See if we can handle this as Reg + Offset 784 if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset)) 785 return false; 786 787 ARMSimplifyRegOffset(Base, Offset, VT); 788 789 unsigned ResultReg; 790 if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false; 791 792 UpdateValueMap(I, ResultReg); 793 return true; 794} 795 796bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, 797 unsigned Base, int Offset) { 798 unsigned StrOpc; 799 bool isFloat = false; 800 // VT is set here only for use in the alloca stores below - those are promoted 801 // to reg size always. 802 switch (VT.getSimpleVT().SimpleTy) { 803 default: return false; 804 case MVT::i1: 805 case MVT::i8: 806 VT = MVT::i32; 807 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRB; 808 break; 809 case MVT::i16: 810 VT = MVT::i32; 811 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH; 812 break; 813 case MVT::i32: 814 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STR; 815 break; 816 case MVT::f32: 817 if (!Subtarget->hasVFP2()) return false; 818 StrOpc = ARM::VSTRS; 819 isFloat = true; 820 break; 821 case MVT::f64: 822 if (!Subtarget->hasVFP2()) return false; 823 StrOpc = ARM::VSTRD; 824 isFloat = true; 825 break; 826 } 827 828 // All SP stores should already have been lowered to another reg. 829 assert(Base != ARM::SP && "No stack stores this late!"); 830 831 // For now with the additions above the offset should be zero - thus we 832 // can always fit into an i12. 833 assert(Offset == 0 && "Offset should be zero at this point!"); 834 835 // The thumb addressing mode has operands swapped from the arm addressing 836 // mode, the floating point one only has two operands. 837 if (isFloat || isThumb) 838 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 839 TII.get(StrOpc)) 840 .addReg(SrcReg).addReg(Base).addImm(Offset)); 841 else 842 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 843 TII.get(StrOpc)) 844 .addReg(SrcReg).addReg(Base).addReg(0).addImm(Offset)); 845 846 return true; 847} 848 849bool ARMFastISel::SelectStore(const Instruction *I) { 850 Value *Op0 = I->getOperand(0); 851 unsigned SrcReg = 0; 852 853 // Yay type legalization 854 EVT VT; 855 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) 856 return false; 857 858 // Get the value to be stored into a register. 859 SrcReg = getRegForValue(Op0); 860 if (SrcReg == 0) 861 return false; 862 863 // Our register and offset with innocuous defaults. 864 unsigned Base = 0; 865 int Offset = 0; 866 867 // See if we can handle this as Reg + Offset 868 if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset)) 869 return false; 870 871 ARMSimplifyRegOffset(Base, Offset, VT); 872 873 if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false; 874 875 return true; 876} 877 878static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) { 879 switch (Pred) { 880 // Needs two compares... 881 case CmpInst::FCMP_ONE: 882 case CmpInst::FCMP_UEQ: 883 default: 884 assert(false && "Unhandled CmpInst::Predicate!"); 885 return ARMCC::AL; 886 case CmpInst::ICMP_EQ: 887 case CmpInst::FCMP_OEQ: 888 return ARMCC::EQ; 889 case CmpInst::ICMP_SGT: 890 case CmpInst::FCMP_OGT: 891 return ARMCC::GT; 892 case CmpInst::ICMP_SGE: 893 case CmpInst::FCMP_OGE: 894 return ARMCC::GE; 895 case CmpInst::ICMP_UGT: 896 case CmpInst::FCMP_UGT: 897 return ARMCC::HI; 898 case CmpInst::FCMP_OLT: 899 return ARMCC::MI; 900 case CmpInst::ICMP_ULE: 901 case CmpInst::FCMP_OLE: 902 return ARMCC::LS; 903 case CmpInst::FCMP_ORD: 904 return ARMCC::VC; 905 case CmpInst::FCMP_UNO: 906 return ARMCC::VS; 907 case CmpInst::FCMP_UGE: 908 return ARMCC::PL; 909 case CmpInst::ICMP_SLT: 910 case CmpInst::FCMP_ULT: 911 return ARMCC::LT; 912 case CmpInst::ICMP_SLE: 913 case CmpInst::FCMP_ULE: 914 return ARMCC::LE; 915 case CmpInst::FCMP_UNE: 916 case CmpInst::ICMP_NE: 917 return ARMCC::NE; 918 case CmpInst::ICMP_UGE: 919 return ARMCC::HS; 920 case CmpInst::ICMP_ULT: 921 return ARMCC::LO; 922 } 923} 924 925bool ARMFastISel::SelectBranch(const Instruction *I) { 926 const BranchInst *BI = cast<BranchInst>(I); 927 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 928 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 929 930 // Simple branch support. 931 // TODO: Try to avoid the re-computation in some places. 932 unsigned CondReg = getRegForValue(BI->getCondition()); 933 if (CondReg == 0) return false; 934 935 // Re-set the flags just in case. 936 unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri; 937 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) 938 .addReg(CondReg).addImm(1)); 939 940 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; 941 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) 942 .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 943 FastEmitBranch(FBB, DL); 944 FuncInfo.MBB->addSuccessor(TBB); 945 return true; 946} 947 948bool ARMFastISel::SelectCmp(const Instruction *I) { 949 const CmpInst *CI = cast<CmpInst>(I); 950 951 EVT VT; 952 const Type *Ty = CI->getOperand(0)->getType(); 953 if (!isTypeLegal(Ty, VT)) 954 return false; 955 956 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); 957 if (isFloat && !Subtarget->hasVFP2()) 958 return false; 959 960 unsigned CmpOpc; 961 unsigned CondReg; 962 switch (VT.getSimpleVT().SimpleTy) { 963 default: return false; 964 // TODO: Verify compares. 965 case MVT::f32: 966 CmpOpc = ARM::VCMPES; 967 CondReg = ARM::FPSCR; 968 break; 969 case MVT::f64: 970 CmpOpc = ARM::VCMPED; 971 CondReg = ARM::FPSCR; 972 break; 973 case MVT::i32: 974 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; 975 CondReg = ARM::CPSR; 976 break; 977 } 978 979 // Get the compare predicate. 980 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate()); 981 982 // We may not handle every CC for now. 983 if (ARMPred == ARMCC::AL) return false; 984 985 unsigned Arg1 = getRegForValue(CI->getOperand(0)); 986 if (Arg1 == 0) return false; 987 988 unsigned Arg2 = getRegForValue(CI->getOperand(1)); 989 if (Arg2 == 0) return false; 990 991 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) 992 .addReg(Arg1).addReg(Arg2)); 993 994 // For floating point we need to move the result to a comparison register 995 // that we can then use for branches. 996 if (isFloat) 997 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 998 TII.get(ARM::FMSTAT))); 999 1000 // Now set a register based on the comparison. Explicitly set the predicates 1001 // here. 1002 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi; 1003 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass 1004 : ARM::GPRRegisterClass; 1005 unsigned DestReg = createResultReg(RC); 1006 Constant *Zero 1007 = ConstantInt::get(Type::getInt32Ty(*Context), 0); 1008 unsigned ZeroReg = TargetMaterializeConstant(Zero); 1009 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg) 1010 .addReg(ZeroReg).addImm(1) 1011 .addImm(ARMPred).addReg(CondReg); 1012 1013 UpdateValueMap(I, DestReg); 1014 return true; 1015} 1016 1017bool ARMFastISel::SelectFPExt(const Instruction *I) { 1018 // Make sure we have VFP and that we're extending float to double. 1019 if (!Subtarget->hasVFP2()) return false; 1020 1021 Value *V = I->getOperand(0); 1022 if (!I->getType()->isDoubleTy() || 1023 !V->getType()->isFloatTy()) return false; 1024 1025 unsigned Op = getRegForValue(V); 1026 if (Op == 0) return false; 1027 1028 unsigned Result = createResultReg(ARM::DPRRegisterClass); 1029 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1030 TII.get(ARM::VCVTDS), Result) 1031 .addReg(Op)); 1032 UpdateValueMap(I, Result); 1033 return true; 1034} 1035 1036bool ARMFastISel::SelectFPTrunc(const Instruction *I) { 1037 // Make sure we have VFP and that we're truncating double to float. 1038 if (!Subtarget->hasVFP2()) return false; 1039 1040 Value *V = I->getOperand(0); 1041 if (!(I->getType()->isFloatTy() && 1042 V->getType()->isDoubleTy())) return false; 1043 1044 unsigned Op = getRegForValue(V); 1045 if (Op == 0) return false; 1046 1047 unsigned Result = createResultReg(ARM::SPRRegisterClass); 1048 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1049 TII.get(ARM::VCVTSD), Result) 1050 .addReg(Op)); 1051 UpdateValueMap(I, Result); 1052 return true; 1053} 1054 1055bool ARMFastISel::SelectSIToFP(const Instruction *I) { 1056 // Make sure we have VFP. 1057 if (!Subtarget->hasVFP2()) return false; 1058 1059 EVT DstVT; 1060 const Type *Ty = I->getType(); 1061 if (!isTypeLegal(Ty, DstVT)) 1062 return false; 1063 1064 unsigned Op = getRegForValue(I->getOperand(0)); 1065 if (Op == 0) return false; 1066 1067 // The conversion routine works on fp-reg to fp-reg and the operand above 1068 // was an integer, move it to the fp registers if possible. 1069 unsigned FP = ARMMoveToFPReg(MVT::f32, Op); 1070 if (FP == 0) return false; 1071 1072 unsigned Opc; 1073 if (Ty->isFloatTy()) Opc = ARM::VSITOS; 1074 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD; 1075 else return 0; 1076 1077 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); 1078 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 1079 ResultReg) 1080 .addReg(FP)); 1081 UpdateValueMap(I, ResultReg); 1082 return true; 1083} 1084 1085bool ARMFastISel::SelectFPToSI(const Instruction *I) { 1086 // Make sure we have VFP. 1087 if (!Subtarget->hasVFP2()) return false; 1088 1089 EVT DstVT; 1090 const Type *RetTy = I->getType(); 1091 if (!isTypeLegal(RetTy, DstVT)) 1092 return false; 1093 1094 unsigned Op = getRegForValue(I->getOperand(0)); 1095 if (Op == 0) return false; 1096 1097 unsigned Opc; 1098 const Type *OpTy = I->getOperand(0)->getType(); 1099 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS; 1100 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD; 1101 else return 0; 1102 1103 // f64->s32 or f32->s32 both need an intermediate f32 reg. 1104 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); 1105 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 1106 ResultReg) 1107 .addReg(Op)); 1108 1109 // This result needs to be in an integer register, but the conversion only 1110 // takes place in fp-regs. 1111 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); 1112 if (IntReg == 0) return false; 1113 1114 UpdateValueMap(I, IntReg); 1115 return true; 1116} 1117 1118bool ARMFastISel::SelectSelect(const Instruction *I) { 1119 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1120 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1121 return false; 1122 1123 // Things need to be register sized for register moves. 1124 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false; 1125 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 1126 1127 unsigned CondReg = getRegForValue(I->getOperand(0)); 1128 if (CondReg == 0) return false; 1129 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1130 if (Op1Reg == 0) return false; 1131 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1132 if (Op2Reg == 0) return false; 1133 1134 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri; 1135 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) 1136 .addReg(CondReg).addImm(1)); 1137 unsigned ResultReg = createResultReg(RC); 1138 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr; 1139 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg) 1140 .addReg(Op1Reg).addReg(Op2Reg) 1141 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 1142 UpdateValueMap(I, ResultReg); 1143 return true; 1144} 1145 1146bool ARMFastISel::SelectSDiv(const Instruction *I) { 1147 EVT VT; 1148 const Type *Ty = I->getType(); 1149 if (!isTypeLegal(Ty, VT)) 1150 return false; 1151 1152 // If we have integer div support we should have selected this automagically. 1153 // In case we have a real miss go ahead and return false and we'll pick 1154 // it up later. 1155 if (Subtarget->hasDivide()) return false; 1156 1157 // Otherwise emit a libcall. 1158 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1159 if (VT == MVT::i8) 1160 LC = RTLIB::SDIV_I8; 1161 else if (VT == MVT::i16) 1162 LC = RTLIB::SDIV_I16; 1163 else if (VT == MVT::i32) 1164 LC = RTLIB::SDIV_I32; 1165 else if (VT == MVT::i64) 1166 LC = RTLIB::SDIV_I64; 1167 else if (VT == MVT::i128) 1168 LC = RTLIB::SDIV_I128; 1169 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1170 1171 return ARMEmitLibcall(I, LC); 1172} 1173 1174bool ARMFastISel::SelectSRem(const Instruction *I) { 1175 EVT VT; 1176 const Type *Ty = I->getType(); 1177 if (!isTypeLegal(Ty, VT)) 1178 return false; 1179 1180 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1181 if (VT == MVT::i8) 1182 LC = RTLIB::SREM_I8; 1183 else if (VT == MVT::i16) 1184 LC = RTLIB::SREM_I16; 1185 else if (VT == MVT::i32) 1186 LC = RTLIB::SREM_I32; 1187 else if (VT == MVT::i64) 1188 LC = RTLIB::SREM_I64; 1189 else if (VT == MVT::i128) 1190 LC = RTLIB::SREM_I128; 1191 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1192 1193 return ARMEmitLibcall(I, LC); 1194} 1195 1196bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) { 1197 EVT VT = TLI.getValueType(I->getType(), true); 1198 1199 // We can get here in the case when we want to use NEON for our fp 1200 // operations, but can't figure out how to. Just use the vfp instructions 1201 // if we have them. 1202 // FIXME: It'd be nice to use NEON instructions. 1203 const Type *Ty = I->getType(); 1204 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); 1205 if (isFloat && !Subtarget->hasVFP2()) 1206 return false; 1207 1208 unsigned Op1 = getRegForValue(I->getOperand(0)); 1209 if (Op1 == 0) return false; 1210 1211 unsigned Op2 = getRegForValue(I->getOperand(1)); 1212 if (Op2 == 0) return false; 1213 1214 unsigned Opc; 1215 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 || 1216 VT.getSimpleVT().SimpleTy == MVT::i64; 1217 switch (ISDOpcode) { 1218 default: return false; 1219 case ISD::FADD: 1220 Opc = is64bit ? ARM::VADDD : ARM::VADDS; 1221 break; 1222 case ISD::FSUB: 1223 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; 1224 break; 1225 case ISD::FMUL: 1226 Opc = is64bit ? ARM::VMULD : ARM::VMULS; 1227 break; 1228 } 1229 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1230 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1231 TII.get(Opc), ResultReg) 1232 .addReg(Op1).addReg(Op2)); 1233 UpdateValueMap(I, ResultReg); 1234 return true; 1235} 1236 1237// Call Handling Code 1238 1239bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, 1240 EVT SrcVT, unsigned &ResultReg) { 1241 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 1242 Src, /*TODO: Kill=*/false); 1243 1244 if (RR != 0) { 1245 ResultReg = RR; 1246 return true; 1247 } else 1248 return false; 1249} 1250 1251// This is largely taken directly from CCAssignFnForNode - we don't support 1252// varargs in FastISel so that part has been removed. 1253// TODO: We may not support all of this. 1254CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) { 1255 switch (CC) { 1256 default: 1257 llvm_unreachable("Unsupported calling convention"); 1258 case CallingConv::C: 1259 case CallingConv::Fast: 1260 // Use target triple & subtarget features to do actual dispatch. 1261 if (Subtarget->isAAPCS_ABI()) { 1262 if (Subtarget->hasVFP2() && 1263 FloatABIType == FloatABI::Hard) 1264 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 1265 else 1266 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 1267 } else 1268 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 1269 case CallingConv::ARM_AAPCS_VFP: 1270 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 1271 case CallingConv::ARM_AAPCS: 1272 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 1273 case CallingConv::ARM_APCS: 1274 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 1275 } 1276} 1277 1278bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args, 1279 SmallVectorImpl<unsigned> &ArgRegs, 1280 SmallVectorImpl<EVT> &ArgVTs, 1281 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 1282 SmallVectorImpl<unsigned> &RegArgs, 1283 CallingConv::ID CC, 1284 unsigned &NumBytes) { 1285 SmallVector<CCValAssign, 16> ArgLocs; 1286 CCState CCInfo(CC, false, TM, ArgLocs, *Context); 1287 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false)); 1288 1289 // Get a count of how many bytes are to be pushed on the stack. 1290 NumBytes = CCInfo.getNextStackOffset(); 1291 1292 // Issue CALLSEQ_START 1293 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 1294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1295 TII.get(AdjStackDown)) 1296 .addImm(NumBytes)); 1297 1298 // Process the args. 1299 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1300 CCValAssign &VA = ArgLocs[i]; 1301 unsigned Arg = ArgRegs[VA.getValNo()]; 1302 EVT ArgVT = ArgVTs[VA.getValNo()]; 1303 1304 // Handle arg promotion, etc. 1305 switch (VA.getLocInfo()) { 1306 case CCValAssign::Full: break; 1307 case CCValAssign::SExt: { 1308 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1309 Arg, ArgVT, Arg); 1310 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 1311 Emitted = true; 1312 ArgVT = VA.getLocVT(); 1313 break; 1314 } 1315 case CCValAssign::ZExt: { 1316 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1317 Arg, ArgVT, Arg); 1318 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 1319 Emitted = true; 1320 ArgVT = VA.getLocVT(); 1321 break; 1322 } 1323 case CCValAssign::AExt: { 1324 // We don't handle NEON or f64 parameters yet. 1325 if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() >= 64) 1326 return false; 1327 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1328 Arg, ArgVT, Arg); 1329 if (!Emitted) 1330 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1331 Arg, ArgVT, Arg); 1332 if (!Emitted) 1333 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1334 Arg, ArgVT, Arg); 1335 1336 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 1337 ArgVT = VA.getLocVT(); 1338 break; 1339 } 1340 case CCValAssign::BCvt: { 1341 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), 1342 VA.getLocVT().getSimpleVT(), 1343 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false); 1344 assert(BC != 0 && "Failed to emit a bitcast!"); 1345 Arg = BC; 1346 ArgVT = VA.getLocVT(); 1347 break; 1348 } 1349 default: llvm_unreachable("Unknown arg promotion!"); 1350 } 1351 1352 // Now copy/store arg to correct locations. 1353 // TODO: We need custom lowering for f64 args. 1354 if (VA.isRegLoc() && !VA.needsCustom()) { 1355 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1356 VA.getLocReg()) 1357 .addReg(Arg); 1358 RegArgs.push_back(VA.getLocReg()); 1359 } else { 1360 // Need to store 1361 return false; 1362 } 1363 } 1364 1365 return true; 1366} 1367 1368bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 1369 const Instruction *I, CallingConv::ID CC, 1370 unsigned &NumBytes) { 1371 // Issue CALLSEQ_END 1372 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 1373 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1374 TII.get(AdjStackUp)) 1375 .addImm(NumBytes).addImm(0)); 1376 1377 // Now the return value. 1378 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { 1379 SmallVector<CCValAssign, 16> RVLocs; 1380 CCState CCInfo(CC, false, TM, RVLocs, *Context); 1381 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true)); 1382 1383 // Copy all of the result registers out of their specified physreg. 1384 if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) { 1385 // For this move we copy into two registers and then move into the 1386 // double fp reg we want. 1387 // TODO: Are the copies necessary? 1388 TargetRegisterClass *CopyRC = TLI.getRegClassFor(MVT::i32); 1389 unsigned Copy1 = createResultReg(CopyRC); 1390 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1391 Copy1).addReg(RVLocs[0].getLocReg()); 1392 UsedRegs.push_back(RVLocs[0].getLocReg()); 1393 1394 unsigned Copy2 = createResultReg(CopyRC); 1395 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1396 Copy2).addReg(RVLocs[1].getLocReg()); 1397 UsedRegs.push_back(RVLocs[1].getLocReg()); 1398 1399 EVT DestVT = RVLocs[0].getValVT(); 1400 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); 1401 unsigned ResultReg = createResultReg(DstRC); 1402 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1403 TII.get(ARM::VMOVDRR), ResultReg) 1404 .addReg(Copy1).addReg(Copy2)); 1405 1406 // Finally update the result. 1407 UpdateValueMap(I, ResultReg); 1408 } else { 1409 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); 1410 EVT CopyVT = RVLocs[0].getValVT(); 1411 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1412 1413 unsigned ResultReg = createResultReg(DstRC); 1414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1415 ResultReg).addReg(RVLocs[0].getLocReg()); 1416 UsedRegs.push_back(RVLocs[0].getLocReg()); 1417 1418 // Finally update the result. 1419 UpdateValueMap(I, ResultReg); 1420 } 1421 } 1422 1423 return true; 1424} 1425 1426// A quick function that will emit a call for a named libcall in F with the 1427// vector of passed arguments for the Instruction in I. We can assume that we 1428// can emit a call for any libcall we can produce. This is an abridged version 1429// of the full call infrastructure since we won't need to worry about things 1430// like computed function pointers or strange arguments at call sites. 1431// TODO: Try to unify this and the normal call bits for ARM, then try to unify 1432// with X86. 1433bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) { 1434 CallingConv::ID CC = TLI.getLibcallCallingConv(Call); 1435 1436 // Handle *simple* calls for now. 1437 const Type *RetTy = I->getType(); 1438 EVT RetVT; 1439 if (RetTy->isVoidTy()) 1440 RetVT = MVT::isVoid; 1441 else if (!isTypeLegal(RetTy, RetVT)) 1442 return false; 1443 1444 // For now we're using BLX etc on the assumption that we have v5t ops. 1445 if (!Subtarget->hasV5TOps()) return false; 1446 1447 // Set up the argument vectors. 1448 SmallVector<Value*, 8> Args; 1449 SmallVector<unsigned, 8> ArgRegs; 1450 SmallVector<EVT, 8> ArgVTs; 1451 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1452 Args.reserve(I->getNumOperands()); 1453 ArgRegs.reserve(I->getNumOperands()); 1454 ArgVTs.reserve(I->getNumOperands()); 1455 ArgFlags.reserve(I->getNumOperands()); 1456 for (unsigned i = 0; i < I->getNumOperands(); ++i) { 1457 Value *Op = I->getOperand(i); 1458 unsigned Arg = getRegForValue(Op); 1459 if (Arg == 0) return false; 1460 1461 const Type *ArgTy = Op->getType(); 1462 EVT ArgVT; 1463 if (!isTypeLegal(ArgTy, ArgVT)) return false; 1464 1465 ISD::ArgFlagsTy Flags; 1466 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1467 Flags.setOrigAlign(OriginalAlignment); 1468 1469 Args.push_back(Op); 1470 ArgRegs.push_back(Arg); 1471 ArgVTs.push_back(ArgVT); 1472 ArgFlags.push_back(Flags); 1473 } 1474 1475 // Handle the arguments now that we've gotten them. 1476 SmallVector<unsigned, 4> RegArgs; 1477 unsigned NumBytes; 1478 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) 1479 return false; 1480 1481 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops. 1482 // TODO: Turn this into the table of arm call ops. 1483 MachineInstrBuilder MIB; 1484 unsigned CallOpc; 1485 if(isThumb) 1486 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi; 1487 else 1488 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL; 1489 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) 1490 .addExternalSymbol(TLI.getLibcallName(Call)); 1491 1492 // Add implicit physical register uses to the call. 1493 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1494 MIB.addReg(RegArgs[i]); 1495 1496 // Finish off the call including any return values. 1497 SmallVector<unsigned, 4> UsedRegs; 1498 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false; 1499 1500 // Set all unused physreg defs as dead. 1501 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 1502 1503 return true; 1504} 1505 1506bool ARMFastISel::SelectCall(const Instruction *I) { 1507 const CallInst *CI = cast<CallInst>(I); 1508 const Value *Callee = CI->getCalledValue(); 1509 1510 // Can't handle inline asm or worry about intrinsics yet. 1511 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false; 1512 1513 // Only handle global variable Callees that are direct calls. 1514 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee); 1515 if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel())) 1516 return false; 1517 1518 // Check the calling convention. 1519 ImmutableCallSite CS(CI); 1520 CallingConv::ID CC = CS.getCallingConv(); 1521 // TODO: Avoid some calling conventions? 1522 if (CC != CallingConv::C) { 1523 // errs() << "Can't handle calling convention: " << CC << "\n"; 1524 return false; 1525 } 1526 1527 // Let SDISel handle vararg functions. 1528 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1529 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1530 if (FTy->isVarArg()) 1531 return false; 1532 1533 // Handle *simple* calls for now. 1534 const Type *RetTy = I->getType(); 1535 EVT RetVT; 1536 if (RetTy->isVoidTy()) 1537 RetVT = MVT::isVoid; 1538 else if (!isTypeLegal(RetTy, RetVT)) 1539 return false; 1540 1541 // For now we're using BLX etc on the assumption that we have v5t ops. 1542 // TODO: Maybe? 1543 if (!Subtarget->hasV5TOps()) return false; 1544 1545 // Set up the argument vectors. 1546 SmallVector<Value*, 8> Args; 1547 SmallVector<unsigned, 8> ArgRegs; 1548 SmallVector<EVT, 8> ArgVTs; 1549 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1550 Args.reserve(CS.arg_size()); 1551 ArgRegs.reserve(CS.arg_size()); 1552 ArgVTs.reserve(CS.arg_size()); 1553 ArgFlags.reserve(CS.arg_size()); 1554 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1555 i != e; ++i) { 1556 unsigned Arg = getRegForValue(*i); 1557 1558 if (Arg == 0) 1559 return false; 1560 ISD::ArgFlagsTy Flags; 1561 unsigned AttrInd = i - CS.arg_begin() + 1; 1562 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1563 Flags.setSExt(); 1564 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1565 Flags.setZExt(); 1566 1567 // FIXME: Only handle *easy* calls for now. 1568 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1569 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1570 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1571 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1572 return false; 1573 1574 const Type *ArgTy = (*i)->getType(); 1575 EVT ArgVT; 1576 if (!isTypeLegal(ArgTy, ArgVT)) 1577 return false; 1578 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1579 Flags.setOrigAlign(OriginalAlignment); 1580 1581 Args.push_back(*i); 1582 ArgRegs.push_back(Arg); 1583 ArgVTs.push_back(ArgVT); 1584 ArgFlags.push_back(Flags); 1585 } 1586 1587 // Handle the arguments now that we've gotten them. 1588 SmallVector<unsigned, 4> RegArgs; 1589 unsigned NumBytes; 1590 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) 1591 return false; 1592 1593 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops. 1594 // TODO: Turn this into the table of arm call ops. 1595 MachineInstrBuilder MIB; 1596 unsigned CallOpc; 1597 if(isThumb) 1598 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi; 1599 else 1600 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL; 1601 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) 1602 .addGlobalAddress(GV, 0, 0); 1603 1604 // Add implicit physical register uses to the call. 1605 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1606 MIB.addReg(RegArgs[i]); 1607 1608 // Finish off the call including any return values. 1609 SmallVector<unsigned, 4> UsedRegs; 1610 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false; 1611 1612 // Set all unused physreg defs as dead. 1613 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 1614 1615 return true; 1616 1617} 1618 1619// TODO: SoftFP support. 1620bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { 1621 // No Thumb-1 for now. 1622 if (isThumb && !AFI->isThumb2Function()) return false; 1623 1624 switch (I->getOpcode()) { 1625 case Instruction::Load: 1626 return SelectLoad(I); 1627 case Instruction::Store: 1628 return SelectStore(I); 1629 case Instruction::Br: 1630 return SelectBranch(I); 1631 case Instruction::ICmp: 1632 case Instruction::FCmp: 1633 return SelectCmp(I); 1634 case Instruction::FPExt: 1635 return SelectFPExt(I); 1636 case Instruction::FPTrunc: 1637 return SelectFPTrunc(I); 1638 case Instruction::SIToFP: 1639 return SelectSIToFP(I); 1640 case Instruction::FPToSI: 1641 return SelectFPToSI(I); 1642 case Instruction::FAdd: 1643 return SelectBinaryOp(I, ISD::FADD); 1644 case Instruction::FSub: 1645 return SelectBinaryOp(I, ISD::FSUB); 1646 case Instruction::FMul: 1647 return SelectBinaryOp(I, ISD::FMUL); 1648 case Instruction::SDiv: 1649 return SelectSDiv(I); 1650 case Instruction::SRem: 1651 return SelectSRem(I); 1652 case Instruction::Call: 1653 return SelectCall(I); 1654 case Instruction::Select: 1655 return SelectSelect(I); 1656 default: break; 1657 } 1658 return false; 1659} 1660 1661namespace llvm { 1662 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { 1663 // Completely untested on non-darwin. 1664 const TargetMachine &TM = funcInfo.MF->getTarget(); 1665 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>(); 1666 if (Subtarget->isTargetDarwin() && EnableARMFastISel) 1667 return new ARMFastISel(funcInfo); 1668 return 0; 1669 } 1670} 1671