ARMMCCodeEmitter.cpp revision 08fef885eb39339a47e3be7f0842b1db33683003
1568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 3568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// The LLVM Compiler Infrastructure 4568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 5568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// This file is distributed under the University of Illinois Open Source 6568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// License. See LICENSE.TXT for details. 7568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 8568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach//===----------------------------------------------------------------------===// 9568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 10568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// This file implements the ARMMCCodeEmitter class. 11568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 12568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach//===----------------------------------------------------------------------===// 13568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 142ac190238e88b21e716e2853900b5076c9013410Chris Lattner#define DEBUG_TYPE "mccodeemitter" 15ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 16be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "MCTargetDesc/ARMBaseInfo.h" 17be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "MCTargetDesc/ARMFixupKinds.h" 18ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMMCExpr.h" 19be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "MCTargetDesc/ARMMCTargetDesc.h" 20568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach#include "llvm/MC/MCCodeEmitter.h" 21568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach#include "llvm/MC/MCExpr.h" 22568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach#include "llvm/MC/MCInst.h" 2359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "llvm/MC/MCInstrInfo.h" 24be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "llvm/MC/MCRegisterInfo.h" 2559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "llvm/MC/MCSubtargetInfo.h" 26ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/ADT/APFloat.h" 27d6d4b42ba473657b6d30242962f0d0fb23fe126eJim Grosbach#include "llvm/ADT/Statistic.h" 28568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach#include "llvm/Support/raw_ostream.h" 2959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng 30568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachusing namespace llvm; 31568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 3270933266ae73c891d9d1c2f0de72ecd1db8f86dfJim GrosbachSTATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 3370933266ae73c891d9d1c2f0de72ecd1db8f86dfJim GrosbachSTATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 34d6d4b42ba473657b6d30242962f0d0fb23fe126eJim Grosbach 35568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachnamespace { 36568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachclass ARMMCCodeEmitter : public MCCodeEmitter { 37568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT 38568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT 3959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng const MCInstrInfo &MCII; 4059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng const MCSubtargetInfo &STI; 41568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 42568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachpublic: 4359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 4459ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng MCContext &ctx) 45af0a2e6730ffb59405352269e1500b6e83e42d6aEvan Cheng : MCII(mcii), STI(sti) { 46568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach } 47568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 48568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach ~ARMMCCodeEmitter() {} 49568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 5059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng bool isThumb() const { 5159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng // FIXME: Can tablegen auto-generate this? 5259ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 5359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng } 5459ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng bool isThumb2() const { 5559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; 5659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng } 5759ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng bool isTargetDarwin() const { 5859ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Triple TT(STI.getTargetTriple()); 5959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Triple::OSType OS = TT.getOS(); 6059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS; 6159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng } 6259ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng 630de6ab3c43ed2143d661115dddf1480545236c91Jim Grosbach unsigned getMachineSoImmOpValue(unsigned SoImm) const; 640de6ab3c43ed2143d661115dddf1480545236c91Jim Grosbach 659af82ba42b53905f580f8c4270626946e3548654Jim Grosbach // getBinaryCodeForInstr - TableGen'erated function for getting the 669af82ba42b53905f580f8c4270626946e3548654Jim Grosbach // binary encoding for an instruction. 67806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getBinaryCodeForInstr(const MCInst &MI, 68806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 699af82ba42b53905f580f8c4270626946e3548654Jim Grosbach 709af82ba42b53905f580f8c4270626946e3548654Jim Grosbach /// getMachineOpValue - Return binary encoding of operand. If the machine 719af82ba42b53905f580f8c4270626946e3548654Jim Grosbach /// operand requires relocation, record the relocation and return zero. 72806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 73806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 749af82ba42b53905f580f8c4270626946e3548654Jim Grosbach 757597212abced110723f2fee985a7d60557c092ecEvan Cheng /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 76971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson /// the specified operand. This is used for operands with :lower16: and 777597212abced110723f2fee985a7d60557c092ecEvan Cheng /// :upper16: prefixes. 787597212abced110723f2fee985a7d60557c092ecEvan Cheng uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 797597212abced110723f2fee985a7d60557c092ecEvan Cheng SmallVectorImpl<MCFixup> &Fixups) const; 80837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim 8192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 82806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned &Reg, unsigned &Imm, 83806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 8492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 85662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 8609aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling /// BL branch target. 87662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 88662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 89662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach 9009aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 9109aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling /// BLX branch target. 9209aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 9309aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 9409aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling 95e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 96e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 97e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 98e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach 9901086451393ef33e82b6fad623989dd97dd70edfJim Grosbach /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 10001086451393ef33e82b6fad623989dd97dd70edfJim Grosbach uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 10101086451393ef33e82b6fad623989dd97dd70edfJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 10201086451393ef33e82b6fad623989dd97dd70edfJim Grosbach 103027d6e8d1ca04e4096fb3a27579b861d861466c5Jim Grosbach /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 104027d6e8d1ca04e4096fb3a27579b861d861466c5Jim Grosbach uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 105dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 106dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling 107c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 108c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach /// branch target. 109c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 110c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 111c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach 112c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 113c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson /// immediate Thumb2 direct branch target. 114c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 115c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 11610096dbdef22a10a6a4444437c935ab428545525Owen Anderson 117685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 118685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim /// branch target. 119685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 120685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim SmallVectorImpl<MCFixup> &Fixups) const; 121f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 122f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 123c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson 1245d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 1255d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach /// ADR label target. 1265d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 1275d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 128d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 129d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 130a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 131a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 132971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson 1335d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach 13492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 13592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling /// operand. 136806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 137806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 13892b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 139f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 140f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 141f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling SmallVectorImpl<MCFixup> &Fixups)const; 1420f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson 1439d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 1449d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson /// operand. 1459d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 1469d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 147b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 148b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 149b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach /// operand. 150b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 151b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 152b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 153a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' 154a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach /// operand. 155a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 156a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 1579d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 1589d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 15954fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 16054fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach /// operand as needed by load/store instructions. 16154fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 16254fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 16354fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach 1645d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 1655d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 1665d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 1675d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 1685d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach switch (Mode) { 1695f8a917b6558f8fdf31b4a6fa591b396e16b9ff2Matt Beaumont-Gay default: assert(0 && "Unknown addressing sub-mode!"); 1705d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach case ARM_AM::da: return 0; 1715d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach case ARM_AM::ia: return 1; 1725d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach case ARM_AM::db: return 2; 1735d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach case ARM_AM::ib: return 3; 1745d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach } 1755d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach } 17699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 17799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach /// 17899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 17999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach switch (ShOpc) { 18099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach default: llvm_unreachable("Unknown shift opc!"); 18199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::no_shift: 18299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::lsl: return 0; 18399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::lsr: return 1; 18499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::asr: return 2; 18599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::ror: 18699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::rrx: return 3; 18799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach } 18899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach return 0; 18999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach } 19099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 19199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach /// getAddrMode2OpValue - Return encoding for addrmode2 operands. 19299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 19399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 19499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 19599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 19699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 19799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 19899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 1997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 2007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 2017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 2037eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 2047eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 2057eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2067eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach 207570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 208570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 209570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2105d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach 211d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 212d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach /// operand. 213d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 214d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 215d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach 216f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 217f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 21822447ae54bcb8ca94ed994cad103074a24e66781Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 2191fd374e9c1c074c1681336bef31e65f0170b0f7eBill Wendling 220b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 221b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 222b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 223b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling 22492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. 225806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 226806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2273e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach 22808bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach /// getCCOutOpValue - Return encoding of the 's' bit. 229806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 230806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 23108bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 23208bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach // '1' respectively. 23308bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach return MI.getOperand(Op).getReg() == ARM::CPSR; 23408bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach } 235ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 2362a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. 237806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, 238806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 2392a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach unsigned SoImm = MI.getOperand(Op).getImm(); 2402a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach int SoImmVal = ARM_AM::getSOImmVal(SoImm); 2412a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach assert(SoImmVal != -1 && "Not a valid so_imm value!"); 2422a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach 2432a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach // Encode rotate_imm. 2442a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 2452a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach << ARMII::SoRotImmShift; 2462a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach 2472a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach // Encode immed_8. 2482a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 2492a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach return Binary; 2502a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach } 2517bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 2525de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 2535de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 2545de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 2555de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned SoImm = MI.getOperand(Op).getImm(); 2565de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 2575de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 2585de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson return Encoded; 2595de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson } 26008bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach 26175579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 26275579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 26375579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 26475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 2656af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 2666af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 2670e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 2680e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 26975579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson 270ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach /// getSORegOpValue - Return an encoded so_reg shifted register value. 271152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 272152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 273152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 274806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2755de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 2765de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 277ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 278806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 279806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 280498ec20703c89d0c2890b0967791f0f5f2b59a2fOwen Anderson return 64 - MI.getOperand(Op).getImm(); 281498ec20703c89d0c2890b0967791f0f5f2b59a2fOwen Anderson } 2828abe32af38b66bf4577526b23b6af6ec7eb6c155Jim Grosbach 283806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 284806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2853fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach 286a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes unsigned getMsbOpValue(const MCInst &MI, unsigned Op, 287a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes SmallVectorImpl<MCFixup> &Fixups) const; 288a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes 289806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 290806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 291806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 292806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 293183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 294183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang SmallVectorImpl<MCFixup> &Fixups) const; 2958e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 2968e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson SmallVectorImpl<MCFixup> &Fixups) const; 297806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 298806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2996b5252db2db5eeeadec4602329ac56beb6dea54aJim Grosbach 3003116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 3013116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 3023116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 3033116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 3043116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 3053116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 3063116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 3073116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 308a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling 3096d74631062e4464326eb5c680a4d62d340fa42ebOwen Anderson unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 3106d74631062e4464326eb5c680a4d62d340fa42ebOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 3116d74631062e4464326eb5c680a4d62d340fa42ebOwen Anderson 312c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 313c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned EncodedValue) const; 31457dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 315cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling unsigned EncodedValue) const; 3168f143913141991baaa535ca0da7c8a81606d6392Owen Anderson unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 317cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling unsigned EncodedValue) const; 318cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling 319cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling unsigned VFPThumb2PostEncoder(const MCInst &MI, 320cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling unsigned EncodedValue) const; 321c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson 32270933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach void EmitByte(unsigned char C, raw_ostream &OS) const { 323568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach OS << (char)C; 324568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach } 325568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 32670933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 327568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach // Output the constant in little endian byte order. 328568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach for (unsigned i = 0; i != Size; ++i) { 32970933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach EmitByte(Val & 255, OS); 330568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach Val >>= 8; 331568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach } 332568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach } 333568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 334568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 335568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 336568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach}; 337568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 338568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach} // end anonymous namespace 339568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 34059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan ChengMCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII, 34159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng const MCSubtargetInfo &STI, 3420800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling MCContext &Ctx) { 34359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng return new ARMMCCodeEmitter(MCII, STI, Ctx); 344568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach} 345568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 3467bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 3477bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach/// instructions, and rewrite them to their Thumb2 form if we are currently in 348c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson/// Thumb2 mode. 349c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Andersonunsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 350c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned EncodedValue) const { 35159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) { 3527bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 353c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 354c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson // set to 1111. 355c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned Bit24 = EncodedValue & 0x01000000; 356c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned Bit28 = Bit24 << 4; 357c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson EncodedValue &= 0xEFFFFFFF; 358c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson EncodedValue |= Bit28; 359c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson EncodedValue |= 0x0F000000; 360c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson } 3617bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 362c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson return EncodedValue; 363c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson} 364c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson 36557dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 3667bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach/// instructions, and rewrite them to their Thumb2 form if we are currently in 36757dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson/// Thumb2 mode. 36857dac88f775c1191a98cff89abd1f7ad33df5e29Owen Andersonunsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 36957dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson unsigned EncodedValue) const { 37059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) { 37157dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson EncodedValue &= 0xF0FFFFFF; 37257dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson EncodedValue |= 0x09000000; 37357dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson } 3747bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 37557dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson return EncodedValue; 37657dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson} 37757dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson 3788f143913141991baaa535ca0da7c8a81606d6392Owen Anderson/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 3797bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach/// instructions, and rewrite them to their Thumb2 form if we are currently in 3808f143913141991baaa535ca0da7c8a81606d6392Owen Anderson/// Thumb2 mode. 3818f143913141991baaa535ca0da7c8a81606d6392Owen Andersonunsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 3828f143913141991baaa535ca0da7c8a81606d6392Owen Anderson unsigned EncodedValue) const { 38359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) { 3848f143913141991baaa535ca0da7c8a81606d6392Owen Anderson EncodedValue &= 0x00FFFFFF; 3858f143913141991baaa535ca0da7c8a81606d6392Owen Anderson EncodedValue |= 0xEE000000; 3868f143913141991baaa535ca0da7c8a81606d6392Owen Anderson } 3877bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 3888f143913141991baaa535ca0da7c8a81606d6392Owen Anderson return EncodedValue; 3898f143913141991baaa535ca0da7c8a81606d6392Owen Anderson} 3908f143913141991baaa535ca0da7c8a81606d6392Owen Anderson 391cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 392cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling/// them to their Thumb2 form if we are currently in Thumb2 mode. 393cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendlingunsigned ARMMCCodeEmitter:: 394cf590263cd5c24ccf1d08cef612738d99cd980d9Bill WendlingVFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { 39559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) { 396cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling EncodedValue &= 0x0FFFFFFF; 397cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling EncodedValue |= 0xE0000000; 398cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling } 399cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling return EncodedValue; 400cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling} 40157dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson 40256ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach/// getMachineOpValue - Return binary encoding of operand. If the machine 40356ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach/// operand requires relocation, record the relocation and return zero. 404806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 405806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetMachineOpValue(const MCInst &MI, const MCOperand &MO, 406806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 407bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling if (MO.isReg()) { 4080800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling unsigned Reg = MO.getReg(); 4090800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling unsigned RegNo = getARMRegisterNumbering(Reg); 410d8a11c25fa64c152628cfcf5f9d36eb60242b302Jim Grosbach 411b0708d292bbe04cfcfe0c5cb5e27d8a872c9839aJim Grosbach // Q registers are encoded as 2x their register number. 4120800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling switch (Reg) { 4130800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling default: 4140800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling return RegNo; 4150800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 4160800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 4170800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 4180800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 4190800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling return 2 * RegNo; 42090d4cf931477b497553a9f2d0ed53377dd5dd88cOwen Anderson } 421bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling } else if (MO.isImm()) { 42256ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach return static_cast<unsigned>(MO.getImm()); 423bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling } else if (MO.isFPImm()) { 424bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling return static_cast<unsigned>(APFloat(MO.getFPImm()) 425bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling .bitcastToAPInt().getHiBits(32).getLimitedValue()); 4260800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling } 4270800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling 428817c1a6dddadb4664738777d224bc7eae6e62cf3Jim Grosbach llvm_unreachable("Unable to encode MCOperand!"); 42956ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach return 0; 43056ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach} 43156ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach 4325df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0adBill Wendling/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 433806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachbool ARMMCCodeEmitter:: 434806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachEncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 435806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const { 4363e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 4373e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 4389af3d1c0dc2250793ada1ca6cfa98e9f1253f7f9Jim Grosbach 43992b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Reg = getARMRegisterNumbering(MO.getReg()); 44092b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 44192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling int32_t SImm = MO1.getImm(); 44292b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling bool isAdd = true; 4435df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0adBill Wendling 444ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach // Special value for #-0 4450da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson if (SImm == INT32_MIN) { 44692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling SImm = 0; 4470da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson isAdd = false; 4480da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson } 4495df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0adBill Wendling 450ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 45192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling if (SImm < 0) { 45292b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling SImm = -SImm; 45392b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling isAdd = false; 45492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling } 45592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 45692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Imm = SImm; 45792b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling return isAdd; 45892b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling} 4595df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0adBill Wendling 460dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// getBranchTargetOpValue - Helper function to get the branch target operand, 461dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// which is either an immediate or requires a fixup. 462dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendlingstatic uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 463dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling unsigned FixupKind, 464dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling SmallVectorImpl<MCFixup> &Fixups) { 465662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 466662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach 467662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach // If the destination is an immediate, we have nothing to do. 468662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach if (MO.isImm()) return MO.getImm(); 469dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling assert(MO.isExpr() && "Unexpected branch target type!"); 470662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach const MCExpr *Expr = MO.getExpr(); 471dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling MCFixupKind Kind = MCFixupKind(FixupKind); 472662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 473662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach 474662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach // All of the information is in the fixup. 475662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach return 0; 476662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach} 477662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach 478559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 479559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson// determined by negating them and XOR'ing them with bit 23. 480559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Andersonstatic int32_t encodeThumbBLOffset(int32_t offset) { 481559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson offset >>= 1; 482559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson uint32_t S = (offset & 0x800000) >> 23; 483559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson uint32_t J1 = (offset & 0x400000) >> 22; 484559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson uint32_t J2 = (offset & 0x200000) >> 21; 485559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson J1 = (~J1 & 0x1); 486559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson J2 = (~J2 & 0x1); 487559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson J1 ^= S; 488559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson J2 ^= S; 489559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson 490559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson offset &= ~0x600000; 491559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson offset |= J1 << 22; 492559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson offset |= J2 << 21; 493559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson 494559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson return offset; 495559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson} 496559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson 497dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 498c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbachuint32_t ARMMCCodeEmitter:: 499dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill WendlinggetThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 500c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 501559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 502559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson if (MO.isExpr()) 503559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 504559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson Fixups); 505559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson return encodeThumbBLOffset(MO.getImm()); 506dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling} 507c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach 50809aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 50909aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling/// BLX branch target. 51009aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendlinguint32_t ARMMCCodeEmitter:: 51109aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill WendlinggetThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 51209aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 513559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 514559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson if (MO.isExpr()) 515559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 516559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson Fixups); 517559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson return encodeThumbBLOffset(MO.getImm()); 51809aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling} 51909aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling 520e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 521e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbachuint32_t ARMMCCodeEmitter:: 522e246717c3a36a913fd4200776ed621649bb2b624Jim GrosbachgetThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 523e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 524391ac65377f2ad5e48a796e75120959e22430605Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 525391ac65377f2ad5e48a796e75120959e22430605Owen Anderson if (MO.isExpr()) 526559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 527559c277aa9242dd5b32d2f2ccc353d938f886ee9Owen Anderson Fixups); 528391ac65377f2ad5e48a796e75120959e22430605Owen Anderson return (MO.getImm() >> 1); 529e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach} 530e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach 53101086451393ef33e82b6fad623989dd97dd70edfJim Grosbach/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 53201086451393ef33e82b6fad623989dd97dd70edfJim Grosbachuint32_t ARMMCCodeEmitter:: 53301086451393ef33e82b6fad623989dd97dd70edfJim GrosbachgetThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 534e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 535721cb1fde07423fd1905338d443172a8028ad634Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 536721cb1fde07423fd1905338d443172a8028ad634Owen Anderson if (MO.isExpr()) 537721cb1fde07423fd1905338d443172a8028ad634Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 538721cb1fde07423fd1905338d443172a8028ad634Owen Anderson Fixups); 539721cb1fde07423fd1905338d443172a8028ad634Owen Anderson return (MO.getImm() >> 1); 54001086451393ef33e82b6fad623989dd97dd70edfJim Grosbach} 54101086451393ef33e82b6fad623989dd97dd70edfJim Grosbach 542027d6e8d1ca04e4096fb3a27579b861d861466c5Jim Grosbach/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 543dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendlinguint32_t ARMMCCodeEmitter:: 544027d6e8d1ca04e4096fb3a27579b861d861466c5Jim GrosbachgetThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 545dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 54621df36c57afc588c8073a070a47e3ba45fa87270Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 54721df36c57afc588c8073a070a47e3ba45fa87270Owen Anderson if (MO.isExpr()) 54821df36c57afc588c8073a070a47e3ba45fa87270Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); 54921df36c57afc588c8073a070a47e3ba45fa87270Owen Anderson return (MO.getImm() >> 1); 550dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling} 551c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach 552685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim/// Return true if this branch has a non-always predication 553685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kimstatic bool HasConditionalBranch(const MCInst &MI) { 554685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim int NumOp = MI.getNumOperands(); 555685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim if (NumOp >= 2) { 556685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim for (int i = 0; i < NumOp-1; ++i) { 557685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim const MCOperand &MCOp1 = MI.getOperand(i); 558685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim const MCOperand &MCOp2 = MI.getOperand(i + 1); 55910096dbdef22a10a6a4444437c935ab428545525Owen Anderson if (MCOp1.isImm() && MCOp2.isReg() && 560685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 56110096dbdef22a10a6a4444437c935ab428545525Owen Anderson if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 562685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim return true; 563685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim } 564685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim } 565685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim } 566685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim return false; 567685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim} 568685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim 569dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 570dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// target. 571dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendlinguint32_t ARMMCCodeEmitter:: 572dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill WendlinggetBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 573dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 574092e2cd5693114a4f1d93eb5b72f3e194de27236Jim Grosbach // FIXME: This really, really shouldn't use TargetMachine. We don't want 575092e2cd5693114a4f1d93eb5b72f3e194de27236Jim Grosbach // coupling between MC and TM anywhere we can help it. 57659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) 577c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson return 578c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); 579685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim return getARMBranchTargetOpValue(MI, OpIdx, Fixups); 580685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim} 581685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim 582685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 583685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim/// target. 584685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kimuint32_t ARMMCCodeEmitter:: 585685c350ae76b588e1f00c01a511fe8bd57f18394Jason W KimgetARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 586685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim SmallVectorImpl<MCFixup> &Fixups) const { 587d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 588d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson if (MO.isExpr()) { 58910096dbdef22a10a6a4444437c935ab428545525Owen Anderson if (HasConditionalBranch(MI)) 590d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, 591d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson ARM::fixup_arm_condbranch, Fixups); 59210096dbdef22a10a6a4444437c935ab428545525Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, 593d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson ARM::fixup_arm_uncondbranch, Fixups); 594d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson } 595d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson 596d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson return MO.getImm() >> 2; 597c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach} 598c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach 599f1eab597b2316c6cfcabfcee98895fedb2071722Owen Andersonuint32_t ARMMCCodeEmitter:: 600f1eab597b2316c6cfcabfcee98895fedb2071722Owen AndersongetARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 601f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 602f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 603f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson if (MO.isExpr()) { 60410096dbdef22a10a6a4444437c935ab428545525Owen Anderson if (HasConditionalBranch(MI)) 605f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, 606f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson ARM::fixup_arm_condbranch, Fixups); 60710096dbdef22a10a6a4444437c935ab428545525Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, 608f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson ARM::fixup_arm_uncondbranch, Fixups); 609f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson } 610685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim 611f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson return MO.getImm() >> 1; 612f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson} 613685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim 614c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 615c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson/// immediate branch target. 616c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Andersonuint32_t ARMMCCodeEmitter:: 617c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen AndersongetUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 618c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 619c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson unsigned Val = 620c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups); 621c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson bool I = (Val & 0x800000); 622c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson bool J1 = (Val & 0x400000); 623c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson bool J2 = (Val & 0x200000); 624c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson if (I ^ J1) 625c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson Val &= ~0x400000; 626c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson else 627c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson Val |= 0x400000; 628971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson 629c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson if (I ^ J2) 630c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson Val &= ~0x200000; 631c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson else 632c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson Val |= 0x200000; 633971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson 634c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson return Val; 635c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson} 636c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson 637dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 638dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// target. 6395d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbachuint32_t ARMMCCodeEmitter:: 6405d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim GrosbachgetAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 6415d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 64296425c846494c1c20a4c931f4783571295ab170cOwen Anderson const MCOperand MO = MI.getOperand(OpIdx); 64396425c846494c1c20a4c931f4783571295ab170cOwen Anderson if (MO.isExpr()) 64496425c846494c1c20a4c931f4783571295ab170cOwen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 64596425c846494c1c20a4c931f4783571295ab170cOwen Anderson Fixups); 64696425c846494c1c20a4c931f4783571295ab170cOwen Anderson int32_t offset = MO.getImm(); 64796425c846494c1c20a4c931f4783571295ab170cOwen Anderson uint32_t Val = 0x2000; 64896425c846494c1c20a4c931f4783571295ab170cOwen Anderson if (offset < 0) { 64996425c846494c1c20a4c931f4783571295ab170cOwen Anderson Val = 0x1000; 65096425c846494c1c20a4c931f4783571295ab170cOwen Anderson offset *= -1; 65196425c846494c1c20a4c931f4783571295ab170cOwen Anderson } 65296425c846494c1c20a4c931f4783571295ab170cOwen Anderson Val |= offset; 65396425c846494c1c20a4c931f4783571295ab170cOwen Anderson return Val; 6545d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach} 6555d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach 656a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 657a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson/// target. 658a838a25d59838adfa91463f6a918ae3adeb352c1Owen Andersonuint32_t ARMMCCodeEmitter:: 659a838a25d59838adfa91463f6a918ae3adeb352c1Owen AndersongetT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 660a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 66196425c846494c1c20a4c931f4783571295ab170cOwen Anderson const MCOperand MO = MI.getOperand(OpIdx); 66296425c846494c1c20a4c931f4783571295ab170cOwen Anderson if (MO.isExpr()) 66396425c846494c1c20a4c931f4783571295ab170cOwen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 66496425c846494c1c20a4c931f4783571295ab170cOwen Anderson Fixups); 66508fef885eb39339a47e3be7f0842b1db33683003Owen Anderson int32_t Val = MO.getImm(); 66608fef885eb39339a47e3be7f0842b1db33683003Owen Anderson if (Val < 0) { 66708fef885eb39339a47e3be7f0842b1db33683003Owen Anderson Val *= -1; 66808fef885eb39339a47e3be7f0842b1db33683003Owen Anderson Val |= 0x1000; 66908fef885eb39339a47e3be7f0842b1db33683003Owen Anderson } 67008fef885eb39339a47e3be7f0842b1db33683003Owen Anderson return Val; 671a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson} 672a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson 673d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 674d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach/// target. 675d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbachuint32_t ARMMCCodeEmitter:: 676d40963c4065432ec7e47879d3ca665a54ee903b6Jim GrosbachgetThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 677d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 67896425c846494c1c20a4c931f4783571295ab170cOwen Anderson const MCOperand MO = MI.getOperand(OpIdx); 67996425c846494c1c20a4c931f4783571295ab170cOwen Anderson if (MO.isExpr()) 68096425c846494c1c20a4c931f4783571295ab170cOwen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 68196425c846494c1c20a4c931f4783571295ab170cOwen Anderson Fixups); 68296425c846494c1c20a4c931f4783571295ab170cOwen Anderson return MO.getImm(); 683d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach} 684d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach 685f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 686f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling/// operand. 6870f4b60d43a289671082deee3bd56a3a055afb16aOwen Andersonuint32_t ARMMCCodeEmitter:: 688f4caf69720d807573c50d41aa06bcec1c99bdbbdBill WendlinggetThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 689f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling SmallVectorImpl<MCFixup> &) const { 690f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling // [Rn, Rm] 691f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling // {5-3} = Rm 692f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling // {2-0} = Rn 6930f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson const MCOperand &MO1 = MI.getOperand(OpIdx); 694f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 6950f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson unsigned Rn = getARMRegisterNumbering(MO1.getReg()); 6960f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson unsigned Rm = getARMRegisterNumbering(MO2.getReg()); 6970f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson return (Rm << 3) | Rn; 6980f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson} 6990f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson 70092b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 701806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachuint32_t ARMMCCodeEmitter:: 702806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 703806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 70492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {17-13} = reg 70592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {12} = (U)nsigned (add == '1', sub == '0') 70692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {11-0} = imm12 70792b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling unsigned Reg, Imm12; 70870933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach bool isAdd = true; 70970933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach // If The first operand isn't a register, we have a label reference. 71070933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 711971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson if (!MO.isReg()) { 712679cbd3b215b1769a6035e334f9009aeeb940dddJim Grosbach Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 71370933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach Imm12 = 0; 71497dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach isAdd = false ; // 'U' bit is set as part of the fixup. 71570933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach 716971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson assert(MO.isExpr() && "Unexpected machine operand type!"); 717971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson const MCExpr *Expr = MO.getExpr(); 7187bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 719d7b3f5870d9d04351d9cd363d9d6af01482a2eb8Owen Anderson MCFixupKind Kind; 72059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) 721d7b3f5870d9d04351d9cd363d9d6af01482a2eb8Owen Anderson Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 722d7b3f5870d9d04351d9cd363d9d6af01482a2eb8Owen Anderson else 723d7b3f5870d9d04351d9cd363d9d6af01482a2eb8Owen Anderson Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 72470933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 72570933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach 72670933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach ++MCNumCPRelocations; 72770933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach } else 72870933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); 72992b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 73092b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling uint32_t Binary = Imm12 & 0xfff; 73192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 732ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach if (isAdd) 73392b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Binary |= (1 << 12); 73492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Binary |= (Reg << 13); 73592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling return Binary; 73692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling} 73792b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 738a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// getT2Imm8s4OpValue - Return encoding info for 739a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// '+/- imm8<<2' operand. 740a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachuint32_t ARMMCCodeEmitter:: 741a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachgetT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 742a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 743a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // FIXME: The immediate operand should have already been encoded like this 744a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // before ever getting here. The encoder method should just need to combine 745a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // the MI operands for the register and the offset into a single 746a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // representation for the complex operand in the .td file. This isn't just 747a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // style, unfortunately. As-is, we can't represent the distinct encoding 748a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // for #-0. 749a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 750a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // {8} = (U)nsigned (add == '1', sub == '0') 751a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // {7-0} = imm8 752a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach int32_t Imm8 = MI.getOperand(OpIdx).getImm(); 753a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isAdd = Imm8 >= 0; 754a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 755a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 756a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach if (Imm8 < 0) 757a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Imm8 = -Imm8; 758a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 759a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Scaled by 4. 760a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Imm8 /= 4; 761a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 762a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach uint32_t Binary = Imm8 & 0xff; 763a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 764a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach if (isAdd) 765a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Binary |= (1 << 8); 766a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return Binary; 767a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 768a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 7699d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson/// getT2AddrModeImm8s4OpValue - Return encoding info for 7709d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson/// 'reg +/- imm8<<2' operand. 7719d63d90de5e57ad96f467b270544443a9284eb2bOwen Andersonuint32_t ARMMCCodeEmitter:: 7729d63d90de5e57ad96f467b270544443a9284eb2bOwen AndersongetT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 7739d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 77490cc533fda9742f5c67203f97e69e5efd270c676Jim Grosbach // {12-9} = reg 77590cc533fda9742f5c67203f97e69e5efd270c676Jim Grosbach // {8} = (U)nsigned (add == '1', sub == '0') 77690cc533fda9742f5c67203f97e69e5efd270c676Jim Grosbach // {7-0} = imm8 7779d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson unsigned Reg, Imm8; 7789d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson bool isAdd = true; 7799d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson // If The first operand isn't a register, we have a label reference. 7809d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson const MCOperand &MO = MI.getOperand(OpIdx); 7819d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson if (!MO.isReg()) { 7829d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 7839d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson Imm8 = 0; 7849d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson isAdd = false ; // 'U' bit is set as part of the fixup. 7859d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 7869d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson assert(MO.isExpr() && "Unexpected machine operand type!"); 7879d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson const MCExpr *Expr = MO.getExpr(); 7889d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 7899d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 7909d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 7919d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson ++MCNumCPRelocations; 7929d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson } else 7939d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 7949d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 795a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // FIXME: The immediate operand should have already been encoded like this 796a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // before ever getting here. The encoder method should just need to combine 797a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // the MI operands for the register and the offset into a single 798a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // representation for the complex operand in the .td file. This isn't just 799a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // style, unfortunately. As-is, we can't represent the distinct encoding 800a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // for #-0. 8019d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson uint32_t Binary = (Imm8 >> 2) & 0xff; 8029d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 8039d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson if (isAdd) 80490cc533fda9742f5c67203f97e69e5efd270c676Jim Grosbach Binary |= (1 << 8); 8059d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson Binary |= (Reg << 9); 8069d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson return Binary; 8079d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson} 8089d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 809b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 810b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach/// 'reg + imm8<<2' operand. 811b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbachuint32_t ARMMCCodeEmitter:: 812b6aed508e310e31dcb080e761ca856127cec0773Jim GrosbachgetT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 813b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 814b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // {11-8} = reg 815b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // {7-0} = imm8 816b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 817b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 818b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach unsigned Reg = getARMRegisterNumbering(MO.getReg()); 819b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach unsigned Imm8 = MO1.getImm(); 820b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return (Reg << 8) | Imm8; 821b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach} 822b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 82386a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// FIXME: This routine assumes that a binary 82486a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// expression will always result in a PCRel expression 82586a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// In reality, its only true if one or more subexpressions 82686a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// is itself a PCRel (i.e. "." in asm or some other pcrel construct) 82786a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// but this is good enough for now. 82886a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kimstatic bool EvaluateAsPCRel(const MCExpr *Expr) { 82986a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim switch (Expr->getKind()) { 8305f8a917b6558f8fdf31b4a6fa591b396e16b9ff2Matt Beaumont-Gay default: assert(0 && "Unexpected expression type"); 83186a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim case MCExpr::SymbolRef: return false; 83286a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim case MCExpr::Binary: return true; 83386a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim } 83486a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim} 83586a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim 8367597212abced110723f2fee985a7d60557c092ecEvan Chenguint32_t 8377597212abced110723f2fee985a7d60557c092ecEvan ChengARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 8387597212abced110723f2fee985a7d60557c092ecEvan Cheng SmallVectorImpl<MCFixup> &Fixups) const { 839837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim // {20-16} = imm{15-12} 840837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim // {11-0} = imm{11-0} 8417bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 8427597212abced110723f2fee985a7d60557c092ecEvan Cheng if (MO.isImm()) 8437597212abced110723f2fee985a7d60557c092ecEvan Cheng // Hi / lo 16 bits already extracted during earlier passes. 844837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim return static_cast<unsigned>(MO.getImm()); 8457597212abced110723f2fee985a7d60557c092ecEvan Cheng 8467597212abced110723f2fee985a7d60557c092ecEvan Cheng // Handle :upper16: and :lower16: assembly prefixes. 8477597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *E = MO.getExpr(); 8487597212abced110723f2fee985a7d60557c092ecEvan Cheng if (E->getKind() == MCExpr::Target) { 8497597212abced110723f2fee985a7d60557c092ecEvan Cheng const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 8507597212abced110723f2fee985a7d60557c092ecEvan Cheng E = ARM16Expr->getSubExpr(); 8517597212abced110723f2fee985a7d60557c092ecEvan Cheng 852837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim MCFixupKind Kind; 8537597212abced110723f2fee985a7d60557c092ecEvan Cheng switch (ARM16Expr->getKind()) { 8545f8a917b6558f8fdf31b4a6fa591b396e16b9ff2Matt Beaumont-Gay default: assert(0 && "Unsupported ARMFixup"); 8557597212abced110723f2fee985a7d60557c092ecEvan Cheng case ARMMCExpr::VK_ARM_HI16: 85659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (!isTargetDarwin() && EvaluateAsPCRel(E)) 85759ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Kind = MCFixupKind(isThumb2() 858f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng ? ARM::fixup_t2_movt_hi16_pcrel 859f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng : ARM::fixup_arm_movt_hi16_pcrel); 860f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng else 86159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Kind = MCFixupKind(isThumb2() 862f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng ? ARM::fixup_t2_movt_hi16 863f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng : ARM::fixup_arm_movt_hi16); 864837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim break; 8657597212abced110723f2fee985a7d60557c092ecEvan Cheng case ARMMCExpr::VK_ARM_LO16: 86659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (!isTargetDarwin() && EvaluateAsPCRel(E)) 86759ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Kind = MCFixupKind(isThumb2() 868f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng ? ARM::fixup_t2_movw_lo16_pcrel 869f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng : ARM::fixup_arm_movw_lo16_pcrel); 870f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng else 87159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Kind = MCFixupKind(isThumb2() 872f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng ? ARM::fixup_t2_movw_lo16 873f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng : ARM::fixup_arm_movw_lo16); 874837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim break; 875837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim } 8767597212abced110723f2fee985a7d60557c092ecEvan Cheng Fixups.push_back(MCFixup::Create(0, E, Kind)); 877837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim return 0; 878817c1a6dddadb4664738777d224bc7eae6e62cf3Jim Grosbach }; 8797597212abced110723f2fee985a7d60557c092ecEvan Cheng 880817c1a6dddadb4664738777d224bc7eae6e62cf3Jim Grosbach llvm_unreachable("Unsupported MCExpr type in MCOperand!"); 881837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim return 0; 882837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim} 883837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim 884837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kimuint32_t ARMMCCodeEmitter:: 88554fea632b161f98e96ec7275922e35102bcecc5dJim GrosbachgetLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 88654fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 88754fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 88854fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 88954fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach const MCOperand &MO2 = MI.getOperand(OpIdx+2); 89054fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach unsigned Rn = getARMRegisterNumbering(MO.getReg()); 89154fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach unsigned Rm = getARMRegisterNumbering(MO1.getReg()); 89254fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 89354fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 89499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 89599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach unsigned SBits = getShiftOp(ShOp); 89654fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach 89754fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {16-13} = Rn 89854fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {12} = isAdd 89954fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {11-0} = shifter 90054fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {3-0} = Rm 90154fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {4} = 0 90254fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {6-5} = type 90354fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {11-7} = imm 904570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach uint32_t Binary = Rm; 90554fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach Binary |= Rn << 13; 90654fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach Binary |= SBits << 5; 90754fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach Binary |= ShImm << 7; 90854fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach if (isAdd) 90954fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach Binary |= 1 << 12; 91054fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach return Binary; 91154fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach} 91254fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach 913570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbachuint32_t ARMMCCodeEmitter:: 91499f53d13efc259b47c93dc0d90a5db763cbe371aJim GrosbachgetAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 91599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 91699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {17-14} Rn 91799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {13} 1 == imm12, 0 == Rm 91899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {12} isAdd 91999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {11-0} imm12/Rm 92099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 92199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach unsigned Rn = getARMRegisterNumbering(MO.getReg()); 92299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups); 92399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach Binary |= Rn << 14; 92499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach return Binary; 92599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach} 92699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 92799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbachuint32_t ARMMCCodeEmitter:: 92899f53d13efc259b47c93dc0d90a5db763cbe371aJim GrosbachgetAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 92999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 93099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {13} 1 == imm12, 0 == Rm 93199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {12} isAdd 93299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {11-0} imm12/Rm 93399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 93499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 93599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach unsigned Imm = MO1.getImm(); 93699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 93799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach bool isReg = MO.getReg() != 0; 93899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach uint32_t Binary = ARM_AM::getAM2Offset(Imm); 93999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 94099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach if (isReg) { 94199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 94299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach Binary <<= 7; // Shift amount is bits [11:7] 94399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 94499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0] 94599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach } 94699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach return Binary | (isAdd << 12) | (isReg << 13); 94799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach} 94899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 94999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbachuint32_t ARMMCCodeEmitter:: 9507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachgetPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 9517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 9527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // {4} isAdd 9537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // {3-0} Rm 9547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 9557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 95616578b50889329eb62774148091ba0f38b681a09Jim Grosbach bool isAdd = MO1.getImm() != 0; 9577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4); 9587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 9597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 9607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachuint32_t ARMMCCodeEmitter:: 9617eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim GrosbachgetAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 9627eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 9637eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // {9} 1 == imm8, 0 == Rm 9647eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // {8} isAdd 9657eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // {7-4} imm7_4/zero 9667eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // {3-0} imm3_0/Rm 9677eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 9687eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 9697eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach unsigned Imm = MO1.getImm(); 9707eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 9717eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach bool isImm = MO.getReg() == 0; 9727eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 9737eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 9747eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach if (!isImm) 9757eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach Imm8 = getARMRegisterNumbering(MO.getReg()); 9767eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach return Imm8 | (isAdd << 8) | (isImm << 9); 9777eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach} 9787eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach 9797eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbachuint32_t ARMMCCodeEmitter:: 980570a9226913ebe1af04832b8fb3273c70b4ee152Jim GrosbachgetAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 981570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 982570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {13} 1 == imm8, 0 == Rm 983570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {12-9} Rn 984570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {8} isAdd 985570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {7-4} imm7_4/zero 986570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {3-0} imm3_0/Rm 987570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 988570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 989570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach const MCOperand &MO2 = MI.getOperand(OpIdx+2); 990570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach unsigned Rn = getARMRegisterNumbering(MO.getReg()); 991570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach unsigned Imm = MO2.getImm(); 992570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 993570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach bool isImm = MO1.getReg() == 0; 994570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 995570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 996570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach if (!isImm) 997570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach Imm8 = getARMRegisterNumbering(MO1.getReg()); 998570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 999570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach} 1000570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach 1001b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1002d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbachuint32_t ARMMCCodeEmitter:: 1003d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim GrosbachgetAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1004d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 1005d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach // [SP, #imm] 1006d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach // {7-0} = imm8 1007d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1008b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1009b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling "Unexpected base register!"); 10107a905a82f7425d1a10b828c8bb3365b2ebc15833Bill Wendling 1011d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach // The immediate is already shifted for the implicit zeroes, so no change 1012d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach // here. 1013d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach return MO1.getImm() & 0xff; 1014d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach} 1015d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach 1016f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling/// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1017272df516d7a9b1f0f69174276abaa759816ee456Bill Wendlinguint32_t ARMMCCodeEmitter:: 1018f4caf69720d807573c50d41aa06bcec1c99bdbbdBill WendlinggetAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 101922447ae54bcb8ca94ed994cad103074a24e66781Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 1020ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling // [Rn, #imm] 1021ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling // {7-3} = imm5 1022ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling // {2-0} = Rn 1023ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling const MCOperand &MO = MI.getOperand(OpIdx); 1024ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1025ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling unsigned Rn = getARMRegisterNumbering(MO.getReg()); 1026656b3d22f70c2d1c8a5286f7270cb380df862565Matt Beaumont-Gay unsigned Imm5 = MO1.getImm(); 1027272df516d7a9b1f0f69174276abaa759816ee456Bill Wendling return ((Imm5 & 0x1f) << 3) | Rn; 10281fd374e9c1c074c1681336bef31e65f0170b0f7eBill Wendling} 10291fd374e9c1c074c1681336bef31e65f0170b0f7eBill Wendling 1030b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1031b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendlinguint32_t ARMMCCodeEmitter:: 1032b8958b031ec5163261f490f131780c5dc3d823d6Bill WendlinggetAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1033b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 1034a7710edd98d71a81c43f8e3889cf0c790885d1b8Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 1035a7710edd98d71a81c43f8e3889cf0c790885d1b8Owen Anderson if (MO.isExpr()) 1036a7710edd98d71a81c43f8e3889cf0c790885d1b8Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); 1037a7710edd98d71a81c43f8e3889cf0c790885d1b8Owen Anderson return (MO.getImm() >> 2); 1038b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling} 1039b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling 10405177f79c378b47e38bed5ac05ba4b597f31b864eJim Grosbach/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. 1041806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachuint32_t ARMMCCodeEmitter:: 1042806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1043806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 104492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {12-9} = reg 104592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {8} = (U)nsigned (add == '1', sub == '0') 104692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {7-0} = imm8 104792b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling unsigned Reg, Imm8; 104897dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach bool isAdd; 104970933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach // If The first operand isn't a register, we have a label reference. 105070933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 105170933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach if (!MO.isReg()) { 1052679cbd3b215b1769a6035e334f9009aeeb940dddJim Grosbach Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 105370933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach Imm8 = 0; 105497dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach isAdd = false; // 'U' bit is handled as part of the fixup. 105570933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach 105670933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach assert(MO.isExpr() && "Unexpected machine operand type!"); 105770933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach const MCExpr *Expr = MO.getExpr(); 1058d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3cOwen Anderson MCFixupKind Kind; 105959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) 1060d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3cOwen Anderson Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1061d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3cOwen Anderson else 1062d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3cOwen Anderson Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 106370933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 106470933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach 106570933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach ++MCNumCPRelocations; 106697dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach } else { 106770933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 106897dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 106997dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach } 107092b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 107192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 107292b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 107397dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach if (isAdd) 107492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Binary |= (1 << 8); 107592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Binary |= (Reg << 9); 10763e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach return Binary; 10773e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach} 10783e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach 1079806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 1080152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen AndersongetSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1081806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 10820800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1083354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // shifted. The second is Rs, the amount to shift by, and the third specifies 1084354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // the type of the shift. 108535b2de012d9404e3e9e4373e45f41711f752dd3aJim Grosbach // 1086ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // {3-0} = Rm. 1087354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {4} = 1 1088ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // {6-5} = type 1089354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {11-8} = Rs 1090354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {7} = 0 1091ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1092ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 1093ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1094ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1095ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1096ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1097ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // Encode Rm. 1098ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach unsigned Binary = getARMRegisterNumbering(MO.getReg()); 1099ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1100ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // Encode the shift opcode. 1101ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach unsigned SBits = 0; 1102ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach unsigned Rs = MO1.getReg(); 1103ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach if (Rs) { 1104ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // Set shift operand (bit[7:4]). 1105ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // LSL - 0001 1106ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // LSR - 0011 1107ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // ASR - 0101 1108ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // ROR - 0111 1109ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach switch (SOpc) { 1110ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach default: llvm_unreachable("Unknown shift opc!"); 1111ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach case ARM_AM::lsl: SBits = 0x1; break; 1112ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach case ARM_AM::lsr: SBits = 0x3; break; 1113ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach case ARM_AM::asr: SBits = 0x5; break; 1114ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach case ARM_AM::ror: SBits = 0x7; break; 1115ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach } 1116ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach } 11170800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling 1118ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach Binary |= SBits << 4; 1119ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1120354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // Encode the shift operation Rs. 1121152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Encode Rs bit[11:8]. 1122152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1123152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 1124152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson} 1125152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1126152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Andersonunsigned ARMMCCodeEmitter:: 1127152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen AndersongetSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1128152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 1129354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1130354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // shifted. The second is the amount to shift by. 1131152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // 1132152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // {3-0} = Rm. 1133354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {4} = 0 1134152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // {6-5} = type 1135354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {11-7} = imm 1136152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1137152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &MO = MI.getOperand(OpIdx); 1138152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1139152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1140152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1141152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Encode Rm. 1142152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson unsigned Binary = getARMRegisterNumbering(MO.getReg()); 1143152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1144152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Encode the shift opcode. 1145152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson unsigned SBits = 0; 1146152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1147152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Set shift operand (bit[6:4]). 1148152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // LSL - 000 1149152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // LSR - 010 1150152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // ASR - 100 1151152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // ROR - 110 1152152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // RRX - 110 and bit[11:8] clear. 1153152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson switch (SOpc) { 1154152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson default: llvm_unreachable("Unknown shift opc!"); 1155152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::lsl: SBits = 0x0; break; 1156152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::lsr: SBits = 0x2; break; 1157152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::asr: SBits = 0x4; break; 1158152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::ror: SBits = 0x6; break; 1159152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::rrx: 1160152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson Binary |= 0x60; 1161152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return Binary; 1162ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach } 1163ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1164ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // Encode shift_imm bit[11:7]. 1165152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson Binary |= SBits << 4; 11663dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 11673dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson assert(Offset && "Offset must be in range 1-32!"); 11683dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson if (Offset == 32) Offset = 0; 11693dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson return Binary | (Offset << 7); 1170ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach} 1171ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1172152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1173806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 117475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen AndersongetT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 117575579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 117675579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson const MCOperand &MO1 = MI.getOperand(OpNum); 117775579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson const MCOperand &MO2 = MI.getOperand(OpNum+1); 11787bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach const MCOperand &MO3 = MI.getOperand(OpNum+2); 11797bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 118075579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // Encoded as [Rn, Rm, imm]. 118175579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // FIXME: Needs fixup support. 118275579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson unsigned Value = getARMRegisterNumbering(MO1.getReg()); 118375579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value <<= 4; 118475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value |= getARMRegisterNumbering(MO2.getReg()); 118575579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value <<= 2; 118675579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value |= MO3.getImm(); 11877bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 118875579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson return Value; 118975579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson} 119075579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson 119175579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Andersonunsigned ARMMCCodeEmitter:: 119275579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen AndersongetT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 119375579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 119475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson const MCOperand &MO1 = MI.getOperand(OpNum); 119575579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson const MCOperand &MO2 = MI.getOperand(OpNum+1); 119675579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson 119775579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // FIXME: Needs fixup support. 119875579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson unsigned Value = getARMRegisterNumbering(MO1.getReg()); 11997bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 120075579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // Even though the immediate is 8 bits long, we need 9 bits in order 120175579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // to represent the (inverse of the) sign bit. 120275579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value <<= 9; 12036af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson int32_t tmp = (int32_t)MO2.getImm(); 12046af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson if (tmp < 0) 12056af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson tmp = abs(tmp); 12066af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson else 12076af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson Value |= 256; // Set the ADD bit 12086af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson Value |= tmp & 255; 12096af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson return Value; 12106af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson} 12116af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson 12126af50f7dd12d82f0a80f3158102180eee4c921aaOwen Andersonunsigned ARMMCCodeEmitter:: 12136af50f7dd12d82f0a80f3158102180eee4c921aaOwen AndersongetT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 12146af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 12156af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson const MCOperand &MO1 = MI.getOperand(OpNum); 12166af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson 12176af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson // FIXME: Needs fixup support. 12186af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson unsigned Value = 0; 12196af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson int32_t tmp = (int32_t)MO1.getImm(); 12206af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson if (tmp < 0) 12216af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson tmp = abs(tmp); 12226af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson else 12236af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson Value |= 256; // Set the ADD bit 12246af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson Value |= tmp & 255; 122575579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson return Value; 122675579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson} 122775579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson 122875579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Andersonunsigned ARMMCCodeEmitter:: 12290e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen AndersongetT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 12300e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 12310e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson const MCOperand &MO1 = MI.getOperand(OpNum); 12320e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson 12330e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson // FIXME: Needs fixup support. 12340e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson unsigned Value = 0; 12350e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson int32_t tmp = (int32_t)MO1.getImm(); 12360e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson if (tmp < 0) 12370e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson tmp = abs(tmp); 12380e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson else 12390e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson Value |= 4096; // Set the ADD bit 12400e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson Value |= tmp & 4095; 12410e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson return Value; 12420e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson} 12430e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson 12440e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Andersonunsigned ARMMCCodeEmitter:: 12455de6d841a5116152793dcab35a2e534a6a9aaa7aOwen AndersongetT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 12465de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 12475de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 12485de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // shifted. The second is the amount to shift by. 12495de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // 12505de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // {3-0} = Rm. 12515de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // {4} = 0 12525de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // {6-5} = type 12535de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // {11-7} = imm 12545de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 12555de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson const MCOperand &MO = MI.getOperand(OpIdx); 12565de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 12575de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 12585de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 12595de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Encode Rm. 12605de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned Binary = getARMRegisterNumbering(MO.getReg()); 12615de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 12625de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Encode the shift opcode. 12635de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned SBits = 0; 12645de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Set shift operand (bit[6:4]). 12655de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // LSL - 000 12665de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // LSR - 010 12675de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // ASR - 100 12685de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // ROR - 110 12695de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson switch (SOpc) { 12705de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson default: llvm_unreachable("Unknown shift opc!"); 12715de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson case ARM_AM::lsl: SBits = 0x0; break; 12725de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson case ARM_AM::lsr: SBits = 0x2; break; 12735de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson case ARM_AM::asr: SBits = 0x4; break; 12745de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson case ARM_AM::ror: SBits = 0x6; break; 12755de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson } 12765de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 12775de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson Binary |= SBits << 4; 12785de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson if (SOpc == ARM_AM::rrx) 12795de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson return Binary; 12805de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 12815de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Encode shift_imm bit[11:7]. 12825de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 12835de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson} 12845de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 12855de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Andersonunsigned ARMMCCodeEmitter:: 1286806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1287806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 12883fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the 12893fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach // msb of the mask. 12903fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach const MCOperand &MO = MI.getOperand(Op); 12913fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach uint32_t v = ~MO.getImm(); 12923fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach uint32_t lsb = CountTrailingZeros_32(v); 12933fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1; 12943fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 12953fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach return lsb | (msb << 5); 12963fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach} 12973fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach 1298806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 1299a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso LopesgetMsbOpValue(const MCInst &MI, unsigned Op, 1300a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes SmallVectorImpl<MCFixup> &Fixups) const { 1301a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes // MSB - 5 bits. 1302a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes uint32_t lsb = MI.getOperand(Op-1).getImm(); 1303a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes uint32_t width = MI.getOperand(Op).getImm(); 1304a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes uint32_t msb = lsb+width-1; 1305a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes assert (width != 0 && msb < 32 && "Illegal bit width!"); 1306a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes return msb; 1307a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes} 1308a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes 1309a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopesunsigned ARMMCCodeEmitter:: 1310806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetRegisterListOpValue(const MCInst &MI, unsigned Op, 13115e559a22c18166508a01fbd65471ec4e752726f9Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 13126bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // VLDM/VSTM: 13136bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // {12-8} = Vd 13146bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // {7-0} = Number of registers 13156bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // 13166bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // LDM/STM: 13176bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // {15-0} = Bitfield of GPRs. 13186bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling unsigned Reg = MI.getOperand(Op).getReg(); 1319be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1320be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 13216bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling 13225e559a22c18166508a01fbd65471ec4e752726f9Bill Wendling unsigned Binary = 0; 13236bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling 13246bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling if (SPRRegs || DPRRegs) { 13256bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // VLDM/VSTM 13266bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling unsigned RegNo = getARMRegisterNumbering(Reg); 13276bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 13286bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling Binary |= (RegNo & 0x1f) << 8; 13296bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling if (SPRRegs) 13306bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling Binary |= NumRegs; 13316bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling else 13326bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling Binary |= NumRegs * 2; 13336bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling } else { 13346bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 13356bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg()); 13366bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling Binary |= 1 << RegNo; 13376bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling } 13385e559a22c18166508a01fbd65471ec4e752726f9Bill Wendling } 13396bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling 13406b5252db2db5eeeadec4602329ac56beb6dea54aJim Grosbach return Binary; 13416b5252db2db5eeeadec4602329ac56beb6dea54aJim Grosbach} 13426b5252db2db5eeeadec4602329ac56beb6dea54aJim Grosbach 13438e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 13448e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// with the alignment operand. 1345806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 1346806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1347806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 1348d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson const MCOperand &Reg = MI.getOperand(Op); 13490800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling const MCOperand &Imm = MI.getOperand(Op + 1); 135035b2de012d9404e3e9e4373e45f41711f752dd3aJim Grosbach 1351d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 13520800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling unsigned Align = 0; 13530800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling 13540800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling switch (Imm.getImm()) { 13550800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling default: break; 13560800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 2: 13570800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 4: 13580800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 8: Align = 0x01; break; 13590800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 16: Align = 0x02; break; 13600800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 32: Align = 0x03; break; 1361d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson } 13620800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling 1363d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson return RegNo | (Align << 4); 1364d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson} 1365d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson 1366183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1367183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang/// along with the alignment operand for use in VST1 and VLD1 with size 32. 1368183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wangunsigned ARMMCCodeEmitter:: 1369183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P WanggetAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1370183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang SmallVectorImpl<MCFixup> &Fixups) const { 1371183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang const MCOperand &Reg = MI.getOperand(Op); 1372183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang const MCOperand &Imm = MI.getOperand(Op + 1); 1373183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 1374183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 1375183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang unsigned Align = 0; 1376183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 1377183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang switch (Imm.getImm()) { 1378183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang default: break; 1379183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 2: 1380183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 4: 1381183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 8: 1382183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 16: Align = 0x00; break; 1383183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 32: Align = 0x03; break; 1384183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang } 1385183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 1386183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang return RegNo | (Align << 4); 1387183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang} 1388183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 1389183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 13908e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 13918e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// alignment operand for use in VLD-dup instructions. This is the same as 13928e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// getAddrMode6AddressOpValue except for the alignment encoding, which is 13938e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// different for VLD4-dup. 13948e0c7b52877983b4838e54e233449912fc1a2325Bob Wilsonunsigned ARMMCCodeEmitter:: 13958e0c7b52877983b4838e54e233449912fc1a2325Bob WilsongetAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 13968e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson SmallVectorImpl<MCFixup> &Fixups) const { 13978e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson const MCOperand &Reg = MI.getOperand(Op); 13988e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson const MCOperand &Imm = MI.getOperand(Op + 1); 13998e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson 14008e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 14018e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson unsigned Align = 0; 14028e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson 14038e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson switch (Imm.getImm()) { 14048e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson default: break; 14058e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson case 2: 14068e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson case 4: 14078e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson case 8: Align = 0x01; break; 14088e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson case 16: Align = 0x03; break; 14098e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson } 14108e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson 14118e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson return RegNo | (Align << 4); 14128e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson} 14138e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson 1414806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 1415806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1416806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 14170800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling const MCOperand &MO = MI.getOperand(Op); 14180800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling if (MO.getReg() == 0) return 0x0D; 14190800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling return MO.getReg(); 1420a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling} 1421a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling 1422a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendlingunsigned ARMMCCodeEmitter:: 14233116dce33840a115130c5f8ffcb9679d023496d6Bill WendlinggetShiftRight8Imm(const MCInst &MI, unsigned Op, 14243116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 1425a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling return 8 - MI.getOperand(Op).getImm(); 1426a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling} 1427a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling 1428a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendlingunsigned ARMMCCodeEmitter:: 14293116dce33840a115130c5f8ffcb9679d023496d6Bill WendlinggetShiftRight16Imm(const MCInst &MI, unsigned Op, 14303116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 1431a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling return 16 - MI.getOperand(Op).getImm(); 1432a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling} 1433a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling 1434a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendlingunsigned ARMMCCodeEmitter:: 14353116dce33840a115130c5f8ffcb9679d023496d6Bill WendlinggetShiftRight32Imm(const MCInst &MI, unsigned Op, 14363116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 1437a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling return 32 - MI.getOperand(Op).getImm(); 14383116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling} 14393116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling 14403116dce33840a115130c5f8ffcb9679d023496d6Bill Wendlingunsigned ARMMCCodeEmitter:: 14413116dce33840a115130c5f8ffcb9679d023496d6Bill WendlinggetShiftRight64Imm(const MCInst &MI, unsigned Op, 14423116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 14433116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling return 64 - MI.getOperand(Op).getImm(); 1444cf667be17b479fe276fd606b8fd72ccfa3065bb8Owen Anderson} 1445cf667be17b479fe276fd606b8fd72ccfa3065bb8Owen Anderson 1446568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachvoid ARMMCCodeEmitter:: 1447568eeedea72c274abbba1310c18a31eef78e14a4Jim GrosbachEncodeInstruction(const MCInst &MI, raw_ostream &OS, 1448806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 1449d6d4b42ba473657b6d30242962f0d0fb23fe126eJim Grosbach // Pseudo instructions don't get encoded. 145059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1451e50e6bcd901ebb1cfc42fe9ca0796ae303d7f1a1Jim Grosbach uint64_t TSFlags = Desc.TSFlags; 1452e50e6bcd901ebb1cfc42fe9ca0796ae303d7f1a1Jim Grosbach if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1453d6d4b42ba473657b6d30242962f0d0fb23fe126eJim Grosbach return; 145416884415db751c75f2133bd04921393c792b1158Owen Anderson 1455e50e6bcd901ebb1cfc42fe9ca0796ae303d7f1a1Jim Grosbach int Size; 145616884415db751c75f2133bd04921393c792b1158Owen Anderson if (Desc.getSize() == 2 || Desc.getSize() == 4) 145716884415db751c75f2133bd04921393c792b1158Owen Anderson Size = Desc.getSize(); 145816884415db751c75f2133bd04921393c792b1158Owen Anderson else 145916884415db751c75f2133bd04921393c792b1158Owen Anderson llvm_unreachable("Unexpected instruction size!"); 146010096dbdef22a10a6a4444437c935ab428545525Owen Anderson 1461d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); 14627597212abced110723f2fee985a7d60557c092ecEvan Cheng // Thumb 32-bit wide instructions need to emit the high order halfword 14637597212abced110723f2fee985a7d60557c092ecEvan Cheng // first. 146459ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb() && Size == 4) { 1465d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach EmitConstant(Binary >> 16, 2, OS); 1466d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach EmitConstant(Binary & 0xffff, 2, OS); 1467d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach } else 1468d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach EmitConstant(Binary, Size, OS); 14697292e0a6564bb24707eff1c49da9044dd5eaec78Bill Wendling ++MCNumEmitted; // Keep track of the # of mi's emitted. 1470568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach} 14719af82ba42b53905f580f8c4270626946e3548654Jim Grosbach 1472806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach#include "ARMGenMCCodeEmitter.inc" 1473