ARMMCCodeEmitter.cpp revision a7710edd98d71a81c43f8e3889cf0c790885d1b8
1568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 3568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// The LLVM Compiler Infrastructure 4568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 5568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// This file is distributed under the University of Illinois Open Source 6568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// License. See LICENSE.TXT for details. 7568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 8568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach//===----------------------------------------------------------------------===// 9568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 10568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// This file implements the ARMMCCodeEmitter class. 11568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach// 12568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach//===----------------------------------------------------------------------===// 13568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 142ac190238e88b21e716e2853900b5076c9013410Chris Lattner#define DEBUG_TYPE "mccodeemitter" 15ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 16be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "MCTargetDesc/ARMBaseInfo.h" 17be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "MCTargetDesc/ARMFixupKinds.h" 18ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMMCExpr.h" 19be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "MCTargetDesc/ARMMCTargetDesc.h" 20568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach#include "llvm/MC/MCCodeEmitter.h" 21568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach#include "llvm/MC/MCExpr.h" 22568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach#include "llvm/MC/MCInst.h" 2359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "llvm/MC/MCInstrInfo.h" 24be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "llvm/MC/MCRegisterInfo.h" 2559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "llvm/MC/MCSubtargetInfo.h" 26ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/ADT/APFloat.h" 27d6d4b42ba473657b6d30242962f0d0fb23fe126eJim Grosbach#include "llvm/ADT/Statistic.h" 28568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach#include "llvm/Support/raw_ostream.h" 2959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng 30568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachusing namespace llvm; 31568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 3270933266ae73c891d9d1c2f0de72ecd1db8f86dfJim GrosbachSTATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 3370933266ae73c891d9d1c2f0de72ecd1db8f86dfJim GrosbachSTATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 34d6d4b42ba473657b6d30242962f0d0fb23fe126eJim Grosbach 35568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachnamespace { 36568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachclass ARMMCCodeEmitter : public MCCodeEmitter { 37568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT 38568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT 3959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng const MCInstrInfo &MCII; 4059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng const MCSubtargetInfo &STI; 41568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 42568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachpublic: 4359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 4459ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng MCContext &ctx) 45af0a2e6730ffb59405352269e1500b6e83e42d6aEvan Cheng : MCII(mcii), STI(sti) { 46568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach } 47568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 48568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach ~ARMMCCodeEmitter() {} 49568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 5059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng bool isThumb() const { 5159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng // FIXME: Can tablegen auto-generate this? 5259ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 5359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng } 5459ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng bool isThumb2() const { 5559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; 5659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng } 5759ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng bool isTargetDarwin() const { 5859ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Triple TT(STI.getTargetTriple()); 5959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Triple::OSType OS = TT.getOS(); 6059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS; 6159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng } 6259ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng 630de6ab3c43ed2143d661115dddf1480545236c91Jim Grosbach unsigned getMachineSoImmOpValue(unsigned SoImm) const; 640de6ab3c43ed2143d661115dddf1480545236c91Jim Grosbach 659af82ba42b53905f580f8c4270626946e3548654Jim Grosbach // getBinaryCodeForInstr - TableGen'erated function for getting the 669af82ba42b53905f580f8c4270626946e3548654Jim Grosbach // binary encoding for an instruction. 67806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getBinaryCodeForInstr(const MCInst &MI, 68806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 699af82ba42b53905f580f8c4270626946e3548654Jim Grosbach 709af82ba42b53905f580f8c4270626946e3548654Jim Grosbach /// getMachineOpValue - Return binary encoding of operand. If the machine 719af82ba42b53905f580f8c4270626946e3548654Jim Grosbach /// operand requires relocation, record the relocation and return zero. 72806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 73806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 749af82ba42b53905f580f8c4270626946e3548654Jim Grosbach 757597212abced110723f2fee985a7d60557c092ecEvan Cheng /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 76971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson /// the specified operand. This is used for operands with :lower16: and 777597212abced110723f2fee985a7d60557c092ecEvan Cheng /// :upper16: prefixes. 787597212abced110723f2fee985a7d60557c092ecEvan Cheng uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 797597212abced110723f2fee985a7d60557c092ecEvan Cheng SmallVectorImpl<MCFixup> &Fixups) const; 80837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim 8192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 82806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned &Reg, unsigned &Imm, 83806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 8492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 85662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 8609aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling /// BL branch target. 87662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 88662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 89662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach 9009aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 9109aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling /// BLX branch target. 9209aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 9309aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 9409aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling 95e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 96e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 97e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 98e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach 9901086451393ef33e82b6fad623989dd97dd70edfJim Grosbach /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 10001086451393ef33e82b6fad623989dd97dd70edfJim Grosbach uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 10101086451393ef33e82b6fad623989dd97dd70edfJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 10201086451393ef33e82b6fad623989dd97dd70edfJim Grosbach 103027d6e8d1ca04e4096fb3a27579b861d861466c5Jim Grosbach /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 104027d6e8d1ca04e4096fb3a27579b861d861466c5Jim Grosbach uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 105dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 106dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling 107c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 108c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach /// branch target. 109c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 110c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 111c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach 112c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 113c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson /// immediate Thumb2 direct branch target. 114c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 115c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 11610096dbdef22a10a6a4444437c935ab428545525Owen Anderson 117685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 118685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim /// branch target. 119685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 120685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim SmallVectorImpl<MCFixup> &Fixups) const; 121f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 122f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 123c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson 1245d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 1255d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach /// ADR label target. 1265d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 1275d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 128d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 129d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 130a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 131a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 132971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson 1335d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach 13492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 13592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling /// operand. 136806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 137806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 13892b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 139f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 140f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 141f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling SmallVectorImpl<MCFixup> &Fixups)const; 1420f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson 1439d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 1449d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson /// operand. 1459d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 1469d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 1479d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 1489d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 14954fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 15054fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach /// operand as needed by load/store instructions. 15154fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 15254fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 15354fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach 1545d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 1555d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 1565d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 1575d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 1585d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach switch (Mode) { 1595f8a917b6558f8fdf31b4a6fa591b396e16b9ff2Matt Beaumont-Gay default: assert(0 && "Unknown addressing sub-mode!"); 1605d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach case ARM_AM::da: return 0; 1615d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach case ARM_AM::ia: return 1; 1625d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach case ARM_AM::db: return 2; 1635d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach case ARM_AM::ib: return 3; 1645d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach } 1655d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach } 16699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 16799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach /// 16899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 16999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach switch (ShOpc) { 17099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach default: llvm_unreachable("Unknown shift opc!"); 17199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::no_shift: 17299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::lsl: return 0; 17399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::lsr: return 1; 17499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::asr: return 2; 17599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::ror: 17699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach case ARM_AM::rrx: return 3; 17799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach } 17899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach return 0; 17999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach } 18099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 18199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach /// getAddrMode2OpValue - Return encoding for addrmode2 operands. 18299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 18399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 18499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 18599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 18699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 18799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 18899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 1897ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 1907ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 1917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 1927ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 1937eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 1947eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1957eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 1967eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach 197570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 198570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 199570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2005d5eb9e3817a2765297e6dd5649ecb9b8b03e334Jim Grosbach 201d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 202d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach /// operand. 203d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 204d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 205d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach 206f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 207f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 20822447ae54bcb8ca94ed994cad103074a24e66781Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 2091fd374e9c1c074c1681336bef31e65f0170b0f7eBill Wendling 210b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 211b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 212b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 213b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling 21492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. 215806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 216806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2173e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach 21808bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach /// getCCOutOpValue - Return encoding of the 's' bit. 219806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 220806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 22108bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 22208bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach // '1' respectively. 22308bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach return MI.getOperand(Op).getReg() == ARM::CPSR; 22408bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach } 225ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 2262a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. 227806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, 228806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 2292a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach unsigned SoImm = MI.getOperand(Op).getImm(); 2302a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach int SoImmVal = ARM_AM::getSOImmVal(SoImm); 2312a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach assert(SoImmVal != -1 && "Not a valid so_imm value!"); 2322a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach 2332a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach // Encode rotate_imm. 2342a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 2352a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach << ARMII::SoRotImmShift; 2362a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach 2372a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach // Encode immed_8. 2382a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 2392a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach return Binary; 2402a6a93d5425b38546de2b6674719d52f565171d8Jim Grosbach } 2417bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 2425de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 2435de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 2445de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 2455de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned SoImm = MI.getOperand(Op).getImm(); 2465de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 2475de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 2485de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson return Encoded; 2495de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson } 25008bd54987f4ae482de13436e7254ff08b23f825fJim Grosbach 25175579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 25275579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 25375579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 25475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 2556af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 2566af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 2570e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 2580e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 25975579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson 260ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach /// getSORegOpValue - Return an encoded so_reg shifted register value. 261152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 262152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 263152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 264806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2655de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 2665de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 267ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 268806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 269806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 270498ec20703c89d0c2890b0967791f0f5f2b59a2fOwen Anderson return 64 - MI.getOperand(Op).getImm(); 271498ec20703c89d0c2890b0967791f0f5f2b59a2fOwen Anderson } 2728abe32af38b66bf4577526b23b6af6ec7eb6c155Jim Grosbach 273806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 274806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2753fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach 276a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes unsigned getMsbOpValue(const MCInst &MI, unsigned Op, 277a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes SmallVectorImpl<MCFixup> &Fixups) const; 278a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes 279806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 280806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 281806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 282806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 283183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 284183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang SmallVectorImpl<MCFixup> &Fixups) const; 2858e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 2868e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson SmallVectorImpl<MCFixup> &Fixups) const; 287806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 288806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 2896b5252db2db5eeeadec4602329ac56beb6dea54aJim Grosbach 2903116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 2913116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 2923116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 2933116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 2943116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 2953116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 2963116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 2973116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const; 298a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling 2996d74631062e4464326eb5c680a4d62d340fa42ebOwen Anderson unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 3006d74631062e4464326eb5c680a4d62d340fa42ebOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const; 3016d74631062e4464326eb5c680a4d62d340fa42ebOwen Anderson 302c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 303c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned EncodedValue) const; 30457dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 305cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling unsigned EncodedValue) const; 3068f143913141991baaa535ca0da7c8a81606d6392Owen Anderson unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 307cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling unsigned EncodedValue) const; 308cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling 309cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling unsigned VFPThumb2PostEncoder(const MCInst &MI, 310cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling unsigned EncodedValue) const; 311c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson 31270933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach void EmitByte(unsigned char C, raw_ostream &OS) const { 313568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach OS << (char)C; 314568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach } 315568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 31670933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 317568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach // Output the constant in little endian byte order. 318568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach for (unsigned i = 0; i != Size; ++i) { 31970933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach EmitByte(Val & 255, OS); 320568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach Val >>= 8; 321568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach } 322568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach } 323568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 324568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 325568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const; 326568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach}; 327568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 328568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach} // end anonymous namespace 329568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 33059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan ChengMCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII, 33159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng const MCSubtargetInfo &STI, 3320800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling MCContext &Ctx) { 33359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng return new ARMMCCodeEmitter(MCII, STI, Ctx); 334568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach} 335568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach 3367bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 3377bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach/// instructions, and rewrite them to their Thumb2 form if we are currently in 338c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson/// Thumb2 mode. 339c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Andersonunsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 340c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned EncodedValue) const { 34159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) { 3427bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 343c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 344c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson // set to 1111. 345c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned Bit24 = EncodedValue & 0x01000000; 346c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson unsigned Bit28 = Bit24 << 4; 347c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson EncodedValue &= 0xEFFFFFFF; 348c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson EncodedValue |= Bit28; 349c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson EncodedValue |= 0x0F000000; 350c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson } 3517bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 352c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson return EncodedValue; 353c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson} 354c7139a6f0d3acd198ab9eb536ea1ec52e61ff130Owen Anderson 35557dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 3567bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach/// instructions, and rewrite them to their Thumb2 form if we are currently in 35757dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson/// Thumb2 mode. 35857dac88f775c1191a98cff89abd1f7ad33df5e29Owen Andersonunsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 35957dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson unsigned EncodedValue) const { 36059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) { 36157dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson EncodedValue &= 0xF0FFFFFF; 36257dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson EncodedValue |= 0x09000000; 36357dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson } 3647bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 36557dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson return EncodedValue; 36657dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson} 36757dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson 3688f143913141991baaa535ca0da7c8a81606d6392Owen Anderson/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 3697bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach/// instructions, and rewrite them to their Thumb2 form if we are currently in 3708f143913141991baaa535ca0da7c8a81606d6392Owen Anderson/// Thumb2 mode. 3718f143913141991baaa535ca0da7c8a81606d6392Owen Andersonunsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 3728f143913141991baaa535ca0da7c8a81606d6392Owen Anderson unsigned EncodedValue) const { 37359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) { 3748f143913141991baaa535ca0da7c8a81606d6392Owen Anderson EncodedValue &= 0x00FFFFFF; 3758f143913141991baaa535ca0da7c8a81606d6392Owen Anderson EncodedValue |= 0xEE000000; 3768f143913141991baaa535ca0da7c8a81606d6392Owen Anderson } 3777bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 3788f143913141991baaa535ca0da7c8a81606d6392Owen Anderson return EncodedValue; 3798f143913141991baaa535ca0da7c8a81606d6392Owen Anderson} 3808f143913141991baaa535ca0da7c8a81606d6392Owen Anderson 381cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 382cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling/// them to their Thumb2 form if we are currently in Thumb2 mode. 383cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendlingunsigned ARMMCCodeEmitter:: 384cf590263cd5c24ccf1d08cef612738d99cd980d9Bill WendlingVFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { 38559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) { 386cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling EncodedValue &= 0x0FFFFFFF; 387cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling EncodedValue |= 0xE0000000; 388cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling } 389cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling return EncodedValue; 390cf590263cd5c24ccf1d08cef612738d99cd980d9Bill Wendling} 39157dac88f775c1191a98cff89abd1f7ad33df5e29Owen Anderson 39256ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach/// getMachineOpValue - Return binary encoding of operand. If the machine 39356ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach/// operand requires relocation, record the relocation and return zero. 394806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 395806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetMachineOpValue(const MCInst &MI, const MCOperand &MO, 396806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 397bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling if (MO.isReg()) { 3980800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling unsigned Reg = MO.getReg(); 3990800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling unsigned RegNo = getARMRegisterNumbering(Reg); 400d8a11c25fa64c152628cfcf5f9d36eb60242b302Jim Grosbach 401b0708d292bbe04cfcfe0c5cb5e27d8a872c9839aJim Grosbach // Q registers are encoded as 2x their register number. 4020800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling switch (Reg) { 4030800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling default: 4040800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling return RegNo; 4050800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 4060800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 4070800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 4080800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 4090800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling return 2 * RegNo; 41090d4cf931477b497553a9f2d0ed53377dd5dd88cOwen Anderson } 411bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling } else if (MO.isImm()) { 41256ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach return static_cast<unsigned>(MO.getImm()); 413bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling } else if (MO.isFPImm()) { 414bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling return static_cast<unsigned>(APFloat(MO.getFPImm()) 415bbbdcd453d22258cb4dd217eddf016668fcebf84Bill Wendling .bitcastToAPInt().getHiBits(32).getLimitedValue()); 4160800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling } 4170800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling 418817c1a6dddadb4664738777d224bc7eae6e62cf3Jim Grosbach llvm_unreachable("Unable to encode MCOperand!"); 41956ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach return 0; 42056ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach} 42156ac907c57fcfddfd650238f03c856a9d55987e5Jim Grosbach 4225df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0adBill Wendling/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 423806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachbool ARMMCCodeEmitter:: 424806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachEncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 425806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const { 4263e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 4273e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 4289af3d1c0dc2250793ada1ca6cfa98e9f1253f7f9Jim Grosbach 42992b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Reg = getARMRegisterNumbering(MO.getReg()); 43092b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 43192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling int32_t SImm = MO1.getImm(); 43292b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling bool isAdd = true; 4335df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0adBill Wendling 434ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach // Special value for #-0 4350da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson if (SImm == INT32_MIN) { 43692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling SImm = 0; 4370da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson isAdd = false; 4380da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson } 4395df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0adBill Wendling 440ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 44192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling if (SImm < 0) { 44292b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling SImm = -SImm; 44392b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling isAdd = false; 44492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling } 44592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 44692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Imm = SImm; 44792b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling return isAdd; 44892b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling} 4495df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0adBill Wendling 450dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// getBranchTargetOpValue - Helper function to get the branch target operand, 451dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// which is either an immediate or requires a fixup. 452dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendlingstatic uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 453dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling unsigned FixupKind, 454dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling SmallVectorImpl<MCFixup> &Fixups) { 455662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 456662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach 457662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach // If the destination is an immediate, we have nothing to do. 458662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach if (MO.isImm()) return MO.getImm(); 459dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling assert(MO.isExpr() && "Unexpected branch target type!"); 460662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach const MCExpr *Expr = MO.getExpr(); 461dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling MCFixupKind Kind = MCFixupKind(FixupKind); 462662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 463662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach 464662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach // All of the information is in the fixup. 465662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach return 0; 466662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach} 467662a816e89a9d77bf75e1328b09cf9235b4682aaJim Grosbach 468dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 469c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbachuint32_t ARMMCCodeEmitter:: 470dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill WendlinggetThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 471c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 472dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups); 473dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling} 474c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach 47509aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 47609aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling/// BLX branch target. 47709aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendlinguint32_t ARMMCCodeEmitter:: 47809aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill WendlinggetThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 47909aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 48009aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups); 48109aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling} 48209aa3f0ef35d9241c92439d74b8d5e9a81d814c2Bill Wendling 483e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 484e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbachuint32_t ARMMCCodeEmitter:: 485e246717c3a36a913fd4200776ed621649bb2b624Jim GrosbachgetThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 486e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 487391ac65377f2ad5e48a796e75120959e22430605Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 488391ac65377f2ad5e48a796e75120959e22430605Owen Anderson if (MO.isExpr()) 489391ac65377f2ad5e48a796e75120959e22430605Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups); 490391ac65377f2ad5e48a796e75120959e22430605Owen Anderson return (MO.getImm() >> 1); 491e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach} 492e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach 49301086451393ef33e82b6fad623989dd97dd70edfJim Grosbach/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 49401086451393ef33e82b6fad623989dd97dd70edfJim Grosbachuint32_t ARMMCCodeEmitter:: 49501086451393ef33e82b6fad623989dd97dd70edfJim GrosbachgetThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 496e246717c3a36a913fd4200776ed621649bb2b624Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 49701086451393ef33e82b6fad623989dd97dd70edfJim Grosbach return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups); 49801086451393ef33e82b6fad623989dd97dd70edfJim Grosbach} 49901086451393ef33e82b6fad623989dd97dd70edfJim Grosbach 500027d6e8d1ca04e4096fb3a27579b861d861466c5Jim Grosbach/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 501dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendlinguint32_t ARMMCCodeEmitter:: 502027d6e8d1ca04e4096fb3a27579b861d861466c5Jim GrosbachgetThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 503dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 504b492a7c2134d3886f545f1b5ea55115d71529a10Jim Grosbach return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); 505dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling} 506c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach 507685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim/// Return true if this branch has a non-always predication 508685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kimstatic bool HasConditionalBranch(const MCInst &MI) { 509685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim int NumOp = MI.getNumOperands(); 510685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim if (NumOp >= 2) { 511685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim for (int i = 0; i < NumOp-1; ++i) { 512685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim const MCOperand &MCOp1 = MI.getOperand(i); 513685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim const MCOperand &MCOp2 = MI.getOperand(i + 1); 51410096dbdef22a10a6a4444437c935ab428545525Owen Anderson if (MCOp1.isImm() && MCOp2.isReg() && 515685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 51610096dbdef22a10a6a4444437c935ab428545525Owen Anderson if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 517685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim return true; 518685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim } 519685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim } 520685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim } 521685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim return false; 522685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim} 523685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim 524dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 525dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// target. 526dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendlinguint32_t ARMMCCodeEmitter:: 527dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill WendlinggetBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 528dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 529092e2cd5693114a4f1d93eb5b72f3e194de27236Jim Grosbach // FIXME: This really, really shouldn't use TargetMachine. We don't want 530092e2cd5693114a4f1d93eb5b72f3e194de27236Jim Grosbach // coupling between MC and TM anywhere we can help it. 53159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) 532c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson return 533c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); 534685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim return getARMBranchTargetOpValue(MI, OpIdx, Fixups); 535685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim} 536685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim 537685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 538685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim/// target. 539685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kimuint32_t ARMMCCodeEmitter:: 540685c350ae76b588e1f00c01a511fe8bd57f18394Jason W KimgetARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 541685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim SmallVectorImpl<MCFixup> &Fixups) const { 542d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 543d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson if (MO.isExpr()) { 54410096dbdef22a10a6a4444437c935ab428545525Owen Anderson if (HasConditionalBranch(MI)) 545d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, 546d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson ARM::fixup_arm_condbranch, Fixups); 54710096dbdef22a10a6a4444437c935ab428545525Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, 548d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson ARM::fixup_arm_uncondbranch, Fixups); 549d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson } 550d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson 551d7568e1c355f5e364eddafc15c6d5553559f32a5Owen Anderson return MO.getImm() >> 2; 552c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach} 553c466b937dbdbaabeef0097fe340de1b8f49a3508Jim Grosbach 554f1eab597b2316c6cfcabfcee98895fedb2071722Owen Andersonuint32_t ARMMCCodeEmitter:: 555f1eab597b2316c6cfcabfcee98895fedb2071722Owen AndersongetARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 556f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 557f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 558f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson if (MO.isExpr()) { 55910096dbdef22a10a6a4444437c935ab428545525Owen Anderson if (HasConditionalBranch(MI)) 560f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, 561f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson ARM::fixup_arm_condbranch, Fixups); 56210096dbdef22a10a6a4444437c935ab428545525Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, 563f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson ARM::fixup_arm_uncondbranch, Fixups); 564f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson } 565685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim 566f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson return MO.getImm() >> 1; 567f1eab597b2316c6cfcabfcee98895fedb2071722Owen Anderson} 568685c350ae76b588e1f00c01a511fe8bd57f18394Jason W Kim 569c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 570c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson/// immediate branch target. 571c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Andersonuint32_t ARMMCCodeEmitter:: 572c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen AndersongetUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 573c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 574c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson unsigned Val = 575c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups); 576c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson bool I = (Val & 0x800000); 577c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson bool J1 = (Val & 0x400000); 578c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson bool J2 = (Val & 0x200000); 579c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson if (I ^ J1) 580c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson Val &= ~0x400000; 581c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson else 582c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson Val |= 0x400000; 583971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson 584c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson if (I ^ J2) 585c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson Val &= ~0x200000; 586c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson else 587c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson Val |= 0x200000; 588971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson 589c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson return Val; 590c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson} 591c266600bec4b5ba0ee93ffdfeaafcab8f1295145Owen Anderson 592dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 593dff2f7151f695b86db8c4b0c6604463bdb8a63eaBill Wendling/// target. 5945d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbachuint32_t ARMMCCodeEmitter:: 5955d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim GrosbachgetAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 5965d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 59796425c846494c1c20a4c931f4783571295ab170cOwen Anderson const MCOperand MO = MI.getOperand(OpIdx); 59896425c846494c1c20a4c931f4783571295ab170cOwen Anderson if (MO.isExpr()) 59996425c846494c1c20a4c931f4783571295ab170cOwen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 60096425c846494c1c20a4c931f4783571295ab170cOwen Anderson Fixups); 60196425c846494c1c20a4c931f4783571295ab170cOwen Anderson int32_t offset = MO.getImm(); 60296425c846494c1c20a4c931f4783571295ab170cOwen Anderson uint32_t Val = 0x2000; 60396425c846494c1c20a4c931f4783571295ab170cOwen Anderson if (offset < 0) { 60496425c846494c1c20a4c931f4783571295ab170cOwen Anderson Val = 0x1000; 60596425c846494c1c20a4c931f4783571295ab170cOwen Anderson offset *= -1; 60696425c846494c1c20a4c931f4783571295ab170cOwen Anderson } 60796425c846494c1c20a4c931f4783571295ab170cOwen Anderson Val |= offset; 60896425c846494c1c20a4c931f4783571295ab170cOwen Anderson return Val; 6095d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach} 6105d14f9be7ba64162c7b996f36d419b11d8cdbe9aJim Grosbach 611a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 612a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson/// target. 613a838a25d59838adfa91463f6a918ae3adeb352c1Owen Andersonuint32_t ARMMCCodeEmitter:: 614a838a25d59838adfa91463f6a918ae3adeb352c1Owen AndersongetT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 615a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 61696425c846494c1c20a4c931f4783571295ab170cOwen Anderson const MCOperand MO = MI.getOperand(OpIdx); 61796425c846494c1c20a4c931f4783571295ab170cOwen Anderson if (MO.isExpr()) 61896425c846494c1c20a4c931f4783571295ab170cOwen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 61996425c846494c1c20a4c931f4783571295ab170cOwen Anderson Fixups); 62096425c846494c1c20a4c931f4783571295ab170cOwen Anderson return MO.getImm(); 621a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson} 622a838a25d59838adfa91463f6a918ae3adeb352c1Owen Anderson 623d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 624d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach/// target. 625d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbachuint32_t ARMMCCodeEmitter:: 626d40963c4065432ec7e47879d3ca665a54ee903b6Jim GrosbachgetThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 627d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 62896425c846494c1c20a4c931f4783571295ab170cOwen Anderson const MCOperand MO = MI.getOperand(OpIdx); 62996425c846494c1c20a4c931f4783571295ab170cOwen Anderson if (MO.isExpr()) 63096425c846494c1c20a4c931f4783571295ab170cOwen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 63196425c846494c1c20a4c931f4783571295ab170cOwen Anderson Fixups); 63296425c846494c1c20a4c931f4783571295ab170cOwen Anderson return MO.getImm(); 633d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach} 634d40963c4065432ec7e47879d3ca665a54ee903b6Jim Grosbach 635f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 636f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling/// operand. 6370f4b60d43a289671082deee3bd56a3a055afb16aOwen Andersonuint32_t ARMMCCodeEmitter:: 638f4caf69720d807573c50d41aa06bcec1c99bdbbdBill WendlinggetThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 639f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling SmallVectorImpl<MCFixup> &) const { 640f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling // [Rn, Rm] 641f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling // {5-3} = Rm 642f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling // {2-0} = Rn 6430f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson const MCOperand &MO1 = MI.getOperand(OpIdx); 644f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 6450f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson unsigned Rn = getARMRegisterNumbering(MO1.getReg()); 6460f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson unsigned Rm = getARMRegisterNumbering(MO2.getReg()); 6470f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson return (Rm << 3) | Rn; 6480f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson} 6490f4b60d43a289671082deee3bd56a3a055afb16aOwen Anderson 65092b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 651806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachuint32_t ARMMCCodeEmitter:: 652806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 653806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 65492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {17-13} = reg 65592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {12} = (U)nsigned (add == '1', sub == '0') 65692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {11-0} = imm12 65792b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling unsigned Reg, Imm12; 65870933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach bool isAdd = true; 65970933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach // If The first operand isn't a register, we have a label reference. 66070933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 661971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson if (!MO.isReg()) { 662679cbd3b215b1769a6035e334f9009aeeb940dddJim Grosbach Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 66370933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach Imm12 = 0; 66497dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach isAdd = false ; // 'U' bit is set as part of the fixup. 66570933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach 666971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson assert(MO.isExpr() && "Unexpected machine operand type!"); 667971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson const MCExpr *Expr = MO.getExpr(); 6687bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 669d7b3f5870d9d04351d9cd363d9d6af01482a2eb8Owen Anderson MCFixupKind Kind; 67059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) 671d7b3f5870d9d04351d9cd363d9d6af01482a2eb8Owen Anderson Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 672d7b3f5870d9d04351d9cd363d9d6af01482a2eb8Owen Anderson else 673d7b3f5870d9d04351d9cd363d9d6af01482a2eb8Owen Anderson Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 67470933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 67570933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach 67670933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach ++MCNumCPRelocations; 67770933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach } else 67870933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); 67992b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 68092b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling uint32_t Binary = Imm12 & 0xfff; 68192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 682ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach if (isAdd) 68392b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Binary |= (1 << 12); 68492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Binary |= (Reg << 13); 68592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling return Binary; 68692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling} 68792b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 6889d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson/// getT2AddrModeImm8s4OpValue - Return encoding info for 6899d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson/// 'reg +/- imm8<<2' operand. 6909d63d90de5e57ad96f467b270544443a9284eb2bOwen Andersonuint32_t ARMMCCodeEmitter:: 6919d63d90de5e57ad96f467b270544443a9284eb2bOwen AndersongetT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 6929d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 69390cc533fda9742f5c67203f97e69e5efd270c676Jim Grosbach // {12-9} = reg 69490cc533fda9742f5c67203f97e69e5efd270c676Jim Grosbach // {8} = (U)nsigned (add == '1', sub == '0') 69590cc533fda9742f5c67203f97e69e5efd270c676Jim Grosbach // {7-0} = imm8 6969d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson unsigned Reg, Imm8; 6979d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson bool isAdd = true; 6989d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson // If The first operand isn't a register, we have a label reference. 6999d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson const MCOperand &MO = MI.getOperand(OpIdx); 7009d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson if (!MO.isReg()) { 7019d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 7029d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson Imm8 = 0; 7039d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson isAdd = false ; // 'U' bit is set as part of the fixup. 7049d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 7059d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson assert(MO.isExpr() && "Unexpected machine operand type!"); 7069d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson const MCExpr *Expr = MO.getExpr(); 7079d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 7089d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 7099d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 7109d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson ++MCNumCPRelocations; 7119d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson } else 7129d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 7139d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 7149d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson uint32_t Binary = (Imm8 >> 2) & 0xff; 7159d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 7169d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson if (isAdd) 71790cc533fda9742f5c67203f97e69e5efd270c676Jim Grosbach Binary |= (1 << 8); 7189d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson Binary |= (Reg << 9); 7199d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson return Binary; 7209d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson} 7219d63d90de5e57ad96f467b270544443a9284eb2bOwen Anderson 72286a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// FIXME: This routine assumes that a binary 72386a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// expression will always result in a PCRel expression 72486a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// In reality, its only true if one or more subexpressions 72586a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// is itself a PCRel (i.e. "." in asm or some other pcrel construct) 72686a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim// but this is good enough for now. 72786a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kimstatic bool EvaluateAsPCRel(const MCExpr *Expr) { 72886a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim switch (Expr->getKind()) { 7295f8a917b6558f8fdf31b4a6fa591b396e16b9ff2Matt Beaumont-Gay default: assert(0 && "Unexpected expression type"); 73086a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim case MCExpr::SymbolRef: return false; 73186a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim case MCExpr::Binary: return true; 73286a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim } 73386a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim} 73486a97f2e4d0cde5e992f52ac287da0de687e0110Jason W Kim 7357597212abced110723f2fee985a7d60557c092ecEvan Chenguint32_t 7367597212abced110723f2fee985a7d60557c092ecEvan ChengARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 7377597212abced110723f2fee985a7d60557c092ecEvan Cheng SmallVectorImpl<MCFixup> &Fixups) const { 738837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim // {20-16} = imm{15-12} 739837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim // {11-0} = imm{11-0} 7407bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 7417597212abced110723f2fee985a7d60557c092ecEvan Cheng if (MO.isImm()) 7427597212abced110723f2fee985a7d60557c092ecEvan Cheng // Hi / lo 16 bits already extracted during earlier passes. 743837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim return static_cast<unsigned>(MO.getImm()); 7447597212abced110723f2fee985a7d60557c092ecEvan Cheng 7457597212abced110723f2fee985a7d60557c092ecEvan Cheng // Handle :upper16: and :lower16: assembly prefixes. 7467597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *E = MO.getExpr(); 7477597212abced110723f2fee985a7d60557c092ecEvan Cheng if (E->getKind() == MCExpr::Target) { 7487597212abced110723f2fee985a7d60557c092ecEvan Cheng const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 7497597212abced110723f2fee985a7d60557c092ecEvan Cheng E = ARM16Expr->getSubExpr(); 7507597212abced110723f2fee985a7d60557c092ecEvan Cheng 751837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim MCFixupKind Kind; 7527597212abced110723f2fee985a7d60557c092ecEvan Cheng switch (ARM16Expr->getKind()) { 7535f8a917b6558f8fdf31b4a6fa591b396e16b9ff2Matt Beaumont-Gay default: assert(0 && "Unsupported ARMFixup"); 7547597212abced110723f2fee985a7d60557c092ecEvan Cheng case ARMMCExpr::VK_ARM_HI16: 75559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (!isTargetDarwin() && EvaluateAsPCRel(E)) 75659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Kind = MCFixupKind(isThumb2() 757f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng ? ARM::fixup_t2_movt_hi16_pcrel 758f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng : ARM::fixup_arm_movt_hi16_pcrel); 759f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng else 76059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Kind = MCFixupKind(isThumb2() 761f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng ? ARM::fixup_t2_movt_hi16 762f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng : ARM::fixup_arm_movt_hi16); 763837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim break; 7647597212abced110723f2fee985a7d60557c092ecEvan Cheng case ARMMCExpr::VK_ARM_LO16: 76559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (!isTargetDarwin() && EvaluateAsPCRel(E)) 76659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Kind = MCFixupKind(isThumb2() 767f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng ? ARM::fixup_t2_movw_lo16_pcrel 768f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng : ARM::fixup_arm_movw_lo16_pcrel); 769f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng else 77059ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng Kind = MCFixupKind(isThumb2() 771f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng ? ARM::fixup_t2_movw_lo16 772f3eb3bba1614a7935b44fc963a805088d71267f3Evan Cheng : ARM::fixup_arm_movw_lo16); 773837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim break; 774837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim } 7757597212abced110723f2fee985a7d60557c092ecEvan Cheng Fixups.push_back(MCFixup::Create(0, E, Kind)); 776837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim return 0; 777817c1a6dddadb4664738777d224bc7eae6e62cf3Jim Grosbach }; 7787597212abced110723f2fee985a7d60557c092ecEvan Cheng 779817c1a6dddadb4664738777d224bc7eae6e62cf3Jim Grosbach llvm_unreachable("Unsupported MCExpr type in MCOperand!"); 780837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim return 0; 781837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim} 782837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kim 783837caa9313e1f9480721f232f89f5c7b1b9c9d09Jason W Kimuint32_t ARMMCCodeEmitter:: 78454fea632b161f98e96ec7275922e35102bcecc5dJim GrosbachgetLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 78554fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 78654fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 78754fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 78854fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach const MCOperand &MO2 = MI.getOperand(OpIdx+2); 78954fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach unsigned Rn = getARMRegisterNumbering(MO.getReg()); 79054fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach unsigned Rm = getARMRegisterNumbering(MO1.getReg()); 79154fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 79254fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 79399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 79499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach unsigned SBits = getShiftOp(ShOp); 79554fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach 79654fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {16-13} = Rn 79754fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {12} = isAdd 79854fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {11-0} = shifter 79954fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {3-0} = Rm 80054fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {4} = 0 80154fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {6-5} = type 80254fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach // {11-7} = imm 803570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach uint32_t Binary = Rm; 80454fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach Binary |= Rn << 13; 80554fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach Binary |= SBits << 5; 80654fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach Binary |= ShImm << 7; 80754fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach if (isAdd) 80854fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach Binary |= 1 << 12; 80954fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach return Binary; 81054fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach} 81154fea632b161f98e96ec7275922e35102bcecc5dJim Grosbach 812570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbachuint32_t ARMMCCodeEmitter:: 81399f53d13efc259b47c93dc0d90a5db763cbe371aJim GrosbachgetAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 81499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 81599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {17-14} Rn 81699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {13} 1 == imm12, 0 == Rm 81799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {12} isAdd 81899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {11-0} imm12/Rm 81999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 82099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach unsigned Rn = getARMRegisterNumbering(MO.getReg()); 82199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups); 82299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach Binary |= Rn << 14; 82399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach return Binary; 82499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach} 82599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 82699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbachuint32_t ARMMCCodeEmitter:: 82799f53d13efc259b47c93dc0d90a5db763cbe371aJim GrosbachgetAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 82899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 82999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {13} 1 == imm12, 0 == Rm 83099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {12} isAdd 83199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // {11-0} imm12/Rm 83299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 83399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 83499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach unsigned Imm = MO1.getImm(); 83599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 83699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach bool isReg = MO.getReg() != 0; 83799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach uint32_t Binary = ARM_AM::getAM2Offset(Imm); 83899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 83999f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach if (isReg) { 84099f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 84199f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach Binary <<= 7; // Shift amount is bits [11:7] 84299f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 84399f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0] 84499f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach } 84599f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach return Binary | (isAdd << 12) | (isReg << 13); 84699f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach} 84799f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbach 84899f53d13efc259b47c93dc0d90a5db763cbe371aJim Grosbachuint32_t ARMMCCodeEmitter:: 8497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachgetPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 8507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 8517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // {4} isAdd 8527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // {3-0} Rm 8537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 8547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 85516578b50889329eb62774148091ba0f38b681a09Jim Grosbach bool isAdd = MO1.getImm() != 0; 8567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4); 8577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 8587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 8597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachuint32_t ARMMCCodeEmitter:: 8607eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim GrosbachgetAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 8617eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 8627eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // {9} 1 == imm8, 0 == Rm 8637eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // {8} isAdd 8647eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // {7-4} imm7_4/zero 8657eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // {3-0} imm3_0/Rm 8667eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 8677eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 8687eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach unsigned Imm = MO1.getImm(); 8697eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 8707eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach bool isImm = MO.getReg() == 0; 8717eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 8727eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 8737eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach if (!isImm) 8747eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach Imm8 = getARMRegisterNumbering(MO.getReg()); 8757eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach return Imm8 | (isAdd << 8) | (isImm << 9); 8767eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach} 8777eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbach 8787eab97f260ba0f56d1d4a82f3a4eb2c979452011Jim Grosbachuint32_t ARMMCCodeEmitter:: 879570a9226913ebe1af04832b8fb3273c70b4ee152Jim GrosbachgetAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 880570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 881570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {13} 1 == imm8, 0 == Rm 882570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {12-9} Rn 883570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {8} isAdd 884570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {7-4} imm7_4/zero 885570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // {3-0} imm3_0/Rm 886570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 887570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx+1); 888570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach const MCOperand &MO2 = MI.getOperand(OpIdx+2); 889570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach unsigned Rn = getARMRegisterNumbering(MO.getReg()); 890570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach unsigned Imm = MO2.getImm(); 891570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 892570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach bool isImm = MO1.getReg() == 0; 893570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 894570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 895570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach if (!isImm) 896570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach Imm8 = getARMRegisterNumbering(MO1.getReg()); 897570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 898570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach} 899570a9226913ebe1af04832b8fb3273c70b4ee152Jim Grosbach 900b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 901d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbachuint32_t ARMMCCodeEmitter:: 902d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim GrosbachgetAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 903d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 904d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach // [SP, #imm] 905d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach // {7-0} = imm8 906d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 907b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 908b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling "Unexpected base register!"); 9097a905a82f7425d1a10b828c8bb3365b2ebc15833Bill Wendling 910d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach // The immediate is already shifted for the implicit zeroes, so no change 911d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach // here. 912d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach return MO1.getImm() & 0xff; 913d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach} 914d967cd096ae87accf2f1df86b2dfac969d9c9da2Jim Grosbach 915f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling/// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 916272df516d7a9b1f0f69174276abaa759816ee456Bill Wendlinguint32_t ARMMCCodeEmitter:: 917f4caf69720d807573c50d41aa06bcec1c99bdbbdBill WendlinggetAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 91822447ae54bcb8ca94ed994cad103074a24e66781Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 919ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling // [Rn, #imm] 920ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling // {7-3} = imm5 921ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling // {2-0} = Rn 922ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling const MCOperand &MO = MI.getOperand(OpIdx); 923ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 924ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling unsigned Rn = getARMRegisterNumbering(MO.getReg()); 925656b3d22f70c2d1c8a5286f7270cb380df862565Matt Beaumont-Gay unsigned Imm5 = MO1.getImm(); 926272df516d7a9b1f0f69174276abaa759816ee456Bill Wendling return ((Imm5 & 0x1f) << 3) | Rn; 9271fd374e9c1c074c1681336bef31e65f0170b0f7eBill Wendling} 9281fd374e9c1c074c1681336bef31e65f0170b0f7eBill Wendling 929b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 930b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendlinguint32_t ARMMCCodeEmitter:: 931b8958b031ec5163261f490f131780c5dc3d823d6Bill WendlinggetAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 932b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 933a7710edd98d71a81c43f8e3889cf0c790885d1b8Owen Anderson const MCOperand MO = MI.getOperand(OpIdx); 934a7710edd98d71a81c43f8e3889cf0c790885d1b8Owen Anderson if (MO.isExpr()) 935a7710edd98d71a81c43f8e3889cf0c790885d1b8Owen Anderson return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); 936a7710edd98d71a81c43f8e3889cf0c790885d1b8Owen Anderson return (MO.getImm() >> 2); 937b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling} 938b8958b031ec5163261f490f131780c5dc3d823d6Bill Wendling 9395177f79c378b47e38bed5ac05ba4b597f31b864eJim Grosbach/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. 940806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachuint32_t ARMMCCodeEmitter:: 941806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 942806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 94392b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {12-9} = reg 94492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {8} = (U)nsigned (add == '1', sub == '0') 94592b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // {7-0} = imm8 94692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling unsigned Reg, Imm8; 94797dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach bool isAdd; 94870933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach // If The first operand isn't a register, we have a label reference. 94970933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 95070933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach if (!MO.isReg()) { 951679cbd3b215b1769a6035e334f9009aeeb940dddJim Grosbach Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 95270933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach Imm8 = 0; 95397dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach isAdd = false; // 'U' bit is handled as part of the fixup. 95470933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach 95570933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach assert(MO.isExpr() && "Unexpected machine operand type!"); 95670933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach const MCExpr *Expr = MO.getExpr(); 957d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3cOwen Anderson MCFixupKind Kind; 95859ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb2()) 959d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3cOwen Anderson Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 960d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3cOwen Anderson else 961d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3cOwen Anderson Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 96270933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 96370933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach 96470933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach ++MCNumCPRelocations; 96597dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach } else { 96670933266ae73c891d9d1c2f0de72ecd1db8f86dfJim Grosbach EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 96797dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 96897dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach } 96992b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 97092b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 97192b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 97297dd28fb89dc4c4caa3c60890335dc99489981a6Jim Grosbach if (isAdd) 97392b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Binary |= (1 << 8); 97492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling Binary |= (Reg << 9); 9753e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach return Binary; 9763e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach} 9773e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach 978806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 979152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen AndersongetSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 980806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 9810800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 982354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // shifted. The second is Rs, the amount to shift by, and the third specifies 983354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // the type of the shift. 98435b2de012d9404e3e9e4373e45f41711f752dd3aJim Grosbach // 985ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // {3-0} = Rm. 986354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {4} = 1 987ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // {6-5} = type 988354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {11-8} = Rs 989354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {7} = 0 990ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 991ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach const MCOperand &MO = MI.getOperand(OpIdx); 992ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 993ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 994ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 995ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 996ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // Encode Rm. 997ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach unsigned Binary = getARMRegisterNumbering(MO.getReg()); 998ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 999ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // Encode the shift opcode. 1000ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach unsigned SBits = 0; 1001ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach unsigned Rs = MO1.getReg(); 1002ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach if (Rs) { 1003ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // Set shift operand (bit[7:4]). 1004ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // LSL - 0001 1005ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // LSR - 0011 1006ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // ASR - 0101 1007ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // ROR - 0111 1008ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach switch (SOpc) { 1009ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach default: llvm_unreachable("Unknown shift opc!"); 1010ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach case ARM_AM::lsl: SBits = 0x1; break; 1011ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach case ARM_AM::lsr: SBits = 0x3; break; 1012ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach case ARM_AM::asr: SBits = 0x5; break; 1013ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach case ARM_AM::ror: SBits = 0x7; break; 1014ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach } 1015ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach } 10160800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling 1017ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach Binary |= SBits << 4; 1018ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1019354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // Encode the shift operation Rs. 1020152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Encode Rs bit[11:8]. 1021152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1022152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 1023152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson} 1024152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1025152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Andersonunsigned ARMMCCodeEmitter:: 1026152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen AndersongetSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1027152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 1028354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1029354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // shifted. The second is the amount to shift by. 1030152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // 1031152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // {3-0} = Rm. 1032354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {4} = 0 1033152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // {6-5} = type 1034354712c5a506449676e6fcac6b623af4092e7100Owen Anderson // {11-7} = imm 1035152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1036152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &MO = MI.getOperand(OpIdx); 1037152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1038152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1039152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1040152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Encode Rm. 1041152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson unsigned Binary = getARMRegisterNumbering(MO.getReg()); 1042152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1043152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Encode the shift opcode. 1044152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson unsigned SBits = 0; 1045152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1046152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Set shift operand (bit[6:4]). 1047152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // LSL - 000 1048152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // LSR - 010 1049152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // ASR - 100 1050152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // ROR - 110 1051152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // RRX - 110 and bit[11:8] clear. 1052152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson switch (SOpc) { 1053152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson default: llvm_unreachable("Unknown shift opc!"); 1054152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::lsl: SBits = 0x0; break; 1055152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::lsr: SBits = 0x2; break; 1056152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::asr: SBits = 0x4; break; 1057152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::ror: SBits = 0x6; break; 1058152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM_AM::rrx: 1059152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson Binary |= 0x60; 1060152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return Binary; 1061ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach } 1062ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1063ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach // Encode shift_imm bit[11:7]. 1064152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson Binary |= SBits << 4; 10653dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 10663dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson assert(Offset && "Offset must be in range 1-32!"); 10673dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson if (Offset == 32) Offset = 0; 10683dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson return Binary | (Offset << 7); 1069ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach} 1070ef324d704425a372aeba5fc91bee4d81635121f3Jim Grosbach 1071152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1072806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 107375579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen AndersongetT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 107475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 107575579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson const MCOperand &MO1 = MI.getOperand(OpNum); 107675579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson const MCOperand &MO2 = MI.getOperand(OpNum+1); 10777bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach const MCOperand &MO3 = MI.getOperand(OpNum+2); 10787bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 107975579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // Encoded as [Rn, Rm, imm]. 108075579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // FIXME: Needs fixup support. 108175579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson unsigned Value = getARMRegisterNumbering(MO1.getReg()); 108275579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value <<= 4; 108375579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value |= getARMRegisterNumbering(MO2.getReg()); 108475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value <<= 2; 108575579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value |= MO3.getImm(); 10867bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 108775579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson return Value; 108875579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson} 108975579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson 109075579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Andersonunsigned ARMMCCodeEmitter:: 109175579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen AndersongetT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 109275579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 109375579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson const MCOperand &MO1 = MI.getOperand(OpNum); 109475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson const MCOperand &MO2 = MI.getOperand(OpNum+1); 109575579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson 109675579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // FIXME: Needs fixup support. 109775579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson unsigned Value = getARMRegisterNumbering(MO1.getReg()); 10987bf4c02789f97e32225fc248dff6622b994a15eeJim Grosbach 109975579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // Even though the immediate is 8 bits long, we need 9 bits in order 110075579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson // to represent the (inverse of the) sign bit. 110175579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson Value <<= 9; 11026af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson int32_t tmp = (int32_t)MO2.getImm(); 11036af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson if (tmp < 0) 11046af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson tmp = abs(tmp); 11056af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson else 11066af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson Value |= 256; // Set the ADD bit 11076af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson Value |= tmp & 255; 11086af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson return Value; 11096af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson} 11106af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson 11116af50f7dd12d82f0a80f3158102180eee4c921aaOwen Andersonunsigned ARMMCCodeEmitter:: 11126af50f7dd12d82f0a80f3158102180eee4c921aaOwen AndersongetT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 11136af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 11146af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson const MCOperand &MO1 = MI.getOperand(OpNum); 11156af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson 11166af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson // FIXME: Needs fixup support. 11176af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson unsigned Value = 0; 11186af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson int32_t tmp = (int32_t)MO1.getImm(); 11196af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson if (tmp < 0) 11206af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson tmp = abs(tmp); 11216af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson else 11226af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson Value |= 256; // Set the ADD bit 11236af50f7dd12d82f0a80f3158102180eee4c921aaOwen Anderson Value |= tmp & 255; 112475579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson return Value; 112575579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson} 112675579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Anderson 112775579f739fbc99a92a15f3ce75bbd7628ba00f8cOwen Andersonunsigned ARMMCCodeEmitter:: 11280e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen AndersongetT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 11290e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 11300e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson const MCOperand &MO1 = MI.getOperand(OpNum); 11310e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson 11320e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson // FIXME: Needs fixup support. 11330e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson unsigned Value = 0; 11340e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson int32_t tmp = (int32_t)MO1.getImm(); 11350e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson if (tmp < 0) 11360e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson tmp = abs(tmp); 11370e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson else 11380e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson Value |= 4096; // Set the ADD bit 11390e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson Value |= tmp & 4095; 11400e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson return Value; 11410e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson} 11420e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Anderson 11430e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609Owen Andersonunsigned ARMMCCodeEmitter:: 11445de6d841a5116152793dcab35a2e534a6a9aaa7aOwen AndersongetT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 11455de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson SmallVectorImpl<MCFixup> &Fixups) const { 11465de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 11475de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // shifted. The second is the amount to shift by. 11485de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // 11495de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // {3-0} = Rm. 11505de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // {4} = 0 11515de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // {6-5} = type 11525de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // {11-7} = imm 11535de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 11545de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson const MCOperand &MO = MI.getOperand(OpIdx); 11555de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 11565de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 11575de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 11585de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Encode Rm. 11595de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned Binary = getARMRegisterNumbering(MO.getReg()); 11605de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 11615de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Encode the shift opcode. 11625de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson unsigned SBits = 0; 11635de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Set shift operand (bit[6:4]). 11645de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // LSL - 000 11655de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // LSR - 010 11665de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // ASR - 100 11675de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // ROR - 110 11685de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson switch (SOpc) { 11695de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson default: llvm_unreachable("Unknown shift opc!"); 11705de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson case ARM_AM::lsl: SBits = 0x0; break; 11715de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson case ARM_AM::lsr: SBits = 0x2; break; 11725de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson case ARM_AM::asr: SBits = 0x4; break; 11735de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson case ARM_AM::ror: SBits = 0x6; break; 11745de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson } 11755de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 11765de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson Binary |= SBits << 4; 11775de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson if (SOpc == ARM_AM::rrx) 11785de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson return Binary; 11795de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 11805de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson // Encode shift_imm bit[11:7]. 11815de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 11825de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson} 11835de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Anderson 11845de6d841a5116152793dcab35a2e534a6a9aaa7aOwen Andersonunsigned ARMMCCodeEmitter:: 1185806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1186806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 11873fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the 11883fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach // msb of the mask. 11893fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach const MCOperand &MO = MI.getOperand(Op); 11903fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach uint32_t v = ~MO.getImm(); 11913fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach uint32_t lsb = CountTrailingZeros_32(v); 11923fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1; 11933fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 11943fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach return lsb | (msb << 5); 11953fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach} 11963fea19105d4929ad694f0b6272de31924c9f9f09Jim Grosbach 1197806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 1198a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso LopesgetMsbOpValue(const MCInst &MI, unsigned Op, 1199a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes SmallVectorImpl<MCFixup> &Fixups) const { 1200a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes // MSB - 5 bits. 1201a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes uint32_t lsb = MI.getOperand(Op-1).getImm(); 1202a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes uint32_t width = MI.getOperand(Op).getImm(); 1203a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes uint32_t msb = lsb+width-1; 1204a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes assert (width != 0 && msb < 32 && "Illegal bit width!"); 1205a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes return msb; 1206a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes} 1207a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopes 1208a461d4222877f43588da38c466145f38dd74e229Bruno Cardoso Lopesunsigned ARMMCCodeEmitter:: 1209806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetRegisterListOpValue(const MCInst &MI, unsigned Op, 12105e559a22c18166508a01fbd65471ec4e752726f9Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 12116bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // VLDM/VSTM: 12126bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // {12-8} = Vd 12136bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // {7-0} = Number of registers 12146bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // 12156bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // LDM/STM: 12166bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // {15-0} = Bitfield of GPRs. 12176bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling unsigned Reg = MI.getOperand(Op).getReg(); 1218be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1219be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 12206bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling 12215e559a22c18166508a01fbd65471ec4e752726f9Bill Wendling unsigned Binary = 0; 12226bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling 12236bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling if (SPRRegs || DPRRegs) { 12246bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling // VLDM/VSTM 12256bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling unsigned RegNo = getARMRegisterNumbering(Reg); 12266bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 12276bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling Binary |= (RegNo & 0x1f) << 8; 12286bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling if (SPRRegs) 12296bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling Binary |= NumRegs; 12306bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling else 12316bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling Binary |= NumRegs * 2; 12326bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling } else { 12336bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 12346bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg()); 12356bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling Binary |= 1 << RegNo; 12366bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling } 12375e559a22c18166508a01fbd65471ec4e752726f9Bill Wendling } 12386bc105a7b9282a0b5beb9d06267b31a3054fb3faBill Wendling 12396b5252db2db5eeeadec4602329ac56beb6dea54aJim Grosbach return Binary; 12406b5252db2db5eeeadec4602329ac56beb6dea54aJim Grosbach} 12416b5252db2db5eeeadec4602329ac56beb6dea54aJim Grosbach 12428e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 12438e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// with the alignment operand. 1244806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 1245806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1246806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 1247d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson const MCOperand &Reg = MI.getOperand(Op); 12480800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling const MCOperand &Imm = MI.getOperand(Op + 1); 124935b2de012d9404e3e9e4373e45f41711f752dd3aJim Grosbach 1250d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 12510800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling unsigned Align = 0; 12520800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling 12530800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling switch (Imm.getImm()) { 12540800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling default: break; 12550800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 2: 12560800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 4: 12570800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 8: Align = 0x01; break; 12580800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 16: Align = 0x02; break; 12590800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling case 32: Align = 0x03; break; 1260d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson } 12610800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling 1262d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson return RegNo | (Align << 4); 1263d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson} 1264d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5Owen Anderson 1265183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1266183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang/// along with the alignment operand for use in VST1 and VLD1 with size 32. 1267183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wangunsigned ARMMCCodeEmitter:: 1268183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P WanggetAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1269183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang SmallVectorImpl<MCFixup> &Fixups) const { 1270183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang const MCOperand &Reg = MI.getOperand(Op); 1271183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang const MCOperand &Imm = MI.getOperand(Op + 1); 1272183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 1273183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 1274183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang unsigned Align = 0; 1275183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 1276183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang switch (Imm.getImm()) { 1277183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang default: break; 1278183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 2: 1279183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 4: 1280183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 8: 1281183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 16: Align = 0x00; break; 1282183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang case 32: Align = 0x03; break; 1283183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang } 1284183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 1285183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang return RegNo | (Align << 4); 1286183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang} 1287183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 1288183c627d89be5d0e8f3255ab7f6d1204c2fabedfMon P Wang 12898e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 12908e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// alignment operand for use in VLD-dup instructions. This is the same as 12918e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// getAddrMode6AddressOpValue except for the alignment encoding, which is 12928e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson/// different for VLD4-dup. 12938e0c7b52877983b4838e54e233449912fc1a2325Bob Wilsonunsigned ARMMCCodeEmitter:: 12948e0c7b52877983b4838e54e233449912fc1a2325Bob WilsongetAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 12958e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson SmallVectorImpl<MCFixup> &Fixups) const { 12968e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson const MCOperand &Reg = MI.getOperand(Op); 12978e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson const MCOperand &Imm = MI.getOperand(Op + 1); 12988e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson 12998e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 13008e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson unsigned Align = 0; 13018e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson 13028e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson switch (Imm.getImm()) { 13038e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson default: break; 13048e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson case 2: 13058e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson case 4: 13068e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson case 8: Align = 0x01; break; 13078e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson case 16: Align = 0x03; break; 13088e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson } 13098e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson 13108e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson return RegNo | (Align << 4); 13118e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson} 13128e0c7b52877983b4838e54e233449912fc1a2325Bob Wilson 1313806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbachunsigned ARMMCCodeEmitter:: 1314806e80ef42bdb416f409142a1ff1d4e8752baac8Jim GrosbachgetAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1315806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 13160800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling const MCOperand &MO = MI.getOperand(Op); 13170800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling if (MO.getReg() == 0) return 0x0D; 13180800ce71896ccd7f49b37861a8cfbc21b6b10022Bill Wendling return MO.getReg(); 1319a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling} 1320a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling 1321a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendlingunsigned ARMMCCodeEmitter:: 13223116dce33840a115130c5f8ffcb9679d023496d6Bill WendlinggetShiftRight8Imm(const MCInst &MI, unsigned Op, 13233116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 1324a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling return 8 - MI.getOperand(Op).getImm(); 1325a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling} 1326a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling 1327a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendlingunsigned ARMMCCodeEmitter:: 13283116dce33840a115130c5f8ffcb9679d023496d6Bill WendlinggetShiftRight16Imm(const MCInst &MI, unsigned Op, 13293116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 1330a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling return 16 - MI.getOperand(Op).getImm(); 1331a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling} 1332a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling 1333a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendlingunsigned ARMMCCodeEmitter:: 13343116dce33840a115130c5f8ffcb9679d023496d6Bill WendlinggetShiftRight32Imm(const MCInst &MI, unsigned Op, 13353116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 1336a656b63ee4d5b0e3f4d26a55dd4cc69795746684Bill Wendling return 32 - MI.getOperand(Op).getImm(); 13373116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling} 13383116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling 13393116dce33840a115130c5f8ffcb9679d023496d6Bill Wendlingunsigned ARMMCCodeEmitter:: 13403116dce33840a115130c5f8ffcb9679d023496d6Bill WendlinggetShiftRight64Imm(const MCInst &MI, unsigned Op, 13413116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling SmallVectorImpl<MCFixup> &Fixups) const { 13423116dce33840a115130c5f8ffcb9679d023496d6Bill Wendling return 64 - MI.getOperand(Op).getImm(); 1343cf667be17b479fe276fd606b8fd72ccfa3065bb8Owen Anderson} 1344cf667be17b479fe276fd606b8fd72ccfa3065bb8Owen Anderson 1345568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbachvoid ARMMCCodeEmitter:: 1346568eeedea72c274abbba1310c18a31eef78e14a4Jim GrosbachEncodeInstruction(const MCInst &MI, raw_ostream &OS, 1347806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach SmallVectorImpl<MCFixup> &Fixups) const { 1348d6d4b42ba473657b6d30242962f0d0fb23fe126eJim Grosbach // Pseudo instructions don't get encoded. 134959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1350e50e6bcd901ebb1cfc42fe9ca0796ae303d7f1a1Jim Grosbach uint64_t TSFlags = Desc.TSFlags; 1351e50e6bcd901ebb1cfc42fe9ca0796ae303d7f1a1Jim Grosbach if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1352d6d4b42ba473657b6d30242962f0d0fb23fe126eJim Grosbach return; 135316884415db751c75f2133bd04921393c792b1158Owen Anderson 1354e50e6bcd901ebb1cfc42fe9ca0796ae303d7f1a1Jim Grosbach int Size; 135516884415db751c75f2133bd04921393c792b1158Owen Anderson if (Desc.getSize() == 2 || Desc.getSize() == 4) 135616884415db751c75f2133bd04921393c792b1158Owen Anderson Size = Desc.getSize(); 135716884415db751c75f2133bd04921393c792b1158Owen Anderson else 135816884415db751c75f2133bd04921393c792b1158Owen Anderson llvm_unreachable("Unexpected instruction size!"); 135910096dbdef22a10a6a4444437c935ab428545525Owen Anderson 1360d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); 13617597212abced110723f2fee985a7d60557c092ecEvan Cheng // Thumb 32-bit wide instructions need to emit the high order halfword 13627597212abced110723f2fee985a7d60557c092ecEvan Cheng // first. 136359ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng if (isThumb() && Size == 4) { 1364d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach EmitConstant(Binary >> 16, 2, OS); 1365d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach EmitConstant(Binary & 0xffff, 2, OS); 1366d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach } else 1367d91f4e40e6312304c60c83c3dd93f769a39a9772Jim Grosbach EmitConstant(Binary, Size, OS); 13687292e0a6564bb24707eff1c49da9044dd5eaec78Bill Wendling ++MCNumEmitted; // Keep track of the # of mi's emitted. 1369568eeedea72c274abbba1310c18a31eef78e14a4Jim Grosbach} 13709af82ba42b53905f580f8c4270626946e3548654Jim Grosbach 1371806e80ef42bdb416f409142a1ff1d4e8752baac8Jim Grosbach#include "ARMGenMCCodeEmitter.inc" 1372