ARMMCCodeEmitter.cpp revision c89c744b69cecac576317a98322fd295e36e9886
1ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// 3ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// The LLVM Compiler Infrastructure 4ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// 5ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// This file is distributed under the University of Illinois Open Source 6ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// License. See LICENSE.TXT for details. 7ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// 8ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen//===----------------------------------------------------------------------===// 9ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// 10ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// This file implements the ARMMCCodeEmitter class. 11ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen// 12ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen//===----------------------------------------------------------------------===// 13ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 14ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#define DEBUG_TYPE "mccodeemitter" 15ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "MCTargetDesc/ARMAddressingModes.h" 16ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "MCTargetDesc/ARMBaseInfo.h" 17ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "MCTargetDesc/ARMFixupKinds.h" 18ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "MCTargetDesc/ARMMCExpr.h" 19ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "MCTargetDesc/ARMMCTargetDesc.h" 20ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/MC/MCCodeEmitter.h" 21ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/MC/MCExpr.h" 22ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/MC/MCInst.h" 23ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/MC/MCInstrInfo.h" 24ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/MC/MCRegisterInfo.h" 25ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/MC/MCSubtargetInfo.h" 26ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/ADT/APFloat.h" 27ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/ADT/Statistic.h" 28ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/Support/raw_ostream.h" 29ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 30ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsenusing namespace llvm; 31ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 32ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian MonsenSTATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 33ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian MonsenSTATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 34ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 35ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsennamespace { 36ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsenclass ARMMCCodeEmitter : public MCCodeEmitter { 37ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT 38ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT 39ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen const MCInstrInfo &MCII; 40ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen const MCSubtargetInfo &STI; 41ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 42ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsenpublic: 43ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 44ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen MCContext &ctx) 45ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen : MCII(mcii), STI(sti) { 46ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen } 47ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 48ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen ~ARMMCCodeEmitter() {} 49ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 50ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen bool isThumb() const { 51ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen // FIXME: Can tablegen auto-generate this? 52ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 53ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen } 54ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen bool isThumb2() const { 55ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; 56ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen } 57ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen bool isTargetDarwin() const { 58ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen Triple TT(STI.getTargetTriple()); 59ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen Triple::OSType OS = TT.getOS(); 60ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS; 61ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen } 62ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 63ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen unsigned getMachineSoImmOpValue(unsigned SoImm) const; 64ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 65ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen // getBinaryCodeForInstr - TableGen'erated function for getting the 66ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen // binary encoding for an instruction. 67ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen uint64_t getBinaryCodeForInstr(const MCInst &MI, 68ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen SmallVectorImpl<MCFixup> &Fixups) const; 69ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 70ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen /// getMachineOpValue - Return binary encoding of operand. If the machine 71ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen /// operand requires relocation, record the relocation and return zero. 72ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 73ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen SmallVectorImpl<MCFixup> &Fixups) const; 74ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 75ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 76ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen /// the specified operand. This is used for operands with :lower16: and 77ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen /// :upper16: prefixes. 78ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 79ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen SmallVectorImpl<MCFixup> &Fixups) const; 80ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 81ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 82ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen unsigned &Reg, unsigned &Imm, 83ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen SmallVectorImpl<MCFixup> &Fixups) const; 84ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen 85ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 86ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen /// BL branch target. 87ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 88 SmallVectorImpl<MCFixup> &Fixups) const; 89 90 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 91 /// BLX branch target. 92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 93 SmallVectorImpl<MCFixup> &Fixups) const; 94 95 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 97 SmallVectorImpl<MCFixup> &Fixups) const; 98 99 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 101 SmallVectorImpl<MCFixup> &Fixups) const; 102 103 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 105 SmallVectorImpl<MCFixup> &Fixups) const; 106 107 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 108 /// branch target. 109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 110 SmallVectorImpl<MCFixup> &Fixups) const; 111 112 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 113 /// immediate Thumb2 direct branch target. 114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 115 SmallVectorImpl<MCFixup> &Fixups) const; 116 117 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 118 /// branch target. 119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 120 SmallVectorImpl<MCFixup> &Fixups) const; 121 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 122 SmallVectorImpl<MCFixup> &Fixups) const; 123 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 124 SmallVectorImpl<MCFixup> &Fixups) const; 125 126 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 127 /// ADR label target. 128 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 129 SmallVectorImpl<MCFixup> &Fixups) const; 130 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 131 SmallVectorImpl<MCFixup> &Fixups) const; 132 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 133 SmallVectorImpl<MCFixup> &Fixups) const; 134 135 136 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 137 /// operand. 138 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 139 SmallVectorImpl<MCFixup> &Fixups) const; 140 141 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 142 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 143 SmallVectorImpl<MCFixup> &Fixups)const; 144 145 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 146 /// operand. 147 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 148 SmallVectorImpl<MCFixup> &Fixups) const; 149 150 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 151 /// operand. 152 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 153 SmallVectorImpl<MCFixup> &Fixups) const; 154 155 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' 156 /// operand. 157 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 158 SmallVectorImpl<MCFixup> &Fixups) const; 159 160 161 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 162 /// operand as needed by load/store instructions. 163 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 164 SmallVectorImpl<MCFixup> &Fixups) const; 165 166 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 167 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 168 SmallVectorImpl<MCFixup> &Fixups) const { 169 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 170 switch (Mode) { 171 default: llvm_unreachable("Unknown addressing sub-mode!"); 172 case ARM_AM::da: return 0; 173 case ARM_AM::ia: return 1; 174 case ARM_AM::db: return 2; 175 case ARM_AM::ib: return 3; 176 } 177 } 178 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 179 /// 180 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 181 switch (ShOpc) { 182 case ARM_AM::no_shift: 183 case ARM_AM::lsl: return 0; 184 case ARM_AM::lsr: return 1; 185 case ARM_AM::asr: return 2; 186 case ARM_AM::ror: 187 case ARM_AM::rrx: return 3; 188 } 189 llvm_unreachable("Invalid ShiftOpc!"); 190 } 191 192 /// getAddrMode2OpValue - Return encoding for addrmode2 operands. 193 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 194 SmallVectorImpl<MCFixup> &Fixups) const; 195 196 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 197 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 198 SmallVectorImpl<MCFixup> &Fixups) const; 199 200 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 201 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 202 SmallVectorImpl<MCFixup> &Fixups) const; 203 204 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 205 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 206 SmallVectorImpl<MCFixup> &Fixups) const; 207 208 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 209 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 210 SmallVectorImpl<MCFixup> &Fixups) const; 211 212 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 213 /// operand. 214 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 215 SmallVectorImpl<MCFixup> &Fixups) const; 216 217 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 218 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 219 SmallVectorImpl<MCFixup> &Fixups) const; 220 221 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 222 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 223 SmallVectorImpl<MCFixup> &Fixups) const; 224 225 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. 226 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 227 SmallVectorImpl<MCFixup> &Fixups) const; 228 229 /// getCCOutOpValue - Return encoding of the 's' bit. 230 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 231 SmallVectorImpl<MCFixup> &Fixups) const { 232 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 233 // '1' respectively. 234 return MI.getOperand(Op).getReg() == ARM::CPSR; 235 } 236 237 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. 238 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, 239 SmallVectorImpl<MCFixup> &Fixups) const { 240 unsigned SoImm = MI.getOperand(Op).getImm(); 241 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 242 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 243 244 // Encode rotate_imm. 245 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 246 << ARMII::SoRotImmShift; 247 248 // Encode immed_8. 249 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 250 return Binary; 251 } 252 253 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 254 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 255 SmallVectorImpl<MCFixup> &Fixups) const { 256 unsigned SoImm = MI.getOperand(Op).getImm(); 257 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 258 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 259 return Encoded; 260 } 261 262 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 263 SmallVectorImpl<MCFixup> &Fixups) const; 264 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 265 SmallVectorImpl<MCFixup> &Fixups) const; 266 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 267 SmallVectorImpl<MCFixup> &Fixups) const; 268 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 269 SmallVectorImpl<MCFixup> &Fixups) const; 270 271 /// getSORegOpValue - Return an encoded so_reg shifted register value. 272 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 273 SmallVectorImpl<MCFixup> &Fixups) const; 274 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 275 SmallVectorImpl<MCFixup> &Fixups) const; 276 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 277 SmallVectorImpl<MCFixup> &Fixups) const; 278 279 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 280 SmallVectorImpl<MCFixup> &Fixups) const { 281 return 64 - MI.getOperand(Op).getImm(); 282 } 283 284 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 285 SmallVectorImpl<MCFixup> &Fixups) const; 286 287 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 288 SmallVectorImpl<MCFixup> &Fixups) const; 289 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 290 SmallVectorImpl<MCFixup> &Fixups) const; 291 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 292 SmallVectorImpl<MCFixup> &Fixups) const; 293 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 294 SmallVectorImpl<MCFixup> &Fixups) const; 295 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 296 SmallVectorImpl<MCFixup> &Fixups) const; 297 298 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 299 SmallVectorImpl<MCFixup> &Fixups) const; 300 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 301 SmallVectorImpl<MCFixup> &Fixups) const; 302 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 303 SmallVectorImpl<MCFixup> &Fixups) const; 304 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 305 SmallVectorImpl<MCFixup> &Fixups) const; 306 307 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 308 SmallVectorImpl<MCFixup> &Fixups) const; 309 310 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 311 unsigned EncodedValue) const; 312 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 313 unsigned EncodedValue) const; 314 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 315 unsigned EncodedValue) const; 316 317 unsigned VFPThumb2PostEncoder(const MCInst &MI, 318 unsigned EncodedValue) const; 319 320 void EmitByte(unsigned char C, raw_ostream &OS) const { 321 OS << (char)C; 322 } 323 324 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 325 // Output the constant in little endian byte order. 326 for (unsigned i = 0; i != Size; ++i) { 327 EmitByte(Val & 255, OS); 328 Val >>= 8; 329 } 330 } 331 332 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 333 SmallVectorImpl<MCFixup> &Fixups) const; 334}; 335 336} // end anonymous namespace 337 338MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII, 339 const MCSubtargetInfo &STI, 340 MCContext &Ctx) { 341 return new ARMMCCodeEmitter(MCII, STI, Ctx); 342} 343 344/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 345/// instructions, and rewrite them to their Thumb2 form if we are currently in 346/// Thumb2 mode. 347unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 348 unsigned EncodedValue) const { 349 if (isThumb2()) { 350 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 351 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 352 // set to 1111. 353 unsigned Bit24 = EncodedValue & 0x01000000; 354 unsigned Bit28 = Bit24 << 4; 355 EncodedValue &= 0xEFFFFFFF; 356 EncodedValue |= Bit28; 357 EncodedValue |= 0x0F000000; 358 } 359 360 return EncodedValue; 361} 362 363/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 364/// instructions, and rewrite them to their Thumb2 form if we are currently in 365/// Thumb2 mode. 366unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 367 unsigned EncodedValue) const { 368 if (isThumb2()) { 369 EncodedValue &= 0xF0FFFFFF; 370 EncodedValue |= 0x09000000; 371 } 372 373 return EncodedValue; 374} 375 376/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 377/// instructions, and rewrite them to their Thumb2 form if we are currently in 378/// Thumb2 mode. 379unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 380 unsigned EncodedValue) const { 381 if (isThumb2()) { 382 EncodedValue &= 0x00FFFFFF; 383 EncodedValue |= 0xEE000000; 384 } 385 386 return EncodedValue; 387} 388 389/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 390/// them to their Thumb2 form if we are currently in Thumb2 mode. 391unsigned ARMMCCodeEmitter:: 392VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { 393 if (isThumb2()) { 394 EncodedValue &= 0x0FFFFFFF; 395 EncodedValue |= 0xE0000000; 396 } 397 return EncodedValue; 398} 399 400/// getMachineOpValue - Return binary encoding of operand. If the machine 401/// operand requires relocation, record the relocation and return zero. 402unsigned ARMMCCodeEmitter:: 403getMachineOpValue(const MCInst &MI, const MCOperand &MO, 404 SmallVectorImpl<MCFixup> &Fixups) const { 405 if (MO.isReg()) { 406 unsigned Reg = MO.getReg(); 407 unsigned RegNo = getARMRegisterNumbering(Reg); 408 409 // Q registers are encoded as 2x their register number. 410 switch (Reg) { 411 default: 412 return RegNo; 413 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 414 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 415 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 416 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 417 return 2 * RegNo; 418 } 419 } else if (MO.isImm()) { 420 return static_cast<unsigned>(MO.getImm()); 421 } else if (MO.isFPImm()) { 422 return static_cast<unsigned>(APFloat(MO.getFPImm()) 423 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 424 } 425 426 llvm_unreachable("Unable to encode MCOperand!"); 427} 428 429/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 430bool ARMMCCodeEmitter:: 431EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 432 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const { 433 const MCOperand &MO = MI.getOperand(OpIdx); 434 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 435 436 Reg = getARMRegisterNumbering(MO.getReg()); 437 438 int32_t SImm = MO1.getImm(); 439 bool isAdd = true; 440 441 // Special value for #-0 442 if (SImm == INT32_MIN) { 443 SImm = 0; 444 isAdd = false; 445 } 446 447 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 448 if (SImm < 0) { 449 SImm = -SImm; 450 isAdd = false; 451 } 452 453 Imm = SImm; 454 return isAdd; 455} 456 457/// getBranchTargetOpValue - Helper function to get the branch target operand, 458/// which is either an immediate or requires a fixup. 459static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 460 unsigned FixupKind, 461 SmallVectorImpl<MCFixup> &Fixups) { 462 const MCOperand &MO = MI.getOperand(OpIdx); 463 464 // If the destination is an immediate, we have nothing to do. 465 if (MO.isImm()) return MO.getImm(); 466 assert(MO.isExpr() && "Unexpected branch target type!"); 467 const MCExpr *Expr = MO.getExpr(); 468 MCFixupKind Kind = MCFixupKind(FixupKind); 469 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 470 471 // All of the information is in the fixup. 472 return 0; 473} 474 475// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 476// determined by negating them and XOR'ing them with bit 23. 477static int32_t encodeThumbBLOffset(int32_t offset) { 478 offset >>= 1; 479 uint32_t S = (offset & 0x800000) >> 23; 480 uint32_t J1 = (offset & 0x400000) >> 22; 481 uint32_t J2 = (offset & 0x200000) >> 21; 482 J1 = (~J1 & 0x1); 483 J2 = (~J2 & 0x1); 484 J1 ^= S; 485 J2 ^= S; 486 487 offset &= ~0x600000; 488 offset |= J1 << 22; 489 offset |= J2 << 21; 490 491 return offset; 492} 493 494/// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 495uint32_t ARMMCCodeEmitter:: 496getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 497 SmallVectorImpl<MCFixup> &Fixups) const { 498 const MCOperand MO = MI.getOperand(OpIdx); 499 if (MO.isExpr()) 500 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 501 Fixups); 502 return encodeThumbBLOffset(MO.getImm()); 503} 504 505/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 506/// BLX branch target. 507uint32_t ARMMCCodeEmitter:: 508getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 509 SmallVectorImpl<MCFixup> &Fixups) const { 510 const MCOperand MO = MI.getOperand(OpIdx); 511 if (MO.isExpr()) 512 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 513 Fixups); 514 return encodeThumbBLOffset(MO.getImm()); 515} 516 517/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 518uint32_t ARMMCCodeEmitter:: 519getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 520 SmallVectorImpl<MCFixup> &Fixups) const { 521 const MCOperand MO = MI.getOperand(OpIdx); 522 if (MO.isExpr()) 523 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 524 Fixups); 525 return (MO.getImm() >> 1); 526} 527 528/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 529uint32_t ARMMCCodeEmitter:: 530getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 531 SmallVectorImpl<MCFixup> &Fixups) const { 532 const MCOperand MO = MI.getOperand(OpIdx); 533 if (MO.isExpr()) 534 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 535 Fixups); 536 return (MO.getImm() >> 1); 537} 538 539/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 540uint32_t ARMMCCodeEmitter:: 541getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 542 SmallVectorImpl<MCFixup> &Fixups) const { 543 const MCOperand MO = MI.getOperand(OpIdx); 544 if (MO.isExpr()) 545 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); 546 return (MO.getImm() >> 1); 547} 548 549/// Return true if this branch has a non-always predication 550static bool HasConditionalBranch(const MCInst &MI) { 551 int NumOp = MI.getNumOperands(); 552 if (NumOp >= 2) { 553 for (int i = 0; i < NumOp-1; ++i) { 554 const MCOperand &MCOp1 = MI.getOperand(i); 555 const MCOperand &MCOp2 = MI.getOperand(i + 1); 556 if (MCOp1.isImm() && MCOp2.isReg() && 557 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 558 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 559 return true; 560 } 561 } 562 } 563 return false; 564} 565 566/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 567/// target. 568uint32_t ARMMCCodeEmitter:: 569getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 570 SmallVectorImpl<MCFixup> &Fixups) const { 571 // FIXME: This really, really shouldn't use TargetMachine. We don't want 572 // coupling between MC and TM anywhere we can help it. 573 if (isThumb2()) 574 return 575 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); 576 return getARMBranchTargetOpValue(MI, OpIdx, Fixups); 577} 578 579/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 580/// target. 581uint32_t ARMMCCodeEmitter:: 582getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 583 SmallVectorImpl<MCFixup> &Fixups) const { 584 const MCOperand MO = MI.getOperand(OpIdx); 585 if (MO.isExpr()) { 586 if (HasConditionalBranch(MI)) 587 return ::getBranchTargetOpValue(MI, OpIdx, 588 ARM::fixup_arm_condbranch, Fixups); 589 return ::getBranchTargetOpValue(MI, OpIdx, 590 ARM::fixup_arm_uncondbranch, Fixups); 591 } 592 593 return MO.getImm() >> 2; 594} 595 596uint32_t ARMMCCodeEmitter:: 597getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 598 SmallVectorImpl<MCFixup> &Fixups) const { 599 const MCOperand MO = MI.getOperand(OpIdx); 600 if (MO.isExpr()) 601 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_bl, Fixups); 602 603 return MO.getImm() >> 2; 604} 605 606uint32_t ARMMCCodeEmitter:: 607getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 608 SmallVectorImpl<MCFixup> &Fixups) const { 609 const MCOperand MO = MI.getOperand(OpIdx); 610 if (MO.isExpr()) 611 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups); 612 613 return MO.getImm() >> 1; 614} 615 616/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 617/// immediate branch target. 618uint32_t ARMMCCodeEmitter:: 619getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 620 SmallVectorImpl<MCFixup> &Fixups) const { 621 unsigned Val = 622 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups); 623 bool I = (Val & 0x800000); 624 bool J1 = (Val & 0x400000); 625 bool J2 = (Val & 0x200000); 626 if (I ^ J1) 627 Val &= ~0x400000; 628 else 629 Val |= 0x400000; 630 631 if (I ^ J2) 632 Val &= ~0x200000; 633 else 634 Val |= 0x200000; 635 636 return Val; 637} 638 639/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 640/// target. 641uint32_t ARMMCCodeEmitter:: 642getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 643 SmallVectorImpl<MCFixup> &Fixups) const { 644 const MCOperand MO = MI.getOperand(OpIdx); 645 if (MO.isExpr()) 646 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 647 Fixups); 648 int32_t offset = MO.getImm(); 649 uint32_t Val = 0x2000; 650 if (offset < 0) { 651 Val = 0x1000; 652 offset *= -1; 653 } 654 Val |= offset; 655 return Val; 656} 657 658/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 659/// target. 660uint32_t ARMMCCodeEmitter:: 661getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 662 SmallVectorImpl<MCFixup> &Fixups) const { 663 const MCOperand MO = MI.getOperand(OpIdx); 664 if (MO.isExpr()) 665 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 666 Fixups); 667 int32_t Val = MO.getImm(); 668 if (Val < 0) { 669 Val *= -1; 670 Val |= 0x1000; 671 } 672 return Val; 673} 674 675/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 676/// target. 677uint32_t ARMMCCodeEmitter:: 678getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 679 SmallVectorImpl<MCFixup> &Fixups) const { 680 const MCOperand MO = MI.getOperand(OpIdx); 681 if (MO.isExpr()) 682 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 683 Fixups); 684 return MO.getImm(); 685} 686 687/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 688/// operand. 689uint32_t ARMMCCodeEmitter:: 690getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 691 SmallVectorImpl<MCFixup> &) const { 692 // [Rn, Rm] 693 // {5-3} = Rm 694 // {2-0} = Rn 695 const MCOperand &MO1 = MI.getOperand(OpIdx); 696 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 697 unsigned Rn = getARMRegisterNumbering(MO1.getReg()); 698 unsigned Rm = getARMRegisterNumbering(MO2.getReg()); 699 return (Rm << 3) | Rn; 700} 701 702/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 703uint32_t ARMMCCodeEmitter:: 704getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 705 SmallVectorImpl<MCFixup> &Fixups) const { 706 // {17-13} = reg 707 // {12} = (U)nsigned (add == '1', sub == '0') 708 // {11-0} = imm12 709 unsigned Reg, Imm12; 710 bool isAdd = true; 711 // If The first operand isn't a register, we have a label reference. 712 const MCOperand &MO = MI.getOperand(OpIdx); 713 if (!MO.isReg()) { 714 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 715 Imm12 = 0; 716 isAdd = false ; // 'U' bit is set as part of the fixup. 717 718 if (MO.isExpr()) { 719 const MCExpr *Expr = MO.getExpr(); 720 721 MCFixupKind Kind; 722 if (isThumb2()) 723 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 724 else 725 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 726 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 727 728 ++MCNumCPRelocations; 729 } else { 730 Reg = ARM::PC; 731 int32_t Offset = MO.getImm(); 732 // FIXME: Handle #-0. 733 if (Offset < 0) { 734 Offset *= -1; 735 isAdd = false; 736 } 737 Imm12 = Offset; 738 } 739 } else 740 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); 741 742 uint32_t Binary = Imm12 & 0xfff; 743 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 744 if (isAdd) 745 Binary |= (1 << 12); 746 Binary |= (Reg << 13); 747 return Binary; 748} 749 750/// getT2Imm8s4OpValue - Return encoding info for 751/// '+/- imm8<<2' operand. 752uint32_t ARMMCCodeEmitter:: 753getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 754 SmallVectorImpl<MCFixup> &Fixups) const { 755 // FIXME: The immediate operand should have already been encoded like this 756 // before ever getting here. The encoder method should just need to combine 757 // the MI operands for the register and the offset into a single 758 // representation for the complex operand in the .td file. This isn't just 759 // style, unfortunately. As-is, we can't represent the distinct encoding 760 // for #-0. 761 762 // {8} = (U)nsigned (add == '1', sub == '0') 763 // {7-0} = imm8 764 int32_t Imm8 = MI.getOperand(OpIdx).getImm(); 765 bool isAdd = Imm8 >= 0; 766 767 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 768 if (Imm8 < 0) 769 Imm8 = -Imm8; 770 771 // Scaled by 4. 772 Imm8 /= 4; 773 774 uint32_t Binary = Imm8 & 0xff; 775 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 776 if (isAdd) 777 Binary |= (1 << 8); 778 return Binary; 779} 780 781/// getT2AddrModeImm8s4OpValue - Return encoding info for 782/// 'reg +/- imm8<<2' operand. 783uint32_t ARMMCCodeEmitter:: 784getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 785 SmallVectorImpl<MCFixup> &Fixups) const { 786 // {12-9} = reg 787 // {8} = (U)nsigned (add == '1', sub == '0') 788 // {7-0} = imm8 789 unsigned Reg, Imm8; 790 bool isAdd = true; 791 // If The first operand isn't a register, we have a label reference. 792 const MCOperand &MO = MI.getOperand(OpIdx); 793 if (!MO.isReg()) { 794 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 795 Imm8 = 0; 796 isAdd = false ; // 'U' bit is set as part of the fixup. 797 798 assert(MO.isExpr() && "Unexpected machine operand type!"); 799 const MCExpr *Expr = MO.getExpr(); 800 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 801 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 802 803 ++MCNumCPRelocations; 804 } else 805 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 806 807 // FIXME: The immediate operand should have already been encoded like this 808 // before ever getting here. The encoder method should just need to combine 809 // the MI operands for the register and the offset into a single 810 // representation for the complex operand in the .td file. This isn't just 811 // style, unfortunately. As-is, we can't represent the distinct encoding 812 // for #-0. 813 uint32_t Binary = (Imm8 >> 2) & 0xff; 814 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 815 if (isAdd) 816 Binary |= (1 << 8); 817 Binary |= (Reg << 9); 818 return Binary; 819} 820 821/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 822/// 'reg + imm8<<2' operand. 823uint32_t ARMMCCodeEmitter:: 824getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 825 SmallVectorImpl<MCFixup> &Fixups) const { 826 // {11-8} = reg 827 // {7-0} = imm8 828 const MCOperand &MO = MI.getOperand(OpIdx); 829 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 830 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 831 unsigned Imm8 = MO1.getImm(); 832 return (Reg << 8) | Imm8; 833} 834 835// FIXME: This routine assumes that a binary 836// expression will always result in a PCRel expression 837// In reality, its only true if one or more subexpressions 838// is itself a PCRel (i.e. "." in asm or some other pcrel construct) 839// but this is good enough for now. 840static bool EvaluateAsPCRel(const MCExpr *Expr) { 841 switch (Expr->getKind()) { 842 default: llvm_unreachable("Unexpected expression type"); 843 case MCExpr::SymbolRef: return false; 844 case MCExpr::Binary: return true; 845 } 846} 847 848uint32_t 849ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 850 SmallVectorImpl<MCFixup> &Fixups) const { 851 // {20-16} = imm{15-12} 852 // {11-0} = imm{11-0} 853 const MCOperand &MO = MI.getOperand(OpIdx); 854 if (MO.isImm()) 855 // Hi / lo 16 bits already extracted during earlier passes. 856 return static_cast<unsigned>(MO.getImm()); 857 858 // Handle :upper16: and :lower16: assembly prefixes. 859 const MCExpr *E = MO.getExpr(); 860 if (E->getKind() == MCExpr::Target) { 861 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 862 E = ARM16Expr->getSubExpr(); 863 864 MCFixupKind Kind; 865 switch (ARM16Expr->getKind()) { 866 default: llvm_unreachable("Unsupported ARMFixup"); 867 case ARMMCExpr::VK_ARM_HI16: 868 if (!isTargetDarwin() && EvaluateAsPCRel(E)) 869 Kind = MCFixupKind(isThumb2() 870 ? ARM::fixup_t2_movt_hi16_pcrel 871 : ARM::fixup_arm_movt_hi16_pcrel); 872 else 873 Kind = MCFixupKind(isThumb2() 874 ? ARM::fixup_t2_movt_hi16 875 : ARM::fixup_arm_movt_hi16); 876 break; 877 case ARMMCExpr::VK_ARM_LO16: 878 if (!isTargetDarwin() && EvaluateAsPCRel(E)) 879 Kind = MCFixupKind(isThumb2() 880 ? ARM::fixup_t2_movw_lo16_pcrel 881 : ARM::fixup_arm_movw_lo16_pcrel); 882 else 883 Kind = MCFixupKind(isThumb2() 884 ? ARM::fixup_t2_movw_lo16 885 : ARM::fixup_arm_movw_lo16); 886 break; 887 } 888 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc())); 889 return 0; 890 }; 891 892 llvm_unreachable("Unsupported MCExpr type in MCOperand!"); 893} 894 895uint32_t ARMMCCodeEmitter:: 896getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 897 SmallVectorImpl<MCFixup> &Fixups) const { 898 const MCOperand &MO = MI.getOperand(OpIdx); 899 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 900 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 901 unsigned Rn = getARMRegisterNumbering(MO.getReg()); 902 unsigned Rm = getARMRegisterNumbering(MO1.getReg()); 903 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 904 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 905 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 906 unsigned SBits = getShiftOp(ShOp); 907 908 // {16-13} = Rn 909 // {12} = isAdd 910 // {11-0} = shifter 911 // {3-0} = Rm 912 // {4} = 0 913 // {6-5} = type 914 // {11-7} = imm 915 uint32_t Binary = Rm; 916 Binary |= Rn << 13; 917 Binary |= SBits << 5; 918 Binary |= ShImm << 7; 919 if (isAdd) 920 Binary |= 1 << 12; 921 return Binary; 922} 923 924uint32_t ARMMCCodeEmitter:: 925getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 926 SmallVectorImpl<MCFixup> &Fixups) const { 927 // {17-14} Rn 928 // {13} 1 == imm12, 0 == Rm 929 // {12} isAdd 930 // {11-0} imm12/Rm 931 const MCOperand &MO = MI.getOperand(OpIdx); 932 unsigned Rn = getARMRegisterNumbering(MO.getReg()); 933 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups); 934 Binary |= Rn << 14; 935 return Binary; 936} 937 938uint32_t ARMMCCodeEmitter:: 939getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 940 SmallVectorImpl<MCFixup> &Fixups) const { 941 // {13} 1 == imm12, 0 == Rm 942 // {12} isAdd 943 // {11-0} imm12/Rm 944 const MCOperand &MO = MI.getOperand(OpIdx); 945 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 946 unsigned Imm = MO1.getImm(); 947 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 948 bool isReg = MO.getReg() != 0; 949 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 950 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 951 if (isReg) { 952 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 953 Binary <<= 7; // Shift amount is bits [11:7] 954 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 955 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0] 956 } 957 return Binary | (isAdd << 12) | (isReg << 13); 958} 959 960uint32_t ARMMCCodeEmitter:: 961getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 962 SmallVectorImpl<MCFixup> &Fixups) const { 963 // {4} isAdd 964 // {3-0} Rm 965 const MCOperand &MO = MI.getOperand(OpIdx); 966 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 967 bool isAdd = MO1.getImm() != 0; 968 return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4); 969} 970 971uint32_t ARMMCCodeEmitter:: 972getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 973 SmallVectorImpl<MCFixup> &Fixups) const { 974 // {9} 1 == imm8, 0 == Rm 975 // {8} isAdd 976 // {7-4} imm7_4/zero 977 // {3-0} imm3_0/Rm 978 const MCOperand &MO = MI.getOperand(OpIdx); 979 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 980 unsigned Imm = MO1.getImm(); 981 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 982 bool isImm = MO.getReg() == 0; 983 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 984 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 985 if (!isImm) 986 Imm8 = getARMRegisterNumbering(MO.getReg()); 987 return Imm8 | (isAdd << 8) | (isImm << 9); 988} 989 990uint32_t ARMMCCodeEmitter:: 991getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 992 SmallVectorImpl<MCFixup> &Fixups) const { 993 // {13} 1 == imm8, 0 == Rm 994 // {12-9} Rn 995 // {8} isAdd 996 // {7-4} imm7_4/zero 997 // {3-0} imm3_0/Rm 998 const MCOperand &MO = MI.getOperand(OpIdx); 999 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1000 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1001 1002 // If The first operand isn't a register, we have a label reference. 1003 if (!MO.isReg()) { 1004 unsigned Rn = getARMRegisterNumbering(ARM::PC); // Rn is PC. 1005 1006 assert(MO.isExpr() && "Unexpected machine operand type!"); 1007 const MCExpr *Expr = MO.getExpr(); 1008 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1009 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 1010 1011 ++MCNumCPRelocations; 1012 return (Rn << 9) | (1 << 13); 1013 } 1014 unsigned Rn = getARMRegisterNumbering(MO.getReg()); 1015 unsigned Imm = MO2.getImm(); 1016 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1017 bool isImm = MO1.getReg() == 0; 1018 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1019 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1020 if (!isImm) 1021 Imm8 = getARMRegisterNumbering(MO1.getReg()); 1022 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1023} 1024 1025/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1026uint32_t ARMMCCodeEmitter:: 1027getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1028 SmallVectorImpl<MCFixup> &Fixups) const { 1029 // [SP, #imm] 1030 // {7-0} = imm8 1031 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1032 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1033 "Unexpected base register!"); 1034 1035 // The immediate is already shifted for the implicit zeroes, so no change 1036 // here. 1037 return MO1.getImm() & 0xff; 1038} 1039 1040/// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1041uint32_t ARMMCCodeEmitter:: 1042getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1043 SmallVectorImpl<MCFixup> &Fixups) const { 1044 // [Rn, #imm] 1045 // {7-3} = imm5 1046 // {2-0} = Rn 1047 const MCOperand &MO = MI.getOperand(OpIdx); 1048 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1049 unsigned Rn = getARMRegisterNumbering(MO.getReg()); 1050 unsigned Imm5 = MO1.getImm(); 1051 return ((Imm5 & 0x1f) << 3) | Rn; 1052} 1053 1054/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1055uint32_t ARMMCCodeEmitter:: 1056getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1057 SmallVectorImpl<MCFixup> &Fixups) const { 1058 const MCOperand MO = MI.getOperand(OpIdx); 1059 if (MO.isExpr()) 1060 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); 1061 return (MO.getImm() >> 2); 1062} 1063 1064/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. 1065uint32_t ARMMCCodeEmitter:: 1066getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1067 SmallVectorImpl<MCFixup> &Fixups) const { 1068 // {12-9} = reg 1069 // {8} = (U)nsigned (add == '1', sub == '0') 1070 // {7-0} = imm8 1071 unsigned Reg, Imm8; 1072 bool isAdd; 1073 // If The first operand isn't a register, we have a label reference. 1074 const MCOperand &MO = MI.getOperand(OpIdx); 1075 if (!MO.isReg()) { 1076 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 1077 Imm8 = 0; 1078 isAdd = false; // 'U' bit is handled as part of the fixup. 1079 1080 assert(MO.isExpr() && "Unexpected machine operand type!"); 1081 const MCExpr *Expr = MO.getExpr(); 1082 MCFixupKind Kind; 1083 if (isThumb2()) 1084 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1085 else 1086 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1087 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 1088 1089 ++MCNumCPRelocations; 1090 } else { 1091 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 1092 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1093 } 1094 1095 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1096 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1097 if (isAdd) 1098 Binary |= (1 << 8); 1099 Binary |= (Reg << 9); 1100 return Binary; 1101} 1102 1103unsigned ARMMCCodeEmitter:: 1104getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1105 SmallVectorImpl<MCFixup> &Fixups) const { 1106 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1107 // shifted. The second is Rs, the amount to shift by, and the third specifies 1108 // the type of the shift. 1109 // 1110 // {3-0} = Rm. 1111 // {4} = 1 1112 // {6-5} = type 1113 // {11-8} = Rs 1114 // {7} = 0 1115 1116 const MCOperand &MO = MI.getOperand(OpIdx); 1117 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1118 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1119 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1120 1121 // Encode Rm. 1122 unsigned Binary = getARMRegisterNumbering(MO.getReg()); 1123 1124 // Encode the shift opcode. 1125 unsigned SBits = 0; 1126 unsigned Rs = MO1.getReg(); 1127 if (Rs) { 1128 // Set shift operand (bit[7:4]). 1129 // LSL - 0001 1130 // LSR - 0011 1131 // ASR - 0101 1132 // ROR - 0111 1133 switch (SOpc) { 1134 default: llvm_unreachable("Unknown shift opc!"); 1135 case ARM_AM::lsl: SBits = 0x1; break; 1136 case ARM_AM::lsr: SBits = 0x3; break; 1137 case ARM_AM::asr: SBits = 0x5; break; 1138 case ARM_AM::ror: SBits = 0x7; break; 1139 } 1140 } 1141 1142 Binary |= SBits << 4; 1143 1144 // Encode the shift operation Rs. 1145 // Encode Rs bit[11:8]. 1146 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1147 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 1148} 1149 1150unsigned ARMMCCodeEmitter:: 1151getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1152 SmallVectorImpl<MCFixup> &Fixups) const { 1153 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1154 // shifted. The second is the amount to shift by. 1155 // 1156 // {3-0} = Rm. 1157 // {4} = 0 1158 // {6-5} = type 1159 // {11-7} = imm 1160 1161 const MCOperand &MO = MI.getOperand(OpIdx); 1162 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1163 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1164 1165 // Encode Rm. 1166 unsigned Binary = getARMRegisterNumbering(MO.getReg()); 1167 1168 // Encode the shift opcode. 1169 unsigned SBits = 0; 1170 1171 // Set shift operand (bit[6:4]). 1172 // LSL - 000 1173 // LSR - 010 1174 // ASR - 100 1175 // ROR - 110 1176 // RRX - 110 and bit[11:8] clear. 1177 switch (SOpc) { 1178 default: llvm_unreachable("Unknown shift opc!"); 1179 case ARM_AM::lsl: SBits = 0x0; break; 1180 case ARM_AM::lsr: SBits = 0x2; break; 1181 case ARM_AM::asr: SBits = 0x4; break; 1182 case ARM_AM::ror: SBits = 0x6; break; 1183 case ARM_AM::rrx: 1184 Binary |= 0x60; 1185 return Binary; 1186 } 1187 1188 // Encode shift_imm bit[11:7]. 1189 Binary |= SBits << 4; 1190 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1191 assert(Offset && "Offset must be in range 1-32!"); 1192 if (Offset == 32) Offset = 0; 1193 return Binary | (Offset << 7); 1194} 1195 1196 1197unsigned ARMMCCodeEmitter:: 1198getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1199 SmallVectorImpl<MCFixup> &Fixups) const { 1200 const MCOperand &MO1 = MI.getOperand(OpNum); 1201 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1202 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1203 1204 // Encoded as [Rn, Rm, imm]. 1205 // FIXME: Needs fixup support. 1206 unsigned Value = getARMRegisterNumbering(MO1.getReg()); 1207 Value <<= 4; 1208 Value |= getARMRegisterNumbering(MO2.getReg()); 1209 Value <<= 2; 1210 Value |= MO3.getImm(); 1211 1212 return Value; 1213} 1214 1215unsigned ARMMCCodeEmitter:: 1216getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 1217 SmallVectorImpl<MCFixup> &Fixups) const { 1218 const MCOperand &MO1 = MI.getOperand(OpNum); 1219 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1220 1221 // FIXME: Needs fixup support. 1222 unsigned Value = getARMRegisterNumbering(MO1.getReg()); 1223 1224 // Even though the immediate is 8 bits long, we need 9 bits in order 1225 // to represent the (inverse of the) sign bit. 1226 Value <<= 9; 1227 int32_t tmp = (int32_t)MO2.getImm(); 1228 if (tmp < 0) 1229 tmp = abs(tmp); 1230 else 1231 Value |= 256; // Set the ADD bit 1232 Value |= tmp & 255; 1233 return Value; 1234} 1235 1236unsigned ARMMCCodeEmitter:: 1237getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1238 SmallVectorImpl<MCFixup> &Fixups) const { 1239 const MCOperand &MO1 = MI.getOperand(OpNum); 1240 1241 // FIXME: Needs fixup support. 1242 unsigned Value = 0; 1243 int32_t tmp = (int32_t)MO1.getImm(); 1244 if (tmp < 0) 1245 tmp = abs(tmp); 1246 else 1247 Value |= 256; // Set the ADD bit 1248 Value |= tmp & 255; 1249 return Value; 1250} 1251 1252unsigned ARMMCCodeEmitter:: 1253getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 1254 SmallVectorImpl<MCFixup> &Fixups) const { 1255 const MCOperand &MO1 = MI.getOperand(OpNum); 1256 1257 // FIXME: Needs fixup support. 1258 unsigned Value = 0; 1259 int32_t tmp = (int32_t)MO1.getImm(); 1260 if (tmp < 0) 1261 tmp = abs(tmp); 1262 else 1263 Value |= 4096; // Set the ADD bit 1264 Value |= tmp & 4095; 1265 return Value; 1266} 1267 1268unsigned ARMMCCodeEmitter:: 1269getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1270 SmallVectorImpl<MCFixup> &Fixups) const { 1271 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1272 // shifted. The second is the amount to shift by. 1273 // 1274 // {3-0} = Rm. 1275 // {4} = 0 1276 // {6-5} = type 1277 // {11-7} = imm 1278 1279 const MCOperand &MO = MI.getOperand(OpIdx); 1280 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1281 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1282 1283 // Encode Rm. 1284 unsigned Binary = getARMRegisterNumbering(MO.getReg()); 1285 1286 // Encode the shift opcode. 1287 unsigned SBits = 0; 1288 // Set shift operand (bit[6:4]). 1289 // LSL - 000 1290 // LSR - 010 1291 // ASR - 100 1292 // ROR - 110 1293 switch (SOpc) { 1294 default: llvm_unreachable("Unknown shift opc!"); 1295 case ARM_AM::lsl: SBits = 0x0; break; 1296 case ARM_AM::lsr: SBits = 0x2; break; 1297 case ARM_AM::asr: SBits = 0x4; break; 1298 case ARM_AM::rrx: // FALLTHROUGH 1299 case ARM_AM::ror: SBits = 0x6; break; 1300 } 1301 1302 Binary |= SBits << 4; 1303 if (SOpc == ARM_AM::rrx) 1304 return Binary; 1305 1306 // Encode shift_imm bit[11:7]. 1307 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1308} 1309 1310unsigned ARMMCCodeEmitter:: 1311getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1312 SmallVectorImpl<MCFixup> &Fixups) const { 1313 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the 1314 // msb of the mask. 1315 const MCOperand &MO = MI.getOperand(Op); 1316 uint32_t v = ~MO.getImm(); 1317 uint32_t lsb = CountTrailingZeros_32(v); 1318 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1; 1319 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1320 return lsb | (msb << 5); 1321} 1322 1323unsigned ARMMCCodeEmitter:: 1324getRegisterListOpValue(const MCInst &MI, unsigned Op, 1325 SmallVectorImpl<MCFixup> &Fixups) const { 1326 // VLDM/VSTM: 1327 // {12-8} = Vd 1328 // {7-0} = Number of registers 1329 // 1330 // LDM/STM: 1331 // {15-0} = Bitfield of GPRs. 1332 unsigned Reg = MI.getOperand(Op).getReg(); 1333 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1334 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1335 1336 unsigned Binary = 0; 1337 1338 if (SPRRegs || DPRRegs) { 1339 // VLDM/VSTM 1340 unsigned RegNo = getARMRegisterNumbering(Reg); 1341 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1342 Binary |= (RegNo & 0x1f) << 8; 1343 if (SPRRegs) 1344 Binary |= NumRegs; 1345 else 1346 Binary |= NumRegs * 2; 1347 } else { 1348 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1349 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg()); 1350 Binary |= 1 << RegNo; 1351 } 1352 } 1353 1354 return Binary; 1355} 1356 1357/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1358/// with the alignment operand. 1359unsigned ARMMCCodeEmitter:: 1360getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1361 SmallVectorImpl<MCFixup> &Fixups) const { 1362 const MCOperand &Reg = MI.getOperand(Op); 1363 const MCOperand &Imm = MI.getOperand(Op + 1); 1364 1365 unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 1366 unsigned Align = 0; 1367 1368 switch (Imm.getImm()) { 1369 default: break; 1370 case 2: 1371 case 4: 1372 case 8: Align = 0x01; break; 1373 case 16: Align = 0x02; break; 1374 case 32: Align = 0x03; break; 1375 } 1376 1377 return RegNo | (Align << 4); 1378} 1379 1380/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1381/// along with the alignment operand for use in VST1 and VLD1 with size 32. 1382unsigned ARMMCCodeEmitter:: 1383getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1384 SmallVectorImpl<MCFixup> &Fixups) const { 1385 const MCOperand &Reg = MI.getOperand(Op); 1386 const MCOperand &Imm = MI.getOperand(Op + 1); 1387 1388 unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 1389 unsigned Align = 0; 1390 1391 switch (Imm.getImm()) { 1392 default: break; 1393 case 8: 1394 case 16: 1395 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1396 case 2: Align = 0x00; break; 1397 case 4: Align = 0x03; break; 1398 } 1399 1400 return RegNo | (Align << 4); 1401} 1402 1403 1404/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1405/// alignment operand for use in VLD-dup instructions. This is the same as 1406/// getAddrMode6AddressOpValue except for the alignment encoding, which is 1407/// different for VLD4-dup. 1408unsigned ARMMCCodeEmitter:: 1409getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1410 SmallVectorImpl<MCFixup> &Fixups) const { 1411 const MCOperand &Reg = MI.getOperand(Op); 1412 const MCOperand &Imm = MI.getOperand(Op + 1); 1413 1414 unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); 1415 unsigned Align = 0; 1416 1417 switch (Imm.getImm()) { 1418 default: break; 1419 case 2: 1420 case 4: 1421 case 8: Align = 0x01; break; 1422 case 16: Align = 0x03; break; 1423 } 1424 1425 return RegNo | (Align << 4); 1426} 1427 1428unsigned ARMMCCodeEmitter:: 1429getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1430 SmallVectorImpl<MCFixup> &Fixups) const { 1431 const MCOperand &MO = MI.getOperand(Op); 1432 if (MO.getReg() == 0) return 0x0D; 1433 return getARMRegisterNumbering(MO.getReg()); 1434} 1435 1436unsigned ARMMCCodeEmitter:: 1437getShiftRight8Imm(const MCInst &MI, unsigned Op, 1438 SmallVectorImpl<MCFixup> &Fixups) const { 1439 return 8 - MI.getOperand(Op).getImm(); 1440} 1441 1442unsigned ARMMCCodeEmitter:: 1443getShiftRight16Imm(const MCInst &MI, unsigned Op, 1444 SmallVectorImpl<MCFixup> &Fixups) const { 1445 return 16 - MI.getOperand(Op).getImm(); 1446} 1447 1448unsigned ARMMCCodeEmitter:: 1449getShiftRight32Imm(const MCInst &MI, unsigned Op, 1450 SmallVectorImpl<MCFixup> &Fixups) const { 1451 return 32 - MI.getOperand(Op).getImm(); 1452} 1453 1454unsigned ARMMCCodeEmitter:: 1455getShiftRight64Imm(const MCInst &MI, unsigned Op, 1456 SmallVectorImpl<MCFixup> &Fixups) const { 1457 return 64 - MI.getOperand(Op).getImm(); 1458} 1459 1460void ARMMCCodeEmitter:: 1461EncodeInstruction(const MCInst &MI, raw_ostream &OS, 1462 SmallVectorImpl<MCFixup> &Fixups) const { 1463 // Pseudo instructions don't get encoded. 1464 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1465 uint64_t TSFlags = Desc.TSFlags; 1466 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1467 return; 1468 1469 int Size; 1470 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1471 Size = Desc.getSize(); 1472 else 1473 llvm_unreachable("Unexpected instruction size!"); 1474 1475 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); 1476 // Thumb 32-bit wide instructions need to emit the high order halfword 1477 // first. 1478 if (isThumb() && Size == 4) { 1479 EmitConstant(Binary >> 16, 2, OS); 1480 EmitConstant(Binary & 0xffff, 2, OS); 1481 } else 1482 EmitConstant(Binary, Size, OS); 1483 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1484} 1485 1486#include "ARMGenMCCodeEmitter.inc" 1487