R600MCCodeEmitter.cpp revision d3293b49f9c7af741d2edd3062499fb50db0e89b 
1//===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11///
12/// \brief The R600 code emitter produces machine code that can be executed
13/// directly on the GPU device.
14//
15//===----------------------------------------------------------------------===//
16
17#include "R600Defines.h"
18#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
19#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/Support/raw_ostream.h"
27#include <stdio.h>
28
29using namespace llvm;
30
31namespace {
32
33class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
34  R600MCCodeEmitter(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
35  void operator=(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
36  const MCInstrInfo &MCII;
37  const MCRegisterInfo &MRI;
38  const MCSubtargetInfo &STI;
39
40public:
41
42  R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
43                    const MCSubtargetInfo &sti)
44    : MCII(mcii), MRI(mri), STI(sti) { }
45
46  /// \brief Encode the instruction and write it to the OS.
47  virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
48                         SmallVectorImpl<MCFixup> &Fixups) const;
49
50  /// \returns the encoding for an MCOperand.
51  virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
52                                     SmallVectorImpl<MCFixup> &Fixups) const;
53private:
54
55  void EmitByte(unsigned int byte, raw_ostream &OS) const;
56
57  void Emit(uint32_t value, raw_ostream &OS) const;
58  void Emit(uint64_t value, raw_ostream &OS) const;
59
60  unsigned getHWRegChan(unsigned reg) const;
61  unsigned getHWReg(unsigned regNo) const;
62
63};
64
65} // End anonymous namespace
66
67enum RegElement {
68  ELEMENT_X = 0,
69  ELEMENT_Y,
70  ELEMENT_Z,
71  ELEMENT_W
72};
73
74enum FCInstr {
75  FC_IF_PREDICATE = 0,
76  FC_ELSE,
77  FC_ENDIF,
78  FC_BGNLOOP,
79  FC_ENDLOOP,
80  FC_BREAK_PREDICATE,
81  FC_CONTINUE
82};
83
84MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
85                                           const MCRegisterInfo &MRI,
86                                           const MCSubtargetInfo &STI) {
87  return new R600MCCodeEmitter(MCII, MRI, STI);
88}
89
90void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
91                                       SmallVectorImpl<MCFixup> &Fixups) const {
92  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
93  if (MI.getOpcode() == AMDGPU::RETURN ||
94    MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
95    MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
96    MI.getOpcode() == AMDGPU::BUNDLE ||
97    MI.getOpcode() == AMDGPU::KILL) {
98    return;
99  } else if (IS_VTX(Desc)) {
100    uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
101    uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
102    InstWord2 |= 1 << 19;
103
104    Emit(InstWord01, OS);
105    Emit(InstWord2, OS);
106    Emit((u_int32_t) 0, OS);
107  } else if (IS_TEX(Desc)) {
108      int64_t Sampler = MI.getOperand(14).getImm();
109
110      uint32_t SrcSelect[4] = {
111        MI.getOperand(2).getImm(),
112        MI.getOperand(3).getImm(),
113        MI.getOperand(4).getImm(),
114        MI.getOperand(5).getImm()
115      };
116      uint32_t Offsets[3] = {
117        MI.getOperand(6).getImm() & 0x1F,
118        MI.getOperand(7).getImm() & 0x1F,
119        MI.getOperand(8).getImm() & 0x1F
120      };
121
122      uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups);
123      uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
124          SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
125          SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
126          Offsets[2] << 10;
127
128      Emit(Word01, OS);
129      Emit(Word2, OS);
130      Emit((u_int32_t) 0, OS);
131  } else {
132    uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
133    if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
134       ((Desc.TSFlags & R600_InstFlag::OP1) ||
135         Desc.TSFlags & R600_InstFlag::OP2)) {
136      uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
137      Inst &= ~(0x3FFULL << 39);
138      Inst |= ISAOpCode << 1;
139    }
140    Emit(Inst, OS);
141  }
142}
143
144void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
145  OS.write((uint8_t) Byte & 0xff);
146}
147
148void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
149  for (unsigned i = 0; i < 4; i++) {
150    OS.write((uint8_t) ((Value >> (8 * i)) & 0xff));
151  }
152}
153
154void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
155  for (unsigned i = 0; i < 8; i++) {
156    EmitByte((Value >> (8 * i)) & 0xff, OS);
157  }
158}
159
160unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
161  return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
162}
163
164unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
165  return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
166}
167
168uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
169                                              const MCOperand &MO,
170                                        SmallVectorImpl<MCFixup> &Fixup) const {
171  if (MO.isReg()) {
172    if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
173      return MRI.getEncodingValue(MO.getReg());
174    } else {
175      return getHWReg(MO.getReg());
176    }
177  } else if (MO.isImm()) {
178    return MO.getImm();
179  } else {
180    assert(0);
181    return 0;
182  }
183}
184
185#include "AMDGPUGenMCCodeEmitter.inc"
186