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..01-Nov-20134 KiB

AsmParser/01-Nov-20134 KiB

CMakeLists.txt01-Nov-20131.2 KiB

Disassembler/01-Nov-20134 KiB

InstPrinter/01-Nov-20134 KiB

LLVMBuild.txt01-Nov-20131 KiB

Makefile01-Nov-2013866

MCTargetDesc/01-Nov-20134 KiB

README.txt01-Nov-20135.5 KiB

SystemZ.h01-Nov-20133.2 KiB

SystemZ.td01-Nov-20132.5 KiB

SystemZAsmPrinter.cpp01-Nov-20134.1 KiB

SystemZAsmPrinter.h01-Nov-20131.7 KiB

SystemZCallingConv.cpp01-Nov-2013680

SystemZCallingConv.h01-Nov-2013619

SystemZCallingConv.td01-Nov-20133 KiB

SystemZConstantPoolValue.cpp01-Nov-20132 KiB

SystemZConstantPoolValue.h01-Nov-20131.7 KiB

SystemZElimCompare.cpp01-Nov-201315.8 KiB

SystemZFrameLowering.cpp01-Nov-201319.1 KiB

SystemZFrameLowering.h01-Nov-20133 KiB

SystemZInstrBuilder.h01-Nov-20131.7 KiB

SystemZInstrFormats.td01-Nov-201348 KiB

SystemZInstrFP.td01-Nov-201313.8 KiB

SystemZInstrInfo.cpp01-Nov-201329.7 KiB

SystemZInstrInfo.h01-Nov-20139.2 KiB

SystemZInstrInfo.td01-Nov-201352.7 KiB

SystemZISelDAGToDAG.cpp01-Nov-201336.8 KiB

SystemZISelLowering.cpp01-Nov-201398.6 KiB

SystemZISelLowering.h01-Nov-201310.1 KiB

SystemZLongBranch.cpp01-Nov-201315.4 KiB

SystemZMachineFunctionInfo.h01-Nov-20132.5 KiB

SystemZMCInstLower.cpp01-Nov-20133.8 KiB

SystemZMCInstLower.h01-Nov-20131.3 KiB

SystemZOperands.td01-Nov-201318.3 KiB

SystemZOperators.td01-Nov-201312.4 KiB

SystemZPatterns.td01-Nov-20134.1 KiB

SystemZProcessors.td01-Nov-20131.4 KiB

SystemZRegisterInfo.cpp01-Nov-20135.2 KiB

SystemZRegisterInfo.h01-Nov-20131.9 KiB

SystemZRegisterInfo.td01-Nov-20135.8 KiB

SystemZSelectionDAGInfo.cpp01-Nov-20135 KiB

SystemZSelectionDAGInfo.h01-Nov-20131.5 KiB

SystemZSubtarget.cpp01-Nov-20132 KiB

SystemZSubtarget.h01-Nov-20131.8 KiB

SystemZTargetMachine.cpp01-Nov-20134 KiB

SystemZTargetMachine.h01-Nov-20132.3 KiB

TargetInfo/01-Nov-20134 KiB

README.txt

1//===---------------------------------------------------------------------===//
2// Random notes about and ideas for the SystemZ backend.
3//===---------------------------------------------------------------------===//
4
5The initial backend is deliberately restricted to z10.  We should add support
6for later architectures at some point.
7
8--
9
10SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() is passed "m" for all
11inline asm memory constraints; it doesn't get to see the original constraint.
12This means that it must conservatively treat all inline asm constraints
13as the most restricted type, "R".
14
15--
16
17If an inline asm ties an i32 "r" result to an i64 input, the input
18will be treated as an i32, leaving the upper bits uninitialised.
19For example:
20
21define void @f4(i32 *%dst) {
22  %val = call i32 asm "blah $0", "=r,0" (i64 103)
23  store i32 %val, i32 *%dst
24  ret void
25}
26
27from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
28to load 103.  This seems to be a general target-independent problem.
29
30--
31
32The tuning of the choice between LOAD ADDRESS (LA) and addition in
33SystemZISelDAGToDAG.cpp is suspect.  It should be tweaked based on
34performance measurements.
35
36--
37
38We don't support tail calls at present.
39
40--
41
42We don't support prefetching yet.
43
44--
45
46There is no scheduling support.
47
48--
49
50We don't use the BRANCH ON COUNT or BRANCH ON INDEX families of instruction.
51
52--
53
54We might want to use BRANCH ON CONDITION for conditional indirect calls
55and conditional returns.
56
57--
58
59We don't use the condition code results of anything except comparisons.
60
61Implementing this may need something more finely grained than the z_cmp
62and z_ucmp that we have now.  It might (or might not) also be useful to
63have a mask of "don't care" values in conditional branches.  For example,
64integer comparisons never set CC to 3, so the bottom bit of the CC mask
65isn't particularly relevant.  JNLH and JE are equally good for testing
66equality after an integer comparison, etc.
67
68--
69
70We don't use the LOAD AND TEST or TEST DATA CLASS instructions.
71
72--
73
74We could use the generic floating-point forms of LOAD COMPLEMENT,
75LOAD NEGATIVE and LOAD POSITIVE in cases where we don't need the
76condition codes.  For example, we could use LCDFR instead of LCDBR.
77
78--
79
80We don't optimize block memory operations.
81
82It's definitely worth using things like MVC, CLC, NC, XC and OC with
83constant lengths.  MVCIN may be worthwhile too.
84
85We should probably implement things like memcpy using MVC with EXECUTE.
86Likewise memcmp and CLC.  MVCLE and CLCLE could be useful too.
87
88--
89
90We don't optimize string operations.
91
92MVST, CLST, SRST and CUSE could be useful here.  Some of the TRANSLATE
93family might be too, although they are probably more difficult to exploit.
94
95--
96
97We don't take full advantage of builtins like fabsl because the calling
98conventions require f128s to be returned by invisible reference.
99
100--
101
102ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
103produce a carry.  SUBTRACT LOGICAL IMMEDIATE could be useful when we
104need to produce a borrow.  (Note that there are no memory forms of
105ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
106part of 128-bit memory operations would probably need to be done
107via a register.)
108
109--
110
111We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
112(LRVH and STRVH).
113
114--
115
116We could take advantage of the various ... UNDER MASK instructions,
117such as ICM and STCM.
118
119--
120
121DAGCombiner can detect integer absolute, but there's not yet an associated
122ISD opcode.  We could add one and implement it using LOAD POSITIVE.
123Negated absolutes could use LOAD NEGATIVE.
124
125--
126
127DAGCombiner doesn't yet fold truncations of extended loads.  Functions like:
128
129    unsigned long f (unsigned long x, unsigned short *y)
130    {
131      return (x << 32) | *y;
132    }
133
134therefore end up as:
135
136        sllg    %r2, %r2, 32
137        llgh    %r0, 0(%r3)
138        lr      %r2, %r0
139        br      %r14
140
141but truncating the load would give:
142
143        sllg    %r2, %r2, 32
144        lh      %r2, 0(%r3)
145        br      %r14
146
147--
148
149Functions like:
150
151define i64 @f1(i64 %a) {
152  %and = and i64 %a, 1
153  ret i64 %and
154}
155
156ought to be implemented as:
157
158        lhi     %r0, 1
159        ngr     %r2, %r0
160        br      %r14
161
162but two-address optimisations reverse the order of the AND and force:
163
164        lhi     %r0, 1
165        ngr     %r0, %r2
166        lgr     %r2, %r0
167        br      %r14
168
169CodeGen/SystemZ/and-04.ll has several examples of this.
170
171--
172
173Out-of-range displacements are usually handled by loading the full
174address into a register.  In many cases it would be better to create
175an anchor point instead.  E.g. for:
176
177define void @f4a(i128 *%aptr, i64 %base) {
178  %addr = add i64 %base, 524288
179  %bptr = inttoptr i64 %addr to i128 *
180  %a = load volatile i128 *%aptr
181  %b = load i128 *%bptr
182  %add = add i128 %a, %b
183  store i128 %add, i128 *%aptr
184  ret void
185}
186
187(from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
188into separate registers, rather than using %base+524288 as a base for both.
189
190--
191
192Dynamic stack allocations round the size to 8 bytes and then allocate
193that rounded amount.  It would be simpler to subtract the unrounded
194size from the copy of the stack pointer and then align the result.
195See CodeGen/SystemZ/alloca-01.ll for an example.
196
197--
198
199Atomic loads and stores use the default compare-and-swap based implementation.
200This is much too conservative in practice, since the architecture guarantees
201that 1-, 2-, 4- and 8-byte loads and stores to aligned addresses are
202inherently atomic.
203
204--
205
206If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.
207
208--
209
210We might want to model all access registers and use them to spill
21132-bit values.
212