r600.h revision 42502b6f03230b828121f60143190c39bc5c8dda
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_H 27#define R600_H 28 29#include <assert.h> 30#include <stdint.h> 31#include <stdio.h> 32#include <util/u_double_list.h> 33#include <pipe/p_compiler.h> 34 35#define RADEON_CTX_MAX_PM4 (64 * 1024 / 4) 36 37#define R600_ERR(fmt, args...) \ 38 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) 39 40typedef uint64_t u64; 41typedef uint32_t u32; 42typedef uint16_t u16; 43typedef uint8_t u8; 44 45struct radeon; 46struct winsys_handle; 47 48enum radeon_family { 49 CHIP_UNKNOWN, 50 CHIP_R100, 51 CHIP_RV100, 52 CHIP_RS100, 53 CHIP_RV200, 54 CHIP_RS200, 55 CHIP_R200, 56 CHIP_RV250, 57 CHIP_RS300, 58 CHIP_RV280, 59 CHIP_R300, 60 CHIP_R350, 61 CHIP_RV350, 62 CHIP_RV380, 63 CHIP_R420, 64 CHIP_R423, 65 CHIP_RV410, 66 CHIP_RS400, 67 CHIP_RS480, 68 CHIP_RS600, 69 CHIP_RS690, 70 CHIP_RS740, 71 CHIP_RV515, 72 CHIP_R520, 73 CHIP_RV530, 74 CHIP_RV560, 75 CHIP_RV570, 76 CHIP_R580, 77 CHIP_R600, 78 CHIP_RV610, 79 CHIP_RV630, 80 CHIP_RV670, 81 CHIP_RV620, 82 CHIP_RV635, 83 CHIP_RS780, 84 CHIP_RS880, 85 CHIP_RV770, 86 CHIP_RV730, 87 CHIP_RV710, 88 CHIP_RV740, 89 CHIP_CEDAR, 90 CHIP_REDWOOD, 91 CHIP_JUNIPER, 92 CHIP_CYPRESS, 93 CHIP_HEMLOCK, 94 CHIP_PALM, 95 CHIP_SUMO, 96 CHIP_SUMO2, 97 CHIP_BARTS, 98 CHIP_TURKS, 99 CHIP_CAICOS, 100 CHIP_CAYMAN, 101 CHIP_LAST, 102}; 103 104enum chip_class { 105 R600, 106 R700, 107 EVERGREEN, 108 CAYMAN, 109}; 110 111struct r600_tiling_info { 112 unsigned num_channels; 113 unsigned num_banks; 114 unsigned group_bytes; 115}; 116 117enum radeon_family r600_get_family(struct radeon *rw); 118enum chip_class r600_get_family_class(struct radeon *radeon); 119struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon); 120unsigned r600_get_clock_crystal_freq(struct radeon *radeon); 121unsigned r600_get_minor_version(struct radeon *radeon); 122unsigned r600_get_num_backends(struct radeon *radeon); 123 124/* r600_bo.c */ 125struct r600_bo; 126struct r600_bo *r600_bo(struct radeon *radeon, 127 unsigned size, unsigned alignment, 128 unsigned binding, unsigned usage); 129struct r600_bo *r600_bo_handle(struct radeon *radeon, 130 unsigned handle, unsigned *array_mode); 131void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx); 132void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo); 133void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, 134 struct r600_bo *src); 135boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo, 136 unsigned stride, struct winsys_handle *whandle); 137static INLINE unsigned r600_bo_offset(struct r600_bo *bo) 138{ 139 return 0; 140} 141 142 143/* R600/R700 STATES */ 144#define R600_GROUP_MAX 16 145#define R600_BLOCK_MAX_BO 32 146#define R600_BLOCK_MAX_REG 128 147 148/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ 149/* there is a block entry for each register so 512 blocks */ 150/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ 151/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ 152#define RANGE_OFFSET_START 0x8000 153#define HASH_SHIFT 9 154#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ 155 156#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) 157#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) 158 159struct r600_pipe_reg { 160 u32 offset; 161 u32 mask; 162 u32 value; 163 struct r600_bo *bo; 164}; 165 166struct r600_pipe_state { 167 unsigned id; 168 unsigned nregs; 169 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG]; 170}; 171 172#define R600_BLOCK_STATUS_ENABLED (1 << 0) 173#define R600_BLOCK_STATUS_DIRTY (1 << 1) 174 175struct r600_block_reloc { 176 struct r600_bo *bo; 177 unsigned flush_flags; 178 unsigned flush_mask; 179 unsigned bo_pm4_index; 180}; 181 182struct r600_block { 183 struct list_head list; 184 unsigned status; 185 unsigned flags; 186 unsigned start_offset; 187 unsigned pm4_ndwords; 188 unsigned pm4_flush_ndwords; 189 unsigned nbo; 190 u16 nreg; 191 u16 nreg_dirty; 192 u32 *reg; 193 u32 pm4[R600_BLOCK_MAX_REG]; 194 unsigned pm4_bo_index[R600_BLOCK_MAX_REG]; 195 struct r600_block_reloc reloc[R600_BLOCK_MAX_BO]; 196}; 197 198struct r600_range { 199 struct r600_block **blocks; 200}; 201 202/* 203 * relocation 204 */ 205#pragma pack(1) 206struct r600_reloc { 207 uint32_t handle; 208 uint32_t read_domain; 209 uint32_t write_domain; 210 uint32_t flags; 211}; 212#pragma pack() 213 214/* 215 * query 216 */ 217struct r600_query { 218 u64 result; 219 /* The kind of query. Currently only OQ is supported. */ 220 unsigned type; 221 /* How many results have been written, in dwords. It's incremented 222 * after end_query and flush. */ 223 unsigned num_results; 224 /* if we've flushed the query */ 225 unsigned state; 226 /* The buffer where query results are stored. */ 227 struct r600_bo *buffer; 228 unsigned buffer_size; 229 /* linked list of queries */ 230 struct list_head list; 231}; 232 233#define R600_QUERY_STATE_STARTED (1 << 0) 234#define R600_QUERY_STATE_ENDED (1 << 1) 235#define R600_QUERY_STATE_SUSPENDED (1 << 2) 236 237#define R600_CONTEXT_DRAW_PENDING (1 << 0) 238#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) 239#define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) 240 241struct r600_context { 242 struct radeon *radeon; 243 struct r600_range *range; 244 unsigned nblocks; 245 struct r600_block **blocks; 246 struct list_head dirty; 247 unsigned pm4_ndwords; 248 unsigned pm4_cdwords; 249 unsigned pm4_dirty_cdwords; 250 unsigned ctx_pm4_ndwords; 251 unsigned nreloc; 252 unsigned creloc; 253 struct r600_reloc *reloc; 254 struct radeon_bo **bo; 255 u32 *pm4; 256 struct list_head query_list; 257 unsigned num_query_running; 258 struct list_head fenced_bo; 259 unsigned max_db; /* for OQ */ 260 unsigned num_dest_buffers; 261 unsigned flags; 262 boolean predicate_drawing; 263}; 264 265struct r600_draw { 266 u32 vgt_num_indices; 267 u32 vgt_num_instances; 268 u32 vgt_index_type; 269 u32 vgt_draw_initiator; 270 u32 indices_bo_offset; 271 struct r600_bo *indices; 272}; 273 274int r600_context_init(struct r600_context *ctx, struct radeon *radeon); 275void r600_context_fini(struct r600_context *ctx); 276void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state); 277void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); 278void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); 279void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); 280void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 281void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 282void r600_context_flush(struct r600_context *ctx); 283void r600_context_dump_bof(struct r600_context *ctx, const char *file); 284void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 285 286struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type); 287void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query); 288boolean r600_context_query_result(struct r600_context *ctx, 289 struct r600_query *query, 290 boolean wait, void *vresult); 291void r600_query_begin(struct r600_context *ctx, struct r600_query *query); 292void r600_query_end(struct r600_context *ctx, struct r600_query *query); 293void r600_context_queries_suspend(struct r600_context *ctx); 294void r600_context_queries_resume(struct r600_context *ctx); 295void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, 296 int flag_wait); 297void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence, 298 unsigned offset, unsigned value); 299void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags); 300void r600_context_flush_dest_caches(struct r600_context *ctx); 301 302int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon); 303void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 304void evergreen_context_flush_dest_caches(struct r600_context *ctx); 305void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); 306void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); 307void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); 308void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 309void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 310 311struct radeon *radeon_decref(struct radeon *radeon); 312 313void _r600_pipe_state_add_reg(struct r600_context *ctx, 314 struct r600_pipe_state *state, 315 u32 offset, u32 value, u32 mask, 316 struct r600_bo *bo); 317 318#define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, bo) 319 320 321#endif 322