r600.h revision 63184bc8b278ba82f5462798b323774c67a019e6
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_H 27#define R600_H 28 29#include <assert.h> 30#include <stdint.h> 31#include <stdio.h> 32#include <util/u_double_list.h> 33#include <pipe/p_compiler.h> 34 35#define RADEON_CTX_MAX_PM4 (64 * 1024 / 4) 36 37#define R600_ERR(fmt, args...) \ 38 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) 39 40typedef uint64_t u64; 41typedef uint32_t u32; 42typedef uint16_t u16; 43typedef uint8_t u8; 44 45struct radeon; 46struct winsys_handle; 47 48enum radeon_family { 49 CHIP_UNKNOWN, 50 CHIP_R100, 51 CHIP_RV100, 52 CHIP_RS100, 53 CHIP_RV200, 54 CHIP_RS200, 55 CHIP_R200, 56 CHIP_RV250, 57 CHIP_RS300, 58 CHIP_RV280, 59 CHIP_R300, 60 CHIP_R350, 61 CHIP_RV350, 62 CHIP_RV380, 63 CHIP_R420, 64 CHIP_R423, 65 CHIP_RV410, 66 CHIP_RS400, 67 CHIP_RS480, 68 CHIP_RS600, 69 CHIP_RS690, 70 CHIP_RS740, 71 CHIP_RV515, 72 CHIP_R520, 73 CHIP_RV530, 74 CHIP_RV560, 75 CHIP_RV570, 76 CHIP_R580, 77 CHIP_R600, 78 CHIP_RV610, 79 CHIP_RV630, 80 CHIP_RV670, 81 CHIP_RV620, 82 CHIP_RV635, 83 CHIP_RS780, 84 CHIP_RS880, 85 CHIP_RV770, 86 CHIP_RV730, 87 CHIP_RV710, 88 CHIP_RV740, 89 CHIP_CEDAR, 90 CHIP_REDWOOD, 91 CHIP_JUNIPER, 92 CHIP_CYPRESS, 93 CHIP_HEMLOCK, 94 CHIP_PALM, 95 CHIP_SUMO, 96 CHIP_SUMO2, 97 CHIP_BARTS, 98 CHIP_TURKS, 99 CHIP_CAICOS, 100 CHIP_CAYMAN, 101 CHIP_LAST, 102}; 103 104enum chip_class { 105 R600, 106 R700, 107 EVERGREEN, 108 CAYMAN, 109}; 110 111struct r600_tiling_info { 112 unsigned num_channels; 113 unsigned num_banks; 114 unsigned group_bytes; 115}; 116 117enum radeon_family r600_get_family(struct radeon *rw); 118enum chip_class r600_get_family_class(struct radeon *radeon); 119struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon); 120unsigned r600_get_clock_crystal_freq(struct radeon *radeon); 121unsigned r600_get_minor_version(struct radeon *radeon); 122unsigned r600_get_num_backends(struct radeon *radeon); 123 124/* r600_bo.c */ 125struct r600_bo; 126struct r600_bo *r600_bo(struct radeon *radeon, 127 unsigned size, unsigned alignment, 128 unsigned binding, unsigned usage); 129struct r600_bo *r600_bo_handle(struct radeon *radeon, 130 unsigned handle, unsigned *array_mode); 131void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx); 132void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo); 133void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, 134 struct r600_bo *src); 135boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo, 136 unsigned stride, struct winsys_handle *whandle); 137static INLINE unsigned r600_bo_offset(struct r600_bo *bo) 138{ 139 return 0; 140} 141 142 143/* R600/R700 STATES */ 144#define R600_GROUP_MAX 16 145#define R600_BLOCK_MAX_BO 32 146#define R600_BLOCK_MAX_REG 128 147 148/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ 149/* there is a block entry for each register so 512 blocks */ 150/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ 151/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ 152#define RANGE_OFFSET_START 0x8000 153#define HASH_SHIFT 9 154#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ 155 156#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) 157#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) 158 159struct r600_pipe_reg { 160 u32 value; 161 u32 mask; 162 struct r600_block *block; 163 struct r600_bo *bo; 164 u32 id; 165}; 166 167struct r600_pipe_state { 168 unsigned id; 169 unsigned nregs; 170 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG]; 171}; 172 173struct r600_pipe_resource_state { 174 unsigned id; 175 u32 val[8]; 176 struct r600_bo *bo[2]; 177}; 178 179#define R600_BLOCK_STATUS_ENABLED (1 << 0) 180#define R600_BLOCK_STATUS_DIRTY (1 << 1) 181 182struct r600_block_reloc { 183 struct r600_bo *bo; 184 unsigned flush_flags; 185 unsigned flush_mask; 186 unsigned bo_pm4_index; 187}; 188 189struct r600_block { 190 struct list_head list; 191 struct list_head enable_list; 192 unsigned status; 193 unsigned flags; 194 unsigned start_offset; 195 unsigned pm4_ndwords; 196 unsigned pm4_flush_ndwords; 197 unsigned nbo; 198 u16 nreg; 199 u16 nreg_dirty; 200 u32 *reg; 201 u32 pm4[R600_BLOCK_MAX_REG]; 202 unsigned pm4_bo_index[R600_BLOCK_MAX_REG]; 203 struct r600_block_reloc reloc[R600_BLOCK_MAX_BO]; 204}; 205 206struct r600_range { 207 struct r600_block **blocks; 208}; 209 210/* 211 * relocation 212 */ 213#pragma pack(1) 214struct r600_reloc { 215 uint32_t handle; 216 uint32_t read_domain; 217 uint32_t write_domain; 218 uint32_t flags; 219}; 220#pragma pack() 221 222/* 223 * query 224 */ 225struct r600_query { 226 u64 result; 227 /* The kind of query. Currently only OQ is supported. */ 228 unsigned type; 229 /* How many results have been written, in dwords. It's incremented 230 * after end_query and flush. */ 231 unsigned num_results; 232 /* if we've flushed the query */ 233 unsigned state; 234 /* The buffer where query results are stored. */ 235 struct r600_bo *buffer; 236 unsigned buffer_size; 237 /* linked list of queries */ 238 struct list_head list; 239}; 240 241#define R600_QUERY_STATE_STARTED (1 << 0) 242#define R600_QUERY_STATE_ENDED (1 << 1) 243#define R600_QUERY_STATE_SUSPENDED (1 << 2) 244 245#define R600_CONTEXT_DRAW_PENDING (1 << 0) 246#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) 247#define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) 248 249struct r600_context { 250 struct radeon *radeon; 251 struct r600_range *range; 252 unsigned nblocks; 253 struct r600_block **blocks; 254 struct list_head dirty; 255 struct list_head enable_list; 256 unsigned pm4_ndwords; 257 unsigned pm4_cdwords; 258 unsigned pm4_dirty_cdwords; 259 unsigned ctx_pm4_ndwords; 260 unsigned nreloc; 261 unsigned creloc; 262 struct r600_reloc *reloc; 263 struct radeon_bo **bo; 264 u32 *pm4; 265 struct list_head query_list; 266 unsigned num_query_running; 267 struct list_head fenced_bo; 268 unsigned max_db; /* for OQ */ 269 unsigned num_dest_buffers; 270 unsigned flags; 271 boolean predicate_drawing; 272 struct r600_range ps_resources; 273 struct r600_range vs_resources; 274 struct r600_range fs_resources; 275 int num_ps_resources, num_vs_resources, num_fs_resources; 276}; 277 278struct r600_draw { 279 u32 vgt_num_indices; 280 u32 vgt_num_instances; 281 u32 vgt_index_type; 282 u32 vgt_draw_initiator; 283 u32 indices_bo_offset; 284 struct r600_bo *indices; 285}; 286 287int r600_context_init(struct r600_context *ctx, struct radeon *radeon); 288void r600_context_fini(struct r600_context *ctx); 289void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state); 290void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 291void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 292void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 293void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 294void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 295void r600_context_flush(struct r600_context *ctx); 296void r600_context_dump_bof(struct r600_context *ctx, const char *file); 297void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 298 299struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type); 300void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query); 301boolean r600_context_query_result(struct r600_context *ctx, 302 struct r600_query *query, 303 boolean wait, void *vresult); 304void r600_query_begin(struct r600_context *ctx, struct r600_query *query); 305void r600_query_end(struct r600_context *ctx, struct r600_query *query); 306void r600_context_queries_suspend(struct r600_context *ctx); 307void r600_context_queries_resume(struct r600_context *ctx); 308void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, 309 int flag_wait); 310void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence, 311 unsigned offset, unsigned value); 312void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags); 313void r600_context_flush_dest_caches(struct r600_context *ctx); 314 315int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon); 316void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 317void evergreen_context_flush_dest_caches(struct r600_context *ctx); 318void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 319void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 320void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 321void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 322void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 323 324struct radeon *radeon_decref(struct radeon *radeon); 325 326void _r600_pipe_state_add_reg(struct r600_context *ctx, 327 struct r600_pipe_state *state, 328 u32 offset, u32 value, u32 mask, 329 u32 range_id, u32 block_id, 330 struct r600_bo *bo); 331 332void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, 333 u32 offset, u32 value, u32 mask, 334 struct r600_bo *bo); 335#define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo) 336 337static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state, 338 u32 value) 339{ 340 state->regs[state->nregs].value = value; 341 state->nregs++; 342} 343 344static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state, 345 u32 value, struct r600_bo *bo) 346{ 347 state->regs[state->nregs].value = value; 348 state->regs[state->nregs].bo = bo; 349 state->nregs++; 350} 351 352#endif 353