radeon_setup_tgsi_llvm.c revision 12a2374da380a9a28cacf968c33b93ba320b0407
1/* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: Tom Stellard <thomas.stellard@amd.com> 24 * 25 */ 26#include "radeon_llvm.h" 27 28#include "gallivm/lp_bld_const.h" 29#include "gallivm/lp_bld_gather.h" 30#include "gallivm/lp_bld_flow.h" 31#include "gallivm/lp_bld_init.h" 32#include "gallivm/lp_bld_intr.h" 33#include "gallivm/lp_bld_swizzle.h" 34#include "tgsi/tgsi_info.h" 35#include "tgsi/tgsi_parse.h" 36#include "util/u_math.h" 37#include "util/u_memory.h" 38#include "util/u_debug.h" 39 40#include <llvm-c/Core.h> 41#include <llvm-c/Transforms/Scalar.h> 42 43static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx) 44{ 45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL; 46} 47 48static struct radeon_llvm_branch * get_current_branch( 49 struct radeon_llvm_context * ctx) 50{ 51 return ctx->branch_depth > 0 ? 52 ctx->branch + (ctx->branch_depth - 1) : NULL; 53} 54 55unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan) 56{ 57 return (index * 4) + chan; 58} 59 60static void radeon_llvm_fetch_args_2_reverse_soa( 61 struct lp_build_tgsi_context * bld_base, 62 struct lp_build_emit_data * emit_data) 63{ 64 assert(emit_data->info->num_src == 2); 65 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst, 66 1, emit_data->chan); 67 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst, 68 0, emit_data->chan); 69 emit_data->arg_count = 2; 70 emit_data->dst_type = LLVMTypeOf(emit_data->args[0]); 71} 72 73static LLVMValueRef emit_swizzle( 74 struct lp_build_tgsi_context * bld_base, 75 LLVMValueRef value, 76 unsigned swizzle_x, 77 unsigned swizzle_y, 78 unsigned swizzle_z, 79 unsigned swizzle_w) 80{ 81 unsigned char swizzles[4]; 82 swizzles[0] = swizzle_x; 83 swizzles[1] = swizzle_y; 84 swizzles[2] = swizzle_z; 85 swizzles[3] = swizzle_w; 86 87 88 return lp_build_swizzle_aos(&bld_base->base, value, swizzles); 89} 90 91static LLVMValueRef 92emit_array_index( 93 struct lp_build_tgsi_soa_context *bld, 94 const struct tgsi_full_src_register *reg, 95 unsigned swizzle) 96{ 97 struct gallivm_state * gallivm = bld->bld_base.base.gallivm; 98 99 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, 100 bld->addr[reg->Indirect.Index][swizzle], ""); 101 LLVMValueRef offset = lp_build_const_int32(gallivm, reg->Register.Index); 102 LLVMValueRef hw_index = LLVMBuildAdd(gallivm->builder, addr, offset, ""); 103 LLVMValueRef soa_index = LLVMBuildMul(gallivm->builder, hw_index, 104 lp_build_const_int32(gallivm, 4), ""); 105 LLVMValueRef array_index = LLVMBuildAdd(gallivm->builder, soa_index, 106 lp_build_const_int32(gallivm, swizzle), ""); 107 108 return array_index; 109} 110 111static LLVMValueRef 112emit_fetch_immediate( 113 struct lp_build_tgsi_context *bld_base, 114 const struct tgsi_full_src_register *reg, 115 enum tgsi_opcode_type type, 116 unsigned swizzle) 117{ 118 LLVMTypeRef ctype; 119 LLVMContextRef ctx = bld_base->base.gallivm->context; 120 121 switch (type) { 122 case TGSI_TYPE_UNSIGNED: 123 case TGSI_TYPE_SIGNED: 124 ctype = LLVMInt32TypeInContext(ctx); 125 break; 126 case TGSI_TYPE_UNTYPED: 127 case TGSI_TYPE_FLOAT: 128 ctype = LLVMFloatTypeInContext(ctx); 129 break; 130 default: 131 ctype = 0; 132 break; 133 } 134 135 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); 136 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype); 137} 138 139static LLVMValueRef 140emit_fetch_input( 141 struct lp_build_tgsi_context *bld_base, 142 const struct tgsi_full_src_register *reg, 143 enum tgsi_opcode_type type, 144 unsigned swizzle) 145{ 146 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 147 if (swizzle == ~0) { 148 LLVMValueRef values[TGSI_NUM_CHANNELS] = {}; 149 unsigned chan; 150 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { 151 values[chan] = ctx->inputs[radeon_llvm_reg_index_soa( 152 reg->Register.Index, chan)]; 153 } 154 return lp_build_gather_values(bld_base->base.gallivm, values, 155 TGSI_NUM_CHANNELS); 156 } else { 157 return bitcast(bld_base, type, ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)]); 158 } 159} 160 161static LLVMValueRef 162emit_fetch_temporary( 163 struct lp_build_tgsi_context *bld_base, 164 const struct tgsi_full_src_register *reg, 165 enum tgsi_opcode_type type, 166 unsigned swizzle) 167{ 168 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); 169 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 170 if (reg->Register.Indirect) { 171 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle); 172 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->temps_array, &array_index, 173 1, ""); 174 return LLVMBuildLoad(builder, ptr, ""); 175 } else { 176 LLVMValueRef temp_ptr; 177 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle); 178 return bitcast(bld_base,type,LLVMBuildLoad(builder, temp_ptr, "")); 179 } 180} 181 182static LLVMValueRef 183emit_fetch_output( 184 struct lp_build_tgsi_context *bld_base, 185 const struct tgsi_full_src_register *reg, 186 enum tgsi_opcode_type type, 187 unsigned swizzle) 188{ 189 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); 190 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 191 if (reg->Register.Indirect) { 192 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle); 193 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->outputs_array, &array_index, 194 1, ""); 195 return LLVMBuildLoad(builder, ptr, ""); 196 } else { 197 LLVMValueRef temp_ptr; 198 temp_ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle); 199 return LLVMBuildLoad(builder, temp_ptr, ""); 200 } 201} 202 203static void emit_declaration( 204 struct lp_build_tgsi_context * bld_base, 205 const struct tgsi_full_declaration *decl) 206{ 207 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 208 switch(decl->Declaration.File) { 209 case TGSI_FILE_ADDRESS: 210 { 211 unsigned idx; 212 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { 213 unsigned chan; 214 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { 215 ctx->soa.addr[idx][chan] = lp_build_alloca( 216 &ctx->gallivm, 217 ctx->soa.bld_base.uint_bld.elem_type, ""); 218 } 219 } 220 break; 221 } 222 223 case TGSI_FILE_TEMPORARY: 224 lp_emit_declaration_soa(bld_base, decl); 225 break; 226 227 case TGSI_FILE_INPUT: 228 { 229 unsigned idx; 230 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { 231 ctx->load_input(ctx, idx, decl); 232 } 233 } 234 break; 235 236 case TGSI_FILE_SYSTEM_VALUE: 237 { 238 unsigned idx; 239 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { 240 ctx->load_system_value(ctx, idx, decl); 241 } 242 } 243 break; 244 245 case TGSI_FILE_OUTPUT: 246 { 247 unsigned idx; 248 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { 249 unsigned chan; 250 assert(idx < RADEON_LLVM_MAX_OUTPUTS); 251 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { 252 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm, 253 ctx->soa.bld_base.base.elem_type, ""); 254 } 255 } 256 257 ctx->output_reg_count = MAX2(ctx->output_reg_count, 258 decl->Range.Last + 1); 259 break; 260 } 261 262 default: 263 break; 264 } 265} 266 267static void 268emit_store( 269 struct lp_build_tgsi_context * bld_base, 270 const struct tgsi_full_instruction * inst, 271 const struct tgsi_opcode_info * info, 272 LLVMValueRef dst[4]) 273{ 274 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); 275 struct gallivm_state *gallivm = bld->bld_base.base.gallivm; 276 struct lp_build_context base = bld->bld_base.base; 277 const struct tgsi_full_dst_register *reg = &inst->Dst[0]; 278 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder; 279 LLVMValueRef temp_ptr; 280 unsigned chan, chan_index; 281 boolean is_vec_store = FALSE; 282 if (dst[0]) { 283 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0])); 284 is_vec_store = (k == LLVMVectorTypeKind); 285 } 286 287 if (is_vec_store) { 288 LLVMValueRef values[4] = {}; 289 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) { 290 LLVMValueRef index = lp_build_const_int32(gallivm, chan); 291 values[chan] = LLVMBuildExtractElement(gallivm->builder, 292 dst[0], index, ""); 293 } 294 bld_base->emit_store(bld_base, inst, info, values); 295 return; 296 } 297 298 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) { 299 LLVMValueRef value = dst[chan_index]; 300 301 if (inst->Instruction.Saturate != TGSI_SAT_NONE) { 302 struct lp_build_emit_data clamp_emit_data; 303 304 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data)); 305 clamp_emit_data.arg_count = 3; 306 clamp_emit_data.args[0] = value; 307 clamp_emit_data.args[2] = base.one; 308 309 switch(inst->Instruction.Saturate) { 310 case TGSI_SAT_ZERO_ONE: 311 clamp_emit_data.args[1] = base.zero; 312 break; 313 case TGSI_SAT_MINUS_PLUS_ONE: 314 clamp_emit_data.args[1] = LLVMConstReal( 315 base.elem_type, -1.0f); 316 break; 317 default: 318 assert(0); 319 } 320 value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP, 321 &clamp_emit_data); 322 } 323 324 switch(reg->Register.File) { 325 case TGSI_FILE_OUTPUT: 326 temp_ptr = bld->outputs[reg->Register.Index][chan_index]; 327 break; 328 329 case TGSI_FILE_TEMPORARY: 330 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index); 331 break; 332 333 default: 334 return; 335 } 336 337 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value); 338 339 LLVMBuildStore(builder, value, temp_ptr); 340 } 341} 342 343static void bgnloop_emit( 344 const struct lp_build_tgsi_action * action, 345 struct lp_build_tgsi_context * bld_base, 346 struct lp_build_emit_data * emit_data) 347{ 348 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 349 struct gallivm_state * gallivm = bld_base->base.gallivm; 350 LLVMBasicBlockRef loop_block; 351 LLVMBasicBlockRef endloop_block; 352 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context, 353 ctx->main_fn, "ENDLOOP"); 354 loop_block = LLVMInsertBasicBlockInContext(gallivm->context, 355 endloop_block, "LOOP"); 356 LLVMBuildBr(gallivm->builder, loop_block); 357 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block); 358 ctx->loop_depth++; 359 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block; 360 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block; 361} 362 363static void brk_emit( 364 const struct lp_build_tgsi_action * action, 365 struct lp_build_tgsi_context * bld_base, 366 struct lp_build_emit_data * emit_data) 367{ 368 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 369 struct gallivm_state * gallivm = bld_base->base.gallivm; 370 struct radeon_llvm_loop * current_loop = get_current_loop(ctx); 371 372 LLVMBuildBr(gallivm->builder, current_loop->endloop_block); 373} 374 375static void cont_emit( 376 const struct lp_build_tgsi_action * action, 377 struct lp_build_tgsi_context * bld_base, 378 struct lp_build_emit_data * emit_data) 379{ 380 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 381 struct gallivm_state * gallivm = bld_base->base.gallivm; 382 struct radeon_llvm_loop * current_loop = get_current_loop(ctx); 383 384 LLVMBuildBr(gallivm->builder, current_loop->loop_block); 385} 386 387static void else_emit( 388 const struct lp_build_tgsi_action * action, 389 struct lp_build_tgsi_context * bld_base, 390 struct lp_build_emit_data * emit_data) 391{ 392 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 393 struct gallivm_state * gallivm = bld_base->base.gallivm; 394 struct radeon_llvm_branch * current_branch = get_current_branch(ctx); 395 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder); 396 397 /* We need to add a terminator to the current block if the previous 398 * instruction was an ENDIF.Example: 399 * IF 400 * [code] 401 * IF 402 * [code] 403 * ELSE 404 * [code] 405 * ENDIF <-- 406 * ELSE<-- 407 * [code] 408 * ENDIF 409 */ 410 411 if (current_block != current_branch->if_block) { 412 LLVMBuildBr(gallivm->builder, current_branch->endif_block); 413 } 414 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) { 415 LLVMBuildBr(gallivm->builder, current_branch->endif_block); 416 } 417 current_branch->has_else = 1; 418 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block); 419} 420 421static void endif_emit( 422 const struct lp_build_tgsi_action * action, 423 struct lp_build_tgsi_context * bld_base, 424 struct lp_build_emit_data * emit_data) 425{ 426 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 427 struct gallivm_state * gallivm = bld_base->base.gallivm; 428 struct radeon_llvm_branch * current_branch = get_current_branch(ctx); 429 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder); 430 431 /* If we have consecutive ENDIF instructions, then the first ENDIF 432 * will not have a terminator, so we need to add one. */ 433 if (current_block != current_branch->if_block 434 && current_block != current_branch->else_block 435 && !LLVMGetBasicBlockTerminator(current_block)) { 436 437 LLVMBuildBr(gallivm->builder, current_branch->endif_block); 438 } 439 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) { 440 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block); 441 LLVMBuildBr(gallivm->builder, current_branch->endif_block); 442 } 443 444 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) { 445 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block); 446 LLVMBuildBr(gallivm->builder, current_branch->endif_block); 447 } 448 449 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block); 450 ctx->branch_depth--; 451} 452 453static void endloop_emit( 454 const struct lp_build_tgsi_action * action, 455 struct lp_build_tgsi_context * bld_base, 456 struct lp_build_emit_data * emit_data) 457{ 458 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 459 struct gallivm_state * gallivm = bld_base->base.gallivm; 460 struct radeon_llvm_loop * current_loop = get_current_loop(ctx); 461 462 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) { 463 LLVMBuildBr(gallivm->builder, current_loop->loop_block); 464 } 465 466 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block); 467 ctx->loop_depth--; 468} 469 470static void if_emit( 471 const struct lp_build_tgsi_action * action, 472 struct lp_build_tgsi_context * bld_base, 473 struct lp_build_emit_data * emit_data) 474{ 475 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 476 struct gallivm_state * gallivm = bld_base->base.gallivm; 477 LLVMValueRef cond; 478 LLVMBasicBlockRef if_block, else_block, endif_block; 479 480 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE, 481 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]), 482 bld_base->int_bld.zero, ""); 483 484 endif_block = LLVMAppendBasicBlockInContext(gallivm->context, 485 ctx->main_fn, "ENDIF"); 486 if_block = LLVMInsertBasicBlockInContext(gallivm->context, 487 endif_block, "IF"); 488 else_block = LLVMInsertBasicBlockInContext(gallivm->context, 489 endif_block, "ELSE"); 490 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block); 491 LLVMPositionBuilderAtEnd(gallivm->builder, if_block); 492 493 ctx->branch_depth++; 494 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block; 495 ctx->branch[ctx->branch_depth - 1].if_block = if_block; 496 ctx->branch[ctx->branch_depth - 1].else_block = else_block; 497 ctx->branch[ctx->branch_depth - 1].has_else = 0; 498} 499 500static void kil_emit( 501 const struct lp_build_tgsi_action * action, 502 struct lp_build_tgsi_context * bld_base, 503 struct lp_build_emit_data * emit_data) 504{ 505 unsigned i; 506 for (i = 0; i < emit_data->arg_count; i++) { 507 emit_data->output[i] = lp_build_intrinsic_unary( 508 bld_base->base.gallivm->builder, 509 action->intr_name, 510 emit_data->dst_type, emit_data->args[i]); 511 } 512} 513 514 515static void emit_prepare_cube_coords( 516 struct lp_build_tgsi_context * bld_base, 517 struct lp_build_emit_data * emit_data) 518{ 519 boolean shadowcube = (emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE); 520 struct gallivm_state * gallivm = bld_base->base.gallivm; 521 LLVMBuilderRef builder = gallivm->builder; 522 LLVMTypeRef type = bld_base->base.elem_type; 523 LLVMValueRef coords[4]; 524 LLVMValueRef mad_args[3]; 525 unsigned i, cnt; 526 527 LLVMValueRef v = build_intrinsic(builder, "llvm.AMDGPU.cube", 528 LLVMVectorType(type, 4), 529 &emit_data->args[0],1, LLVMReadNoneAttribute); 530 531 /* save src.w for shadow cube */ 532 cnt = shadowcube ? 3 : 4; 533 534 for (i = 0; i < cnt; ++i) { 535 LLVMValueRef idx = lp_build_const_int32(gallivm, i); 536 coords[i] = LLVMBuildExtractElement(builder, v, idx, ""); 537 } 538 539 coords[2] = build_intrinsic(builder, "llvm.AMDIL.fabs.", 540 type, &coords[2], 1, LLVMReadNoneAttribute); 541 coords[2] = build_intrinsic(builder, "llvm.AMDGPU.rcp", 542 type, &coords[2], 1, LLVMReadNoneAttribute); 543 544 mad_args[1] = coords[2]; 545 mad_args[2] = LLVMConstReal(type, 1.5); 546 547 mad_args[0] = coords[0]; 548 coords[0] = build_intrinsic(builder, "llvm.AMDIL.mad.", 549 type, mad_args, 3, LLVMReadNoneAttribute); 550 551 mad_args[0] = coords[1]; 552 coords[1] = build_intrinsic(builder, "llvm.AMDIL.mad.", 553 type, mad_args, 3, LLVMReadNoneAttribute); 554 555 /* apply yxwy swizzle to cooords */ 556 coords[2] = coords[3]; 557 coords[3] = coords[1]; 558 coords[1] = coords[0]; 559 coords[0] = coords[3]; 560 561 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm, 562 coords, 4); 563} 564 565static void txp_fetch_args( 566 struct lp_build_tgsi_context * bld_base, 567 struct lp_build_emit_data * emit_data) 568{ 569 const struct tgsi_full_instruction * inst = emit_data->inst; 570 LLVMValueRef src_w; 571 unsigned chan; 572 LLVMValueRef coords[4]; 573 574 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); 575 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W); 576 577 for (chan = 0; chan < 3; chan++ ) { 578 LLVMValueRef arg = lp_build_emit_fetch(bld_base, 579 emit_data->inst, 0, chan); 580 coords[chan] = lp_build_emit_llvm_binary(bld_base, 581 TGSI_OPCODE_DIV, arg, src_w); 582 } 583 coords[3] = bld_base->base.one; 584 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm, 585 coords, 4); 586 emit_data->arg_count = 1; 587 588 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE || 589 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) && 590 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) { 591 emit_prepare_cube_coords(bld_base, emit_data); 592 } 593} 594 595static void tex_fetch_args( 596 struct lp_build_tgsi_context * bld_base, 597 struct lp_build_emit_data * emit_data) 598{ 599 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types, 600 * when we used CHAN_ALL. We should be able to get this to work, 601 * but for now we will swizzle it ourselves 602 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst, 603 0, CHAN_ALL); 604 605 */ 606 607 const struct tgsi_full_instruction * inst = emit_data->inst; 608 609 LLVMValueRef coords[4]; 610 unsigned chan; 611 for (chan = 0; chan < 4; chan++) { 612 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan); 613 } 614 615 emit_data->arg_count = 1; 616 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm, 617 coords, 4); 618 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); 619 620 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE || 621 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) && 622 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) { 623 emit_prepare_cube_coords(bld_base, emit_data); 624 } 625} 626 627static void emit_icmp( 628 const struct lp_build_tgsi_action * action, 629 struct lp_build_tgsi_context * bld_base, 630 struct lp_build_emit_data * emit_data) 631{ 632 unsigned pred; 633 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 634 LLVMContextRef context = bld_base->base.gallivm->context; 635 636 switch (emit_data->inst->Instruction.Opcode) { 637 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break; 638 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break; 639 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break; 640 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break; 641 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break; 642 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break; 643 default: 644 assert(!"unknown instruction"); 645 } 646 647 LLVMValueRef v = LLVMBuildICmp(builder, pred, 648 emit_data->args[0], emit_data->args[1],""); 649 650 v = LLVMBuildSExtOrBitCast(builder, v, 651 LLVMInt32TypeInContext(context), ""); 652 653 emit_data->output[emit_data->chan] = v; 654} 655 656static void emit_not( 657 const struct lp_build_tgsi_action * action, 658 struct lp_build_tgsi_context * bld_base, 659 struct lp_build_emit_data * emit_data) 660{ 661 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 662 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED, 663 emit_data->args[0]); 664 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, ""); 665} 666 667static void emit_and( 668 const struct lp_build_tgsi_action * action, 669 struct lp_build_tgsi_context * bld_base, 670 struct lp_build_emit_data * emit_data) 671{ 672 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 673 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder, 674 emit_data->args[0], emit_data->args[1], ""); 675} 676 677static void emit_or( 678 const struct lp_build_tgsi_action * action, 679 struct lp_build_tgsi_context * bld_base, 680 struct lp_build_emit_data * emit_data) 681{ 682 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 683 emit_data->output[emit_data->chan] = LLVMBuildOr(builder, 684 emit_data->args[0], emit_data->args[1], ""); 685} 686 687static void emit_uadd( 688 const struct lp_build_tgsi_action * action, 689 struct lp_build_tgsi_context * bld_base, 690 struct lp_build_emit_data * emit_data) 691{ 692 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 693 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder, 694 emit_data->args[0], emit_data->args[1], ""); 695} 696 697static void emit_udiv( 698 const struct lp_build_tgsi_action * action, 699 struct lp_build_tgsi_context * bld_base, 700 struct lp_build_emit_data * emit_data) 701{ 702 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 703 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder, 704 emit_data->args[0], emit_data->args[1], ""); 705} 706 707static void emit_idiv( 708 const struct lp_build_tgsi_action * action, 709 struct lp_build_tgsi_context * bld_base, 710 struct lp_build_emit_data * emit_data) 711{ 712 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 713 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder, 714 emit_data->args[0], emit_data->args[1], ""); 715} 716 717static void emit_mod( 718 const struct lp_build_tgsi_action * action, 719 struct lp_build_tgsi_context * bld_base, 720 struct lp_build_emit_data * emit_data) 721{ 722 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 723 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder, 724 emit_data->args[0], emit_data->args[1], ""); 725} 726 727static void emit_umod( 728 const struct lp_build_tgsi_action * action, 729 struct lp_build_tgsi_context * bld_base, 730 struct lp_build_emit_data * emit_data) 731{ 732 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 733 emit_data->output[emit_data->chan] = LLVMBuildURem(builder, 734 emit_data->args[0], emit_data->args[1], ""); 735} 736 737static void emit_shl( 738 const struct lp_build_tgsi_action * action, 739 struct lp_build_tgsi_context * bld_base, 740 struct lp_build_emit_data * emit_data) 741{ 742 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 743 emit_data->output[emit_data->chan] = LLVMBuildShl(builder, 744 emit_data->args[0], emit_data->args[1], ""); 745} 746 747static void emit_ushr( 748 const struct lp_build_tgsi_action * action, 749 struct lp_build_tgsi_context * bld_base, 750 struct lp_build_emit_data * emit_data) 751{ 752 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 753 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder, 754 emit_data->args[0], emit_data->args[1], ""); 755} 756static void emit_ishr( 757 const struct lp_build_tgsi_action * action, 758 struct lp_build_tgsi_context * bld_base, 759 struct lp_build_emit_data * emit_data) 760{ 761 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 762 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder, 763 emit_data->args[0], emit_data->args[1], ""); 764} 765 766static void emit_xor( 767 const struct lp_build_tgsi_action * action, 768 struct lp_build_tgsi_context * bld_base, 769 struct lp_build_emit_data * emit_data) 770{ 771 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 772 emit_data->output[emit_data->chan] = LLVMBuildXor(builder, 773 emit_data->args[0], emit_data->args[1], ""); 774} 775 776static void emit_ssg( 777 const struct lp_build_tgsi_action * action, 778 struct lp_build_tgsi_context * bld_base, 779 struct lp_build_emit_data * emit_data) 780{ 781 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 782 783 LLVMValueRef cmp, val; 784 785 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) { 786 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, ""); 787 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], ""); 788 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, ""); 789 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), ""); 790 } else { // float SSG 791 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->int_bld.zero, ""); 792 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], ""); 793 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, ""); 794 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), ""); 795 } 796 797 emit_data->output[emit_data->chan] = val; 798} 799 800static void emit_ineg( 801 const struct lp_build_tgsi_action * action, 802 struct lp_build_tgsi_context * bld_base, 803 struct lp_build_emit_data * emit_data) 804{ 805 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 806 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder, 807 emit_data->args[0], ""); 808} 809 810static void emit_f2i( 811 const struct lp_build_tgsi_action * action, 812 struct lp_build_tgsi_context * bld_base, 813 struct lp_build_emit_data * emit_data) 814{ 815 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 816 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder, 817 emit_data->args[0], bld_base->int_bld.elem_type, ""); 818} 819 820static void emit_f2u( 821 const struct lp_build_tgsi_action * action, 822 struct lp_build_tgsi_context * bld_base, 823 struct lp_build_emit_data * emit_data) 824{ 825 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 826 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder, 827 emit_data->args[0], bld_base->uint_bld.elem_type, ""); 828} 829 830static void emit_i2f( 831 const struct lp_build_tgsi_action * action, 832 struct lp_build_tgsi_context * bld_base, 833 struct lp_build_emit_data * emit_data) 834{ 835 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 836 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder, 837 emit_data->args[0], bld_base->base.elem_type, ""); 838} 839 840static void emit_u2f( 841 const struct lp_build_tgsi_action * action, 842 struct lp_build_tgsi_context * bld_base, 843 struct lp_build_emit_data * emit_data) 844{ 845 LLVMBuilderRef builder = bld_base->base.gallivm->builder; 846 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder, 847 emit_data->args[0], bld_base->base.elem_type, ""); 848} 849 850static void emit_immediate(struct lp_build_tgsi_context * bld_base, 851 const struct tgsi_full_immediate *imm) 852{ 853 unsigned i; 854 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); 855 856 for (i = 0; i < 4; ++i) { 857 ctx->soa.immediates[ctx->soa.num_immediates][i] = 858 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false ); 859 } 860 861 ctx->soa.num_immediates++; 862} 863 864LLVMValueRef 865build_intrinsic(LLVMBuilderRef builder, 866 const char *name, 867 LLVMTypeRef ret_type, 868 LLVMValueRef *args, 869 unsigned num_args, 870 LLVMAttribute attr) 871{ 872 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder))); 873 LLVMValueRef function; 874 875 function = LLVMGetNamedFunction(module, name); 876 if(!function) { 877 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS]; 878 unsigned i; 879 880 assert(num_args <= LP_MAX_FUNC_ARGS); 881 882 for(i = 0; i < num_args; ++i) { 883 assert(args[i]); 884 arg_types[i] = LLVMTypeOf(args[i]); 885 } 886 887 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args); 888 889 if (attr) 890 LLVMAddFunctionAttr(function, attr); 891 } 892 893 return LLVMBuildCall(builder, function, args, num_args, ""); 894} 895 896void 897build_tgsi_intrinsic_nomem( 898 const struct lp_build_tgsi_action * action, 899 struct lp_build_tgsi_context * bld_base, 900 struct lp_build_emit_data * emit_data) 901{ 902 struct lp_build_context * base = &bld_base->base; 903 emit_data->output[emit_data->chan] = build_intrinsic( 904 base->gallivm->builder, action->intr_name, 905 emit_data->dst_type, emit_data->args, 906 emit_data->arg_count, LLVMReadNoneAttribute); 907} 908 909void radeon_llvm_context_init(struct radeon_llvm_context * ctx) 910{ 911 struct lp_type type; 912 LLVMTypeRef main_fn_type; 913 LLVMBasicBlockRef main_fn_body; 914 915 /* Initialize the gallivm object: 916 * We are only using the module, context, and builder fields of this struct. 917 * This should be enough for us to be able to pass our gallivm struct to the 918 * helper functions in the gallivm module. 919 */ 920 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm)); 921 memset(&ctx->soa, 0, sizeof(ctx->soa)); 922 ctx->gallivm.context = LLVMContextCreate(); 923 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi", 924 ctx->gallivm.context); 925 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context); 926 927 /* Setup the module */ 928 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context), 929 NULL, 0, 0); 930 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type); 931 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context, 932 ctx->main_fn, "main_body"); 933 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body); 934 935 ctx->store_output_intr = "llvm.AMDGPU.store.output."; 936 ctx->swizzle_intr = "llvm.AMDGPU.swizzle"; 937 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base; 938 939 /* XXX: We need to revisit this.I think the correct way to do this is 940 * to use length = 4 here and use the elem_bld for everything. */ 941 type.floating = TRUE; 942 type.sign = TRUE; 943 type.width = 32; 944 type.length = 1; 945 946 lp_build_context_init(&bld_base->base, &ctx->gallivm, type); 947 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type)); 948 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type)); 949 950 bld_base->soa = 1; 951 bld_base->emit_store = emit_store; 952 bld_base->emit_swizzle = emit_swizzle; 953 bld_base->emit_declaration = emit_declaration; 954 bld_base->emit_immediate = emit_immediate; 955 956 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch_immediate; 957 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch_input; 958 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch_temporary; 959 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch_output; 960 961 /* Allocate outputs */ 962 ctx->soa.outputs = ctx->outputs; 963 964 /* XXX: Is there a better way to initialize all this ? */ 965 966 lp_set_default_actions(bld_base); 967 968 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem; 969 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs."; 970 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not; 971 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and; 972 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor; 973 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or; 974 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd; 975 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv; 976 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv; 977 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod; 978 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod; 979 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg; 980 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl; 981 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr; 982 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr; 983 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg; 984 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg; 985 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f; 986 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f; 987 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i; 988 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u; 989 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx"; 990 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args; 991 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy"; 992 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args; 993 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp; 994 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp; 995 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp; 996 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp; 997 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp; 998 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp; 999 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem; 1000 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest."; 1001 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem; 1002 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min."; 1003 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem; 1004 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max."; 1005 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem; 1006 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin"; 1007 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem; 1008 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax"; 1009 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem; 1010 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin"; 1011 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem; 1012 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax"; 1013 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = tex_fetch_args; 1014 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf"; 1015 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args; 1016 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq"; 1017 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem; 1018 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.AMDIL.round.posinf."; 1019 1020 1021 1022 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem; 1023 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "llvm.AMDIL.fabs."; 1024 bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem; 1025 bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl"; 1026 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit; 1027 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit; 1028 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit; 1029 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem; 1030 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp."; 1031 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem; 1032 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt"; 1033 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem; 1034 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.AMDGPU.cos"; 1035 bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem; 1036 bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div"; 1037 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit; 1038 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit; 1039 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit; 1040 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem; 1041 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp."; 1042 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem; 1043 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.AMDGPU.floor"; 1044 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem; 1045 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction."; 1046 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit; 1047 bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit; 1048 bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill"; 1049 bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic; 1050 bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp"; 1051 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem; 1052 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.AMDIL.log."; 1053 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem; 1054 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp"; 1055 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem; 1056 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min."; 1057 bld_base->op_actions[TGSI_OPCODE_MAD].emit = build_tgsi_intrinsic_nomem; 1058 bld_base->op_actions[TGSI_OPCODE_MAD].intr_name = "llvm.AMDIL.mad."; 1059 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem; 1060 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max."; 1061 bld_base->op_actions[TGSI_OPCODE_MUL].emit = build_tgsi_intrinsic_nomem; 1062 bld_base->op_actions[TGSI_OPCODE_MUL].intr_name = "llvm.AMDGPU.mul"; 1063 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem; 1064 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.AMDGPU.pow"; 1065 bld_base->op_actions[TGSI_OPCODE_RCP].emit = build_tgsi_intrinsic_nomem; 1066 bld_base->op_actions[TGSI_OPCODE_RCP].intr_name = "llvm.AMDGPU.rcp"; 1067 bld_base->op_actions[TGSI_OPCODE_SSG].emit = build_tgsi_intrinsic_nomem; 1068 bld_base->op_actions[TGSI_OPCODE_SSG].intr_name = "llvm.AMDGPU.ssg"; 1069 bld_base->op_actions[TGSI_OPCODE_SGE].emit = build_tgsi_intrinsic_nomem; 1070 bld_base->op_actions[TGSI_OPCODE_SGE].intr_name = "llvm.AMDGPU.sge"; 1071 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = build_tgsi_intrinsic_nomem; 1072 bld_base->op_actions[TGSI_OPCODE_SEQ].intr_name = "llvm.AMDGPU.seq"; 1073 bld_base->op_actions[TGSI_OPCODE_SLE].fetch_args = radeon_llvm_fetch_args_2_reverse_soa; 1074 bld_base->op_actions[TGSI_OPCODE_SLE].emit = build_tgsi_intrinsic_nomem; 1075 bld_base->op_actions[TGSI_OPCODE_SLE].intr_name = "llvm.AMDGPU.sge"; 1076 bld_base->op_actions[TGSI_OPCODE_SLT].fetch_args = radeon_llvm_fetch_args_2_reverse_soa; 1077 bld_base->op_actions[TGSI_OPCODE_SLT].emit = build_tgsi_intrinsic_nomem; 1078 bld_base->op_actions[TGSI_OPCODE_SLT].intr_name = "llvm.AMDGPU.sgt"; 1079 bld_base->op_actions[TGSI_OPCODE_SNE].emit = build_tgsi_intrinsic_nomem; 1080 bld_base->op_actions[TGSI_OPCODE_SNE].intr_name = "llvm.AMDGPU.sne"; 1081 bld_base->op_actions[TGSI_OPCODE_SGT].emit = build_tgsi_intrinsic_nomem; 1082 bld_base->op_actions[TGSI_OPCODE_SGT].intr_name = "llvm.AMDGPU.sgt"; 1083 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem; 1084 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.AMDGPU.sin"; 1085 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args; 1086 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex"; 1087 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args; 1088 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb"; 1089 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = tex_fetch_args; 1090 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd"; 1091 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args; 1092 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl"; 1093 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args; 1094 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex"; 1095 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem; 1096 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc"; 1097 1098 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem; 1099 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq"; 1100} 1101 1102void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx) 1103{ 1104 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm; 1105 /* End the main function with Return*/ 1106 LLVMBuildRetVoid(gallivm->builder); 1107 1108 /* Create the pass manager */ 1109 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule( 1110 gallivm->module); 1111 1112 /* This pass should eliminate all the load and store instructions */ 1113 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr); 1114 1115 /* Add some optimization passes */ 1116 LLVMAddScalarReplAggregatesPass(gallivm->passmgr); 1117 LLVMAddCFGSimplificationPass(gallivm->passmgr); 1118 1119 /* Run the passs */ 1120 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn); 1121 1122 LLVMDisposeBuilder(gallivm->builder); 1123 LLVMDisposePassManager(gallivm->passmgr); 1124 1125} 1126 1127void radeon_llvm_dispose(struct radeon_llvm_context * ctx) 1128{ 1129 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module); 1130 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context); 1131} 1132