1bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl/* 2adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellCopyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 4adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThe Weather Channel (TM) funded Tungsten Graphics to develop the 5adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellinitial release of the Radeon 8500 driver under the XFree86 license. 6adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThis notice must be preserved. 7adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 8adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellPermission is hereby granted, free of charge, to any person obtaining 9adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwella copy of this software and associated documentation files (the 10adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell"Software"), to deal in the Software without restriction, including 11adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellwithout limitation the rights to use, copy, modify, merge, publish, 12adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelldistribute, sublicense, and/or sell copies of the Software, and to 13adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellpermit persons to whom the Software is furnished to do so, subject to 14adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellthe following conditions: 15adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 16adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThe above copyright notice and this permission notice (including the 17adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellnext paragraph) shall be included in all copies or substantial 18adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellportions of the Software. 19adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 20adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 28adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell**************************************************************************/ 29adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 30adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* 31adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Authors: 32adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Keith Whitwell <keith@tungstengraphics.com> 33adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 34adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 35adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#ifndef __R200_CONTEXT_H__ 36adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define __R200_CONTEXT_H__ 37adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 38e946688edac5cdf153652defae3ef732a3487416Ian Romanick#include "tnl/t_vertex.h" 39ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl#include "drm.h" 40ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl#include "radeon_drm.h" 41adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "dri_util.h" 42adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 43ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/macros.h" 44ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/mtypes.h" 45ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/colormac.h" 46adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "r200_reg.h" 4798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#include "r200_vertprog.h" 48adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 49bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#ifndef R200_EMIT_VAP_PVS_CNTL 50bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#error This driver requires a newer libdrm to compile 51bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#endif 52bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger 534637235183b80963536f2364e4d50fcb894886ddDave Airlie#include "radeon_screen.h" 548cb16e6daff40bbfd7b63a43da72862226a4a164Dave Airlie#include "radeon_common.h" 558cb16e6daff40bbfd7b63a43da72862226a4a164Dave Airlie 56adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_context; 57adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef struct r200_context r200ContextRec; 58adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef struct r200_context *r200ContextPtr; 59adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 604637235183b80963536f2364e4d50fcb894886ddDave Airlie#include "main/mm.h" 61adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 6298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheideggerstruct r200_vertex_program { 63122629f27925a9dc50029bebc5079f87f416a7e1Brian Paul struct gl_vertex_program mesa_program; /* Must be first */ 6498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int translated; 65fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger /* need excess instr: 1 for late loop checking, 2 for 66fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger additional instr due to instr/attr, 3 for fog */ 67fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; 6898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int pos_end; 6998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int inputs[VERT_ATTRIB_MAX]; 70421ce180f52ff55b866066fabd861a51dd6d2b26Roland Scheidegger GLubyte inputmap_rev[16]; 7198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int native; 72fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger int fogpidx; 73fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger int fogmode; 7498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger}; 7598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 76692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_TEX_ALL 0x3f 77adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 78adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 79adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_texture_env_state { 80692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonTexObjPtr texobj; 8136603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint outputreg; 8236603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint unitneeded; 83adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 84adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 8548ccaf200940613032dfaaafe71382947f398004Roland Scheidegger#define R200_MAX_TEXTURE_UNITS 6 86adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 87adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_texture_state { 88adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; 89adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 90adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 91adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 92adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Trying to keep these relatively short as the variables are becoming 93adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * extravagently long. Drop the driver name prefix off the front of 94adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * everything - I think we know which driver we're in by now, and keep the 95adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * prefix to 3 letters unless absolutely impossible. 96adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 97adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 98adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_0 0 99adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_MISC 1 100adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_FOG_COLOR 2 101adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RE_SOLID_COLOR 3 102adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_BLENDCNTL 4 103adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_DEPTHOFFSET 5 104adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_DEPTHPITCH 6 105adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_ZSTENCILCNTL 7 106adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_1 8 107adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_CNTL 9 108adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_CNTL 10 109adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_COLOROFFSET 11 110adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_2 12 /* why */ 111adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_COLORPITCH 13 /* why */ 112033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_STATE_SIZE_OLDDRM 14 113033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_CMD_3 14 114033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_BLENDCOLOR 15 115033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_ABLENDCNTL 16 116033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_CBLENDCNTL 17 117033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_STATE_SIZE_NEWDRM 18 118adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 119adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_CMD_0 0 120adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_SE_CNTL 1 121adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_RE_CNTL 2 /* replace se_coord_fmt */ 122adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_STATE_SIZE 3 123adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 124adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_CMD_0 0 125adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_SE_VTE_CNTL 1 126adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_STATE_SIZE 2 127adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 128adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_CMD_0 0 129adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_RE_LINE_PATTERN 1 130adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_RE_LINE_STATE 2 131adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_CMD_1 3 132adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_SE_LINE_WIDTH 4 133adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_STATE_SIZE 5 134adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 135adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_CMD_0 0 136adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_STENCILREFMASK 1 137adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_ROPCNTL 2 138adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_PLANEMASK 3 139adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_STATE_SIZE 4 140adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 141adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_CMD_0 0 142adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_XSCALE 1 143adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_XOFFSET 2 144adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_YSCALE 3 145adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_YOFFSET 4 146adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_ZSCALE 5 147adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_ZOFFSET 6 148adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_STATE_SIZE 7 149adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 150adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_CMD_0 0 151adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_SE_ZBIAS_FACTOR 1 152adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_SE_ZBIAS_CONSTANT 2 153adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_STATE_SIZE 3 154adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 155adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_CMD_0 0 156adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_RE_MISC 1 157adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_STATE_SIZE 2 158adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 159adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_CMD_0 0 160adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_DEBUG3 1 161adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_STATE_SIZE 2 162adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 163adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_CMD_0 0 164adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFILTER 1 /*2c00*/ 165adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFORMAT 2 /*2c04*/ 166adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFORMAT_X 3 /*2c08*/ 167adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXSIZE 4 /*2c0c*/ 168adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXPITCH 5 /*2c10*/ 169adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_BORDER_COLOR 6 /*2c14*/ 170f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_CMD_1_OLDDRM 7 171f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ 172f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_STATE_SIZE_OLDDRM 9 173f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_CUBIC_FACES 7 174f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXMULTI_CTL 8 175f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_CMD_1_NEWDRM 9 176f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXOFFSET_NEWDRM 10 177f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_STATE_SIZE_NEWDRM 11 178f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 179f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ 180f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ 181adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_CMD_1 2 /* 5 registers follow */ 182adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ 183adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ 184adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ 185adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ 186adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ 187adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_STATE_SIZE 8 188adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 189adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_CMD_0 0 190adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXCBLEND 1 191adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXCBLEND2 2 192adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXABLEND 3 193adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXABLEND2 4 194adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_STATE_SIZE 5 195adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 196adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_CMD_0 0 197adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_0 1 198adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_1 2 199adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_2 3 200adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_3 4 201adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_4 5 202adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_5 6 203adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_STATE_SIZE 7 204adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 205f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_CMD_0 0 206f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_0 1 207f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_1 2 208f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_2 3 209f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_3 4 210f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_4 5 211f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_5 6 212f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_6 7 213f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_7 8 214f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_STATE_SIZE 9 215f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 216f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger/* ATI_FRAGMENT_SHADER */ 217f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_CMD_0 0 218f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IC0 1 /* 2f00 */ 219f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IC1 2 /* 2f04 */ 220f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IA0 3 /* 2f08 */ 221f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IA1 4 /* 2f0c */ 222f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_STATE_SIZE 33 223f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 22498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CMD_0 0 22598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CNTL_1 1 22698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CNTL_2 2 22798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_STATE_SIZE 3 22898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 22998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger/* those are quite big... */ 23098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_CMD_0 0 23198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_OPDST_0 1 23298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC0_0 2 23398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC1_0 3 23498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC2_0 4 23598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_OPDST_63 253 23698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC0_63 254 23798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC1_63 255 23898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC2_63 256 23998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_STATE_SIZE 257 24098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 24198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_CMD_0 0 24298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM0_0 1 24398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM1_0 2 24498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM2_0 3 24598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM3_0 4 24698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM0_95 381 24798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM1_95 382 24898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM2_95 383 24998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM3_95 384 25098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_STATE_SIZE 385 25198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 252adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_CMD_0 0 253adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_LIGHT_MODEL_CTL_0 1 254adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_LIGHT_MODEL_CTL_1 2 255adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_0 3 256adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_1 4 257adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_2 5 258adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_3 6 259adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_CMD_1 7 260adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_UCP_VERT_BLEND_CTL 8 261adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_STATE_SIZE 9 262adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 263adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_CMD_0 0 264adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_0 1 265adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_1 2 266adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_2 3 267adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_3 4 268adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_4 5 269adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_STATE_SIZE 6 270adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 271adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_CMD_0 0 272adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_2 1 273adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_3 2 274adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_0 3 275adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_1 4 276adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_CYL_WRAP_CTL 5 277adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_STATE_SIZE 6 278adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 279adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_CMD_0 0 280adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_RED 1 281adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_GREEN 2 282adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_BLUE 3 283adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_ALPHA 4 284adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_RED 5 285adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_GREEN 6 286adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_BLUE 7 287adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_ALPHA 8 288adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_RED 9 289adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_GREEN 10 290adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_BLUE 11 291adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_ALPHA 12 292adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_RED 13 293adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_GREEN 14 294adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_BLUE 15 295adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_ALPHA 16 296adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_CMD_1 17 297adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SHININESS 18 298adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_STATE_SIZE 19 299adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 300adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_CMD_0 0 301adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_SE_VAP_CNTL 1 302adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_STATE_SIZE 2 303adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 304adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Replaces a lot of packet info from radeon 305adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 306adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_0 0 307adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_VTXFMT_0 1 308adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_VTXFMT_1 2 309adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_VTXFMT_0 3 310adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_VTXFMT_1 4 311adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_1 5 312adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_COMPSEL 6 313adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_2 7 314adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_STATE_CNTL 8 315adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_STATE_SIZE 9 316adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 31744dace86eaf9eded8e6465adfadf6345658686ddRoland Scheidegger/* SPR - point sprite state 31844dace86eaf9eded8e6465adfadf6345658686ddRoland Scheidegger */ 319cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_CMD_0 0 320cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_POINT_SPRITE_CNTL 1 321cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_STATE_SIZE 2 322cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger 323cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CMD_0 0 324cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_0 1 325cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_1 2 326cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_PTSIZE 3 327cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_3 4 328cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CMD_1 5 329cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_QUAD 6 330cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_LIN 7 331cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_CON 8 332cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_3 9 333cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_X 10 334cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_Y 11 335cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_Z 12 336cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_3 13 337cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_MIN 14 338cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_MAX 15 339cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_2 16 340cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_3 17 341cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_STATE_SIZE 18 342adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 343adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ 344adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell R200_VTX_COLOR_MASK) 345adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 34695a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick/** 34795a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine 34895a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick * how many components are in texture coordinate \c n. 34995a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick */ 35095a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) 35195a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick 352adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_CMD_0 0 353adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_ELT_0 1 354adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_STATE_SIZE 17 355adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 356adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_CMD_0 0 357adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_VERT_GUARD_CLIP_ADJ 1 358adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_VERT_GUARD_DISCARD_ADJ 2 359adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_HORZ_GUARD_CLIP_ADJ 3 360adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_HORZ_GUARD_DISCARD_ADJ 4 361adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_STATE_SIZE 5 362adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 363adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* position changes frequently when lighting in modelpos - separate 364adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * out to new state item? 365adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 366adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_CMD_0 0 367adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_RED 1 368adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_GREEN 2 369adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_BLUE 3 370adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_ALPHA 4 371adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_RED 5 372adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_GREEN 6 373adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_BLUE 7 374adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_ALPHA 8 375adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_RED 9 376adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_GREEN 10 377adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_BLUE 11 378adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_ALPHA 12 379adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_X 13 380adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_Y 14 381adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_Z 15 382adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_W 16 383adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_X 17 384adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_Y 18 385adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_Z 19 386adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_W 20 3875d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_QUADRATIC 21 388adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_ATTEN_LINEAR 22 3895d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_CONST 23 390adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_ATTEN_XXX 24 391adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_CMD_1 25 392adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_DCD 26 393adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_DCM 27 394adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_EXPONENT 28 395adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_CUTOFF 29 396adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_THRESH 30 397adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_RANGE_CUTOFF 31 /* ? */ 3985d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_CONST_INV 32 399adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_STATE_SIZE 33 400adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 401adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Fog 402adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 403adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_CMD_0 0 404adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_R 1 405adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_C 2 406adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_D 3 407adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_PAD 4 408adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_STATE_SIZE 5 409adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 410adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* UCP 411adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 412adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_CMD_0 0 413adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_X 1 414adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_Y 2 415adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_Z 3 416adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_W 4 417adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_STATE_SIZE 5 418adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 419adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* GLT - Global ambient 420adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 421adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_CMD_0 0 422adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_RED 1 423adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_GREEN 2 424adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_BLUE 3 425adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_ALPHA 4 426adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_STATE_SIZE 5 427adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 428adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* EYE 429adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 430adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_CMD_0 0 431adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_X 1 432adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_Y 2 433adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_Z 3 434adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_RESCALE_FACTOR 4 435adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_STATE_SIZE 5 436adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 437adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* CST - constant state 438adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 439adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_0 0 440adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_PP_CNTL_X 1 441adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_1 2 442adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RB3D_DEPTHXY_OFFSET 3 443adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_2 4 444adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_AUX_SCISSOR_CNTL 5 445be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_CMD_4 6 446be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_SE_VAP_CNTL_STATUS 7 447be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_CMD_5 8 448be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_RE_POINTSIZE 9 449be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_CMD_6 10 450be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_SE_TCL_INPUT_VTX_0 11 451be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_SE_TCL_INPUT_VTX_1 12 452be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_SE_TCL_INPUT_VTX_2 13 453be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_SE_TCL_INPUT_VTX_3 14 454be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define CST_STATE_SIZE 15 455adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 456fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_CMD_0 0 457fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_PP_TRI_PERF 1 458fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_PP_PERF_CNTL 2 459fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_STATE_SIZE 3 460adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 461adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 462be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define SCI_CMD_1 0 463be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define SCI_XY_1 1 464be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define SCI_CMD_2 2 465be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define SCI_XY_2 3 466be2dcc5e9f61d380aec93eeb01227cbb6b5037c1Roland Scheidegger#define SCI_STATE_SIZE 4 467dbf59de6d2f8be526e97af6c768622e6ca3cf6b1Pauli Nieminen 468b6df23d8b3e70d86433ba9fc4d87338e1063fe39Dave Airlie#define R200_QUERYOBJ_CMD_0 0 469b6df23d8b3e70d86433ba9fc4d87338e1063fe39Dave Airlie#define R200_QUERYOBJ_DATA_0 1 470b6df23d8b3e70d86433ba9fc4d87338e1063fe39Dave Airlie#define R200_QUERYOBJ_CMDSIZE 2 471dbf59de6d2f8be526e97af6c768622e6ca3cf6b1Pauli Nieminen 4727d361537661b93a501c9533271458a41b965ea79Dave Airlie#define STP_CMD_0 0 4737d361537661b93a501c9533271458a41b965ea79Dave Airlie#define STP_DATA_0 1 4747d361537661b93a501c9533271458a41b965ea79Dave Airlie#define STP_CMD_1 2 4757d361537661b93a501c9533271458a41b965ea79Dave Airlie#define STP_STATE_SIZE 35 4767d361537661b93a501c9533271458a41b965ea79Dave Airlie 477adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_hw_state { 478adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Hardware state, stored as cmdbuf commands: 479adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * -- Need to doublebuffer for 480adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * - reviving state after loss of context 481adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * - eliding noop statechange loops? (except line stipple count) 482adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 483b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ctx; 484b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom set; 485dbf59de6d2f8be526e97af6c768622e6ca3cf6b1Pauli Nieminen struct radeon_state_atom sci; 486b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vte; 487b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom lin; 488b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msk; 489b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpt; 490b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vap; 491b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vtx; 492b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tcl; 493b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msl; 494b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tcg; 495b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msc; 496b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom cst; 497b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tam; 498b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tf; 499b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tex[6]; 500b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom cube[6]; 501b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom zbs; 502b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom mtl[2]; 503b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom mat[9]; 504b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 505b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ucp[6]; 506b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom pix[6]; /* pixshader stages */ 507b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom eye; /* eye pos */ 508b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom grd; /* guard band clipping */ 509b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom fog; 510b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom glt; 511b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom prf; 512b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom afs[2]; 513b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom pvs; 514b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpi[2]; 515b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpp[2]; 516b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom atf; 517b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom spr; 518b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ptp; 5197d361537661b93a501c9533271458a41b965ea79Dave Airlie struct radeon_state_atom stp; 520adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 521adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 522adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_state { 523adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Derived state for internal purposes: 524adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 525adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_texture_state texture; 52636603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint envneeded; 527adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 528adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5298a6182105772280e2727de4a00809c8fb7b13c87Roland Scheidegger#define R200_CMD_BUF_SZ (16*1024) 530adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5317d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie#define R200_ELT_BUF_SZ (16*1024) 532adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* r200_tcl.c 533adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 534adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_tcl_info { 535adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint hw_primitive; 536adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5377d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie int elt_used; 5387d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie 539adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 540adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 541adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 542adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* r200_swtcl.c 543adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 544adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_swtcl_info { 545e946688edac5cdf153652defae3ef732a3487416Ian Romanick 546adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5474637235183b80963536f2364e4d50fcb894886ddDave Airlie radeon_point_func draw_point; 5484637235183b80963536f2364e4d50fcb894886ddDave Airlie radeon_line_func draw_line; 5494637235183b80963536f2364e4d50fcb894886ddDave Airlie radeon_tri_func draw_tri; 550adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 551e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 552e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Offset of the 4UB color data within a hardware (swtcl) vertex. 553e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 554e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLuint coloroffset; 555e946688edac5cdf153652defae3ef732a3487416Ian Romanick 556e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 557e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 558e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 559e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLuint specoffset; 560e946688edac5cdf153652defae3ef732a3487416Ian Romanick 561e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 562e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Should Mesa project vertex data or will the hardware do it? 563e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 564e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLboolean needproj; 565adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 566adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 567adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 568adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 569adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 57048ccaf200940613032dfaaafe71382947f398004Roland Scheidegger /* A maximum total of 29 elements per vertex: 3 floats for position, 3 571adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * floats for normal, 4 floats for color, 4 bytes for secondary color, 57248ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * 3 floats for each texture unit (18 floats total). 573adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * 57448ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * we maybe need add. 4 to prevent segfault if someone specifies 57548ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) 576adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * 577adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * The position data is never actually stored here, so 3 elements could be 578adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * trimmed out of the buffer. 579adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 58048ccaf200940613032dfaaafe71382947f398004Roland Scheidegger 58148ccaf200940613032dfaaafe71382947f398004Roland Scheidegger#define R200_MAX_VERTEX_SIZE ((3*6)+11) 58248ccaf200940613032dfaaafe71382947f398004Roland Scheidegger 583adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_context { 5844637235183b80963536f2364e4d50fcb894886ddDave Airlie struct radeon_context radeon; 585adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 586adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Driver and hardware state management 587adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 588adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_hw_state hw; 589adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_state state; 59098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger struct r200_vertex_program *curr_vp_hw; 591adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 592adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Vertex buffers 593adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 594692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_ioctl ioctl; 5950217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie struct radeon_store store; 596adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 597adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Clientdata textures; 598adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 5991090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie GLuint prefer_gart_client_texturing; 600adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 601adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* TCL stuff 602adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 603adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; 604adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; 605adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; 60624a44d74b6e9880dfc019bd1cfa9ce0351377c85Roland Scheidegger GLuint TexMatEnabled; 607adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexMatCompSel; 608adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexGenEnabled; 609adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexGenCompSel; 610adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLmatrix tmpmat; 611adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 612adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* r200_tcl.c 613adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 614adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_tcl_info tcl; 615adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 616adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* r200_swtcl.c 617adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 618adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_swtcl_info swtcl; 619adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 620b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger GLboolean using_hyperz; 6214837ea30208d002bc36a836d2117f826d40c8bfaRoland Scheidegger GLboolean texmicrotile; 622f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 623f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger struct ati_fragment_shader *afs_loaded; 624adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 625adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 626adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) 627adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 628adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 629d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsbergextern void r200DestroyContext( __DRIcontext *driContextPriv ); 630a7a9a91d7b28e5b5faed509d00f0f951e3136b1bKristian Høgsbergextern GLboolean r200CreateContext( gl_api api, 631d3491e775fb07f891463b2185d74bbad62f3ed24Kristian Høgsberg const struct gl_config *glVisual, 632d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIcontext *driContextPriv, 633e532b6288f01b63d8d8ba8c8dc08292967e65490Ian Romanick unsigned major_version, 634e532b6288f01b63d8d8ba8c8dc08292967e65490Ian Romanick unsigned minor_version, 635e532b6288f01b63d8d8ba8c8dc08292967e65490Ian Romanick uint32_t flags, 636e532b6288f01b63d8d8ba8c8dc08292967e65490Ian Romanick unsigned *error, 637adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell void *sharedContextPrivate); 638d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsbergextern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv, 639d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIdrawable *driDrawPriv, 640d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIdrawable *driReadPriv ); 641d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsbergextern GLboolean r200UnbindContext( __DRIcontext *driContextPriv ); 642adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 6431ced546577745d361ad06577914f44f484656d37Alex Deucherextern void r200_init_texcopy_functions(struct dd_function_table *table); 6441ced546577745d361ad06577914f44f484656d37Alex Deucher 645adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* ================================================================ 646adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Debugging: 647adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 648adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 64923295cf8e84495af86f62395d32b3116261927e8Dave Airlie#define R200_DEBUG RADEON_DEBUG 650adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 651b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie 652adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 653adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#endif /* __R200_CONTEXT_H__ */ 654