radeon_state_init.c revision 80c88304fc9d09531b2530b74973821e47b46753
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v 1.3 2003/02/22 06:21:11 dawes Exp $ */ 2/* 3 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * on the rights to use, copy, modify, merge, publish, distribute, sub 11 * license, and/or sell copies of the Software, and to permit persons to whom 12 * the Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Gareth Hughes <gareth@valinux.com> 28 * Keith Whitwell <keith@tungstengraphics.com> 29 */ 30 31#include "glheader.h" 32#include "imports.h" 33#include "api_arrayelt.h" 34 35#include "swrast/swrast.h" 36#include "vbo/vbo.h" 37#include "tnl/tnl.h" 38#include "tnl/t_pipeline.h" 39#include "swrast_setup/swrast_setup.h" 40 41#include "radeon_context.h" 42#include "radeon_ioctl.h" 43#include "radeon_state.h" 44#include "radeon_tcl.h" 45#include "radeon_tex.h" 46#include "radeon_swtcl.h" 47 48#include "xmlpool.h" 49 50/* ============================================================= 51 * State initialization 52 */ 53 54void radeonPrintDirty( radeonContextPtr rmesa, const char *msg ) 55{ 56 struct radeon_state_atom *l; 57 58 fprintf(stderr, msg); 59 fprintf(stderr, ": "); 60 61 foreach(l, &rmesa->hw.atomlist) { 62 if (l->dirty || rmesa->hw.all_dirty) 63 fprintf(stderr, "%s, ", l->name); 64 } 65 66 fprintf(stderr, "\n"); 67} 68 69static int cmdpkt( int id ) 70{ 71 drm_radeon_cmd_header_t h; 72 h.i = 0; 73 h.packet.cmd_type = RADEON_CMD_PACKET; 74 h.packet.packet_id = id; 75 return h.i; 76} 77 78static int cmdvec( int offset, int stride, int count ) 79{ 80 drm_radeon_cmd_header_t h; 81 h.i = 0; 82 h.vectors.cmd_type = RADEON_CMD_VECTORS; 83 h.vectors.offset = offset; 84 h.vectors.stride = stride; 85 h.vectors.count = count; 86 return h.i; 87} 88 89static int cmdscl( int offset, int stride, int count ) 90{ 91 drm_radeon_cmd_header_t h; 92 h.i = 0; 93 h.scalars.cmd_type = RADEON_CMD_SCALARS; 94 h.scalars.offset = offset; 95 h.scalars.stride = stride; 96 h.scalars.count = count; 97 return h.i; 98} 99 100#define CHECK( NM, FLAG ) \ 101static GLboolean check_##NM( GLcontext *ctx ) \ 102{ \ 103 return FLAG; \ 104} 105 106#define TCL_CHECK( NM, FLAG ) \ 107static GLboolean check_##NM( GLcontext *ctx ) \ 108{ \ 109 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ 110 return !rmesa->TclFallback && (FLAG); \ 111} 112 113 114CHECK( always, GL_TRUE ) 115CHECK( never, GL_FALSE ) 116CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled ) 117CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled ) 118/* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */ 119CHECK( tex2, ctx->Texture._EnabledUnits ) 120CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT)) 121CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT)) 122CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT)) 123CHECK( fog, ctx->Fog.Enabled ) 124TCL_CHECK( tcl, GL_TRUE ) 125TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled ) 126TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled ) 127TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled ) 128TCL_CHECK( tcl_lighting, ctx->Light.Enabled ) 129TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled ) 130TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled ) 131TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled ) 132TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled ) 133TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled ) 134TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled ) 135TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled ) 136TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled ) 137TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled ) 138TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) ) 139TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) ) 140TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) ) 141TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) ) 142TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) ) 143TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) ) 144TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled ) 145 146CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) 147CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)) 148CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)) 149 150 151 152/* Initialize the context's hardware state. 153 */ 154void radeonInitState( radeonContextPtr rmesa ) 155{ 156 GLcontext *ctx = rmesa->glCtx; 157 GLuint color_fmt, depth_fmt, i; 158 GLint drawPitch, drawOffset; 159 160 switch ( rmesa->radeonScreen->cpp ) { 161 case 2: 162 color_fmt = RADEON_COLOR_FORMAT_RGB565; 163 break; 164 case 4: 165 color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 166 break; 167 default: 168 fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); 169 exit( -1 ); 170 } 171 172 rmesa->state.color.clear = 0x00000000; 173 174 switch ( ctx->Visual.depthBits ) { 175 case 16: 176 rmesa->state.depth.clear = 0x0000ffff; 177 rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff; 178 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 179 rmesa->state.stencil.clear = 0x00000000; 180 break; 181 case 24: 182 rmesa->state.depth.clear = 0x00ffffff; 183 rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; 184 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 185 rmesa->state.stencil.clear = 0xffff0000; 186 break; 187 default: 188 fprintf( stderr, "Error: Unsupported depth %d... exiting\n", 189 ctx->Visual.depthBits ); 190 exit( -1 ); 191 } 192 193 /* Only have hw stencil when depth buffer is 24 bits deep */ 194 rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && 195 ctx->Visual.depthBits == 24 ); 196 197 rmesa->Fallback = 0; 198 199 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { 200 drawOffset = rmesa->radeonScreen->backOffset; 201 drawPitch = rmesa->radeonScreen->backPitch; 202 } else { 203 drawOffset = rmesa->radeonScreen->frontOffset; 204 drawPitch = rmesa->radeonScreen->frontPitch; 205 } 206 207 rmesa->hw.max_state_size = 0; 208 209#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ 210 do { \ 211 rmesa->hw.ATOM.cmd_size = SZ; \ 212 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \ 213 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \ 214 rmesa->hw.ATOM.name = NM; \ 215 rmesa->hw.ATOM.is_tcl = FLAG; \ 216 rmesa->hw.ATOM.check = check_##CHK; \ 217 rmesa->hw.ATOM.dirty = GL_TRUE; \ 218 rmesa->hw.max_state_size += SZ * sizeof(int); \ 219 } while (0) 220 221 222 /* Allocate state buffers: 223 */ 224 ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 ); 225 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 226 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 227 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 228 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 229 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 230 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 231 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 ); 232 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 ); 233 ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 ); 234 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 ); 235 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 ); 236 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); 237 ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 ); 238 ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 ); 239 ALLOC_STATE( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0 ); 240 if (rmesa->radeonScreen->drmSupportsCubeMapsR100) 241 { 242 ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0 ); 243 ALLOC_STATE( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0 ); 244 ALLOC_STATE( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0 ); 245 } 246 else 247 { 248 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0 ); 249 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0 ); 250 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0 ); 251 } 252 ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 ); 253 ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 ); 254 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); 255 ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 ); 256 ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 257 ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 ); 258 ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); 259 ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 260 ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); 261 ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); 262 ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); 263 ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); 264 ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 ); 265 ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 ); 266 ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 ); 267 ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 ); 268 ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 ); 269 ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 ); 270 ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 ); 271 ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 ); 272 ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 ); 273 ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 ); 274 ALLOC_STATE( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0 ); 275 276 radeonSetUpAtomList( rmesa ); 277 278 /* Fill in the packet headers: 279 */ 280 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC); 281 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL); 282 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH); 283 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN); 284 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH); 285 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK); 286 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE); 287 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL); 288 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(RADEON_EMIT_SE_CNTL_STATUS); 289 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC); 290 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_0); 291 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0); 292 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1); 293 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1); 294 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_2); 295 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_2); 296 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_0); 297 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T0); 298 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_1); 299 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T1); 300 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_2); 301 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T2); 302 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR); 303 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); 304 rmesa->hw.mtl.cmd[MTL_CMD_0] = 305 cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); 306 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0); 307 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1); 308 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_2); 309 rmesa->hw.grd.cmd[GRD_CMD_0] = 310 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 311 rmesa->hw.fog.cmd[FOG_CMD_0] = 312 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 ); 313 rmesa->hw.glt.cmd[GLT_CMD_0] = 314 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 315 rmesa->hw.eye.cmd[EYE_CMD_0] = 316 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 ); 317 318 for (i = 0 ; i < 6; i++) { 319 rmesa->hw.mat[i].cmd[MAT_CMD_0] = 320 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16); 321 } 322 323 for (i = 0 ; i < 8; i++) { 324 rmesa->hw.lit[i].cmd[LIT_CMD_0] = 325 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 326 rmesa->hw.lit[i].cmd[LIT_CMD_1] = 327 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 ); 328 } 329 330 for (i = 0 ; i < 6; i++) { 331 rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 332 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); 333 } 334 335 rmesa->last_ReallyEnabled = -1; 336 337 /* Initial Harware state: 338 */ 339 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS | 340 RADEON_CHROMA_FUNC_FAIL | 341 RADEON_CHROMA_KEY_NEAREST | 342 RADEON_SHADOW_FUNC_EQUAL | 343 RADEON_SHADOW_PASS_1 /*| 344 RADEON_RIGHT_HAND_CUBE_OGL */); 345 346 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX | 347 /* this bit unused for vertex fog */ 348 RADEON_FOG_USE_DEPTH); 349 350 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 351 352 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP | 353 RADEON_SRC_BLEND_GL_ONE | 354 RADEON_DST_BLEND_GL_ZERO ); 355 356 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = 357 rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation; 358 359 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 360 ((rmesa->radeonScreen->depthPitch & 361 RADEON_DEPTHPITCH_MASK) | 362 RADEON_DEPTH_ENDIAN_NO_SWAP); 363 364 if (rmesa->using_hyperz) 365 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ; 366 367 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt | 368 RADEON_Z_TEST_LESS | 369 RADEON_STENCIL_TEST_ALWAYS | 370 RADEON_STENCIL_FAIL_KEEP | 371 RADEON_STENCIL_ZPASS_KEEP | 372 RADEON_STENCIL_ZFAIL_KEEP | 373 RADEON_Z_WRITE_ENABLE); 374 375 if (rmesa->using_hyperz) { 376 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | 377 RADEON_Z_DECOMPRESSION_ENABLE; 378 if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 379 /* works for q3, but slight rendering errors with glxgears ? */ 380/* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ 381 /* need this otherwise get lots of lockups with q3 ??? */ 382 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY; 383 } 384 } 385 386 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | 387 RADEON_ANTI_ALIAS_NONE); 388 389 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | 390 color_fmt | 391 RADEON_ZBLOCK16); 392 393 switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) { 394 case DRI_CONF_DITHER_XERRORDIFFRESET: 395 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; 396 break; 397 case DRI_CONF_DITHER_ORDERED: 398 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; 399 break; 400 } 401 if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) == 402 DRI_CONF_ROUND_ROUND ) 403 rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE; 404 else 405 rmesa->state.color.roundEnable = 0; 406 if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) == 407 DRI_CONF_COLOR_REDUCTION_DITHER ) 408 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; 409 else 410 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; 411 412 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + 413 rmesa->radeonScreen->fbLocation) 414 & RADEON_COLOROFFSET_MASK); 415 416 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch & 417 RADEON_COLORPITCH_MASK) | 418 RADEON_COLOR_ENDIAN_NO_SWAP); 419 420 421 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */ 422 if (rmesa->sarea->tiling_enabled) { 423 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; 424 } 425 426 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | 427 RADEON_BFACE_SOLID | 428 RADEON_FFACE_SOLID | 429/* RADEON_BADVTX_CULL_DISABLE | */ 430 RADEON_FLAT_SHADE_VTX_LAST | 431 RADEON_DIFFUSE_SHADE_GOURAUD | 432 RADEON_ALPHA_SHADE_GOURAUD | 433 RADEON_SPECULAR_SHADE_GOURAUD | 434 RADEON_FOG_SHADE_GOURAUD | 435 RADEON_VPORT_XY_XFORM_ENABLE | 436 RADEON_VPORT_Z_XFORM_ENABLE | 437 RADEON_VTX_PIX_CENTER_OGL | 438 RADEON_ROUND_MODE_TRUNC | 439 RADEON_ROUND_PREC_8TH_PIX); 440 441 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] = 442#ifdef MESA_BIG_ENDIAN 443 RADEON_VC_32BIT_SWAP; 444#else 445 RADEON_VC_NO_SWAP; 446#endif 447 448 if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 449 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; 450 } 451 452 rmesa->hw.set.cmd[SET_SE_COORDFMT] = ( 453 RADEON_VTX_W0_IS_NOT_1_OVER_W0 | 454 RADEON_TEX1_W_ROUTING_USE_Q1); 455 456 457 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 458 459 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 460 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) | 461 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT)); 462 463 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 464 465 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 466 ((0x00 << RADEON_STENCIL_REF_SHIFT) | 467 (0xff << RADEON_STENCIL_MASK_SHIFT) | 468 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT)); 469 470 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY; 471 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 472 473 rmesa->hw.msc.cmd[MSC_RE_MISC] = 474 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) | 475 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) | 476 RADEON_STIPPLE_BIG_BIT_ORDER); 477 478 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 479 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 480 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 481 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 482 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 483 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 484 485 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 486 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL; 487 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 488 (RADEON_TXFORMAT_ENDIAN_NO_SWAP | 489 RADEON_TXFORMAT_PERSPECTIVE_ENABLE | 490 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */ 491 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | 492 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); 493 494 /* Initialize the texture offset to the start of the card texture heap */ 495 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 496 rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 497 498 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 499 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = 500 (RADEON_COLOR_ARG_A_ZERO | 501 RADEON_COLOR_ARG_B_ZERO | 502 RADEON_COLOR_ARG_C_CURRENT_COLOR | 503 RADEON_BLEND_CTL_ADD | 504 RADEON_SCALE_1X | 505 RADEON_CLAMP_TX); 506 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = 507 (RADEON_ALPHA_ARG_A_ZERO | 508 RADEON_ALPHA_ARG_B_ZERO | 509 RADEON_ALPHA_ARG_C_CURRENT_ALPHA | 510 RADEON_BLEND_CTL_ADD | 511 RADEON_SCALE_1X | 512 RADEON_CLAMP_TX); 513 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0; 514 515 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; 516 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] = 517 rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 518 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] = 519 rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 520 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] = 521 rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 522 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] = 523 rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 524 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] = 525 rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 526 } 527 528 /* Can only add ST1 at the time of doing some multitex but can keep 529 * it after that. Errors if DIFFUSE is missing. 530 */ 531 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = 532 (RADEON_TCL_VTX_Z0 | 533 RADEON_TCL_VTX_W0 | 534 RADEON_TCL_VTX_PK_DIFFUSE 535 ); /* need to keep this uptodate */ 536 537 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = 538 ( RADEON_TCL_COMPUTE_XYZW | 539 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | 540 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | 541 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT)); 542 543 544 /* XXX */ 545 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = 546 ((MODEL << RADEON_MODELVIEW_0_SHIFT) | 547 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT)); 548 549 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = 550 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) | 551 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) | 552 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) | 553 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT)); 554 555 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 556 (RADEON_UCP_IN_CLIP_SPACE | 557 RADEON_CULL_FRONT_IS_CCW); 558 559 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; 560 561 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = 562 (RADEON_SPECULAR_LIGHTS | 563 RADEON_DIFFUSE_SPECULAR_COMBINE | 564 RADEON_LOCAL_LIGHT_VEC_GL | 565 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) | 566 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) | 567 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) | 568 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT)); 569 570 for (i = 0 ; i < 8; i++) { 571 struct gl_light *l = &ctx->Light.Light[i]; 572 GLenum p = GL_LIGHT0 + i; 573 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 574 575 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 576 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 577 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 578 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); 579 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); 580 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 581 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 582 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 583 &l->ConstantAttenuation ); 584 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 585 &l->LinearAttenuation ); 586 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 587 &l->QuadraticAttenuation ); 588 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 589 } 590 591 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 592 ctx->Light.Model.Ambient ); 593 594 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 595 596 for (i = 0 ; i < 6; i++) { 597 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 598 } 599 600 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); 601 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 602 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 603 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 604 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 605 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); 606 607 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 608 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 609 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 610 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 611 612 rmesa->hw.eye.cmd[EYE_X] = 0; 613 rmesa->hw.eye.cmd[EYE_Y] = 0; 614 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 615 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 616 617 rmesa->hw.all_dirty = GL_TRUE; 618} 619