radeon_state_init.c revision f64f940281f0d716e0ddc641e7ef1728f143d67f
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v 1.3 2003/02/22 06:21:11 dawes Exp $ */ 2/* 3 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * on the rights to use, copy, modify, merge, publish, distribute, sub 11 * license, and/or sell copies of the Software, and to permit persons to whom 12 * the Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Gareth Hughes <gareth@valinux.com> 28 * Keith Whitwell <keith@tungstengraphics.com> 29 */ 30 31#include "glheader.h" 32#include "imports.h" 33#include "api_arrayelt.h" 34 35#include "swrast/swrast.h" 36#include "array_cache/acache.h" 37#include "tnl/tnl.h" 38#include "tnl/t_pipeline.h" 39#include "swrast_setup/swrast_setup.h" 40 41#include "radeon_context.h" 42#include "radeon_ioctl.h" 43#include "radeon_state.h" 44#include "radeon_tcl.h" 45#include "radeon_tex.h" 46#include "radeon_swtcl.h" 47#include "radeon_vtxfmt.h" 48 49#include "xmlpool.h" 50 51/* ============================================================= 52 * State initialization 53 */ 54 55void radeonPrintDirty( radeonContextPtr rmesa, const char *msg ) 56{ 57 struct radeon_state_atom *l; 58 59 fprintf(stderr, msg); 60 fprintf(stderr, ": "); 61 62 foreach(l, &(rmesa->hw.dirty)) { 63 fprintf(stderr, "%s, ", l->name); 64 } 65 66 fprintf(stderr, "\n"); 67} 68 69static int cmdpkt( int id ) 70{ 71 drmRadeonCmdHeader h; 72 h.i = 0; 73 h.packet.cmd_type = RADEON_CMD_PACKET; 74 h.packet.packet_id = id; 75 return h.i; 76} 77 78static int cmdvec( int offset, int stride, int count ) 79{ 80 drmRadeonCmdHeader h; 81 h.i = 0; 82 h.vectors.cmd_type = RADEON_CMD_VECTORS; 83 h.vectors.offset = offset; 84 h.vectors.stride = stride; 85 h.vectors.count = count; 86 return h.i; 87} 88 89static int cmdscl( int offset, int stride, int count ) 90{ 91 drmRadeonCmdHeader h; 92 h.i = 0; 93 h.scalars.cmd_type = RADEON_CMD_SCALARS; 94 h.scalars.offset = offset; 95 h.scalars.stride = stride; 96 h.scalars.count = count; 97 return h.i; 98} 99 100#define CHECK( NM, FLAG ) \ 101static GLboolean check_##NM( GLcontext *ctx ) \ 102{ \ 103 return FLAG; \ 104} 105 106#define TCL_CHECK( NM, FLAG ) \ 107static GLboolean check_##NM( GLcontext *ctx ) \ 108{ \ 109 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ 110 return !rmesa->TclFallback && (FLAG); \ 111} 112 113 114CHECK( always, GL_TRUE ) 115CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled ) 116CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled ) 117CHECK( fog, ctx->Fog.Enabled ) 118TCL_CHECK( tcl, GL_TRUE ) 119TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled ) 120TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled ) 121TCL_CHECK( tcl_lighting, ctx->Light.Enabled ) 122TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled ) 123TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled ) 124TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled ) 125TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled ) 126TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled ) 127TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled ) 128TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled ) 129TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled ) 130TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled ) 131TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) ) 132TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) ) 133TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) ) 134TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) ) 135TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) ) 136TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) ) 137TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled ) 138 139CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) 140CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)) 141 142 143 144/* Initialize the context's hardware state. 145 */ 146void radeonInitState( radeonContextPtr rmesa ) 147{ 148 GLcontext *ctx = rmesa->glCtx; 149 GLuint color_fmt, depth_fmt, i; 150 151 switch ( rmesa->radeonScreen->cpp ) { 152 case 2: 153 color_fmt = RADEON_COLOR_FORMAT_RGB565; 154 break; 155 case 4: 156 color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 157 break; 158 default: 159 fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); 160 exit( -1 ); 161 } 162 163 rmesa->state.color.clear = 0x00000000; 164 165 switch ( ctx->Visual.depthBits ) { 166 case 16: 167 rmesa->state.depth.clear = 0x0000ffff; 168 rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff; 169 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 170 rmesa->state.stencil.clear = 0x00000000; 171 break; 172 case 24: 173 rmesa->state.depth.clear = 0x00ffffff; 174 rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; 175 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 176 rmesa->state.stencil.clear = 0xff000000; 177 break; 178 default: 179 fprintf( stderr, "Error: Unsupported depth %d... exiting\n", 180 ctx->Visual.depthBits ); 181 exit( -1 ); 182 } 183 184 /* Only have hw stencil when depth buffer is 24 bits deep */ 185 rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && 186 ctx->Visual.depthBits == 24 ); 187 188 rmesa->Fallback = 0; 189 190 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { 191 rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset; 192 rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch; 193 } else { 194 rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset; 195 rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch; 196 } 197 rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset; 198 rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch; 199 200 /* Initialize lists: 201 */ 202 make_empty_list(&(rmesa->hw.dirty)); 203 make_empty_list(&(rmesa->hw.clean)); 204 205 206#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ 207 do { \ 208 rmesa->hw.ATOM.cmd_size = SZ; \ 209 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \ 210 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \ 211 rmesa->hw.ATOM.name = NM; \ 212 rmesa->hw.ATOM.is_tcl = FLAG; \ 213 rmesa->hw.ATOM.check = check_##CHK; \ 214 insert_at_head(&(rmesa->hw.dirty), &(rmesa->hw.ATOM)); \ 215 } while (0) 216 217 218 /* Allocate state buffers: 219 */ 220 ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 ); 221 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 222 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 223 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 224 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 225 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 226 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 227 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 ); 228 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 ); 229 ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 ); 230 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 ); 231 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 ); 232 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); 233 ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 ); 234 ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 ); 235 ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 ); 236 ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 ); 237 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); 238 ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 ); 239 ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 240 ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); 241 ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 242 ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); 243 ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); 244 ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); 245 ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); 246 ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 ); 247 ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 ); 248 ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 ); 249 ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 ); 250 ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 ); 251 ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 ); 252 ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 ); 253 ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 ); 254 ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 ); 255 ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 ); 256 257 258 /* Fill in the packet headers: 259 */ 260 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC); 261 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL); 262 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH); 263 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN); 264 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH); 265 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK); 266 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE); 267 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL); 268 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(RADEON_EMIT_SE_CNTL_STATUS); 269 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC); 270 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_0); 271 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0); 272 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1); 273 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1); 274 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR); 275 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); 276 rmesa->hw.mtl.cmd[MTL_CMD_0] = 277 cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); 278 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0); 279 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1); 280 rmesa->hw.grd.cmd[GRD_CMD_0] = 281 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 282 rmesa->hw.fog.cmd[FOG_CMD_0] = 283 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 ); 284 rmesa->hw.glt.cmd[GLT_CMD_0] = 285 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 286 rmesa->hw.eye.cmd[EYE_CMD_0] = 287 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 ); 288 289 for (i = 0 ; i < 5; i++) { 290 rmesa->hw.mat[i].cmd[MAT_CMD_0] = 291 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16); 292 } 293 294 for (i = 0 ; i < 8; i++) { 295 rmesa->hw.lit[i].cmd[LIT_CMD_0] = 296 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 297 rmesa->hw.lit[i].cmd[LIT_CMD_1] = 298 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 ); 299 } 300 301 for (i = 0 ; i < 6; i++) { 302 rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 303 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); 304 } 305 306 rmesa->last_ReallyEnabled = -1; 307 308 /* Initial Harware state: 309 */ 310 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS | 311 RADEON_CHROMA_FUNC_FAIL | 312 RADEON_CHROMA_KEY_NEAREST | 313 RADEON_SHADOW_FUNC_EQUAL | 314 RADEON_SHADOW_PASS_1 | 315 RADEON_RIGHT_HAND_CUBE_OGL); 316 317 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX | 318 RADEON_FOG_USE_DEPTH); 319 320 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 321 322 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP | 323 RADEON_SRC_BLEND_GL_ONE | 324 RADEON_DST_BLEND_GL_ZERO ); 325 326 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = 327 rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation; 328 329 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 330 ((rmesa->radeonScreen->depthPitch & 331 RADEON_DEPTHPITCH_MASK) | 332 RADEON_DEPTH_ENDIAN_NO_SWAP); 333 334 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt | 335 RADEON_Z_TEST_LESS | 336 RADEON_STENCIL_TEST_ALWAYS | 337 RADEON_STENCIL_FAIL_KEEP | 338 RADEON_STENCIL_ZPASS_KEEP | 339 RADEON_STENCIL_ZFAIL_KEEP | 340 RADEON_Z_WRITE_ENABLE); 341 342 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | 343 RADEON_ANTI_ALIAS_NONE); 344 345 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | 346 color_fmt | 347 (1<<15)); 348 349 switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) { 350 case DRI_CONF_DITHER_XERRORDIFFRESET: 351 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; 352 break; 353 case DRI_CONF_DITHER_ORDERED: 354 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; 355 break; 356 } 357 if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) == 358 DRI_CONF_ROUND_ROUND ) 359 rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE; 360 else 361 rmesa->state.color.roundEnable = 0; 362 if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) == 363 DRI_CONF_COLOR_REDUCTION_DITHER ) 364 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; 365 else 366 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; 367 368 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + 369 rmesa->radeonScreen->fbLocation) 370 & RADEON_COLOROFFSET_MASK); 371 372 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & 373 RADEON_COLORPITCH_MASK) | 374 RADEON_COLOR_ENDIAN_NO_SWAP); 375 376 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | 377 RADEON_BFACE_SOLID | 378 RADEON_FFACE_SOLID | 379/* RADEON_BADVTX_CULL_DISABLE | */ 380 RADEON_FLAT_SHADE_VTX_LAST | 381 RADEON_DIFFUSE_SHADE_GOURAUD | 382 RADEON_ALPHA_SHADE_GOURAUD | 383 RADEON_SPECULAR_SHADE_GOURAUD | 384 RADEON_FOG_SHADE_GOURAUD | 385 RADEON_VPORT_XY_XFORM_ENABLE | 386 RADEON_VPORT_Z_XFORM_ENABLE | 387 RADEON_VTX_PIX_CENTER_OGL | 388 RADEON_ROUND_MODE_TRUNC | 389 RADEON_ROUND_PREC_8TH_PIX); 390 391 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] = 392#ifdef MESA_BIG_ENDIAN 393 RADEON_VC_32BIT_SWAP; 394#else 395 RADEON_VC_NO_SWAP; 396#endif 397 398 if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) { 399 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; 400 } 401 402 rmesa->hw.set.cmd[SET_SE_COORDFMT] = ( 403 RADEON_VTX_W0_IS_NOT_1_OVER_W0 | 404 RADEON_TEX1_W_ROUTING_USE_Q1); 405 406 407 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 408 409 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 410 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) | 411 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT)); 412 413 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 414 415 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 416 ((0x00 << RADEON_STENCIL_REF_SHIFT) | 417 (0xff << RADEON_STENCIL_MASK_SHIFT) | 418 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT)); 419 420 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY; 421 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 422 423 rmesa->hw.msc.cmd[MSC_RE_MISC] = 424 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) | 425 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) | 426 RADEON_STIPPLE_BIG_BIT_ORDER); 427 428 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 429 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 430 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 431 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 432 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 433 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 434 435 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 436 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL; 437 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 438 (RADEON_TXFORMAT_ENDIAN_NO_SWAP | 439 RADEON_TXFORMAT_PERSPECTIVE_ENABLE | 440 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */ 441 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | 442 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); 443 444 /* Initialize the texture offset to the start of the card texture heap */ 445 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 446 rmesa->radeonScreen->texOffset[RADEON_CARD_HEAP]; 447 448 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 449 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = 450 (RADEON_COLOR_ARG_A_ZERO | 451 RADEON_COLOR_ARG_B_ZERO | 452 RADEON_COLOR_ARG_C_CURRENT_COLOR | 453 RADEON_BLEND_CTL_ADD | 454 RADEON_SCALE_1X | 455 RADEON_CLAMP_TX); 456 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = 457 (RADEON_ALPHA_ARG_A_ZERO | 458 RADEON_ALPHA_ARG_B_ZERO | 459 RADEON_ALPHA_ARG_C_CURRENT_ALPHA | 460 RADEON_BLEND_CTL_ADD | 461 RADEON_SCALE_1X | 462 RADEON_CLAMP_TX); 463 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0; 464 } 465 466 /* Can only add ST1 at the time of doing some multitex but can keep 467 * it after that. Errors if DIFFUSE is missing. 468 */ 469 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = 470 (RADEON_TCL_VTX_Z0 | 471 RADEON_TCL_VTX_W0 | 472 RADEON_TCL_VTX_PK_DIFFUSE 473 ); /* need to keep this uptodate */ 474 475 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = 476 ( RADEON_TCL_COMPUTE_XYZW | 477 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | 478 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | 479 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT)); 480 481 482 /* XXX */ 483 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = 484 ((MODEL << RADEON_MODELVIEW_0_SHIFT) | 485 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT)); 486 487 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = 488 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) | 489 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) | 490 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT)); 491 492 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 493 (RADEON_UCP_IN_CLIP_SPACE | 494 RADEON_CULL_FRONT_IS_CCW); 495 496 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; 497 498 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = 499 (RADEON_SPECULAR_LIGHTS | 500 RADEON_DIFFUSE_SPECULAR_COMBINE | 501 RADEON_LOCAL_LIGHT_VEC_GL | 502 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) | 503 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) | 504 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) | 505 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT)); 506 507 for (i = 0 ; i < 8; i++) { 508 struct gl_light *l = &ctx->Light.Light[i]; 509 GLenum p = GL_LIGHT0 + i; 510 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 511 512 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 513 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 514 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 515 ctx->Driver.Lightfv( ctx, p, GL_POSITION, 0 ); 516 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, 0 ); 517 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 518 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 519 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 520 &l->ConstantAttenuation ); 521 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 522 &l->LinearAttenuation ); 523 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 524 &l->QuadraticAttenuation ); 525 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 526 } 527 528 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 529 ctx->Light.Model.Ambient ); 530 531 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 532 533 for (i = 0 ; i < 6; i++) { 534 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 535 } 536 537 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, 0 ); 538 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 539 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 540 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 541 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 542 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, 0 ); 543 544 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 545 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 546 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 547 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 548 549 rmesa->hw.eye.cmd[EYE_X] = 0; 550 rmesa->hw.eye.cmd[EYE_Y] = 0; 551 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 552 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 553} 554