Cross Reference: /art/compiler/dex/quick/arm/utility

Lines Matching refs:r_dest
72 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) {
73   DCHECK(RegStorage::IsSingle(r_dest));
78     NewLIR2(kThumb2Vmovs_IMM8, r_dest, 0);
80     return NewLIR3(kThumb2Vsubs, r_dest, r_dest, r_dest);
84       return NewLIR2(kThumb2Vmovs_IMM8, r_dest, encoded_imm);
93                           r_dest, rs_r15pc.GetReg(), 0, 0, 0, data_target);
170  * 1) r_dest is freshly returned from AllocTemp or
173 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
177   if (r_dest.IsFloat()) {
178     return LoadFPConstantValue(r_dest.GetReg(), value);
182   if (r_dest.Low8() && (value >= 0) && (value <= 255)) {
183     return NewLIR2(kThumbMovImm, r_dest.GetReg(), value);
188     res = NewLIR2(kThumb2MovI8M, r_dest.GetReg(), mod_imm);
193     res = NewLIR2(kThumb2MvnI8M, r_dest.GetReg(), mod_imm);
198     res = NewLIR2(kThumb2MovImm16, r_dest.GetReg(), value);
202   res = NewLIR2(kThumb2MovImm16, r_dest.GetReg(), Low16Bits(value));
203   NewLIR2(kThumb2MovImm16H, r_dest.GetReg(), High16Bits(value));
375 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
390 LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1,
393   bool thumb_form = (shift == 0) && r_dest.Low8() && r_src1.Low8() && r_src2.Low8();
452     return NewLIR4(opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg(), shift);
455     return NewLIR3(opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg());
459 LIR* ArmMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) {
460   return OpRegRegRegShift(op, r_dest, r_src1, r_src2, 0);
463 LIR* ArmMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) {
469   bool all_low_regs = r_dest.Low8() && r_src1.Low8();
475         return NewLIR3(kThumbLslRRI5, r_dest.GetReg(), r_src1.GetReg(), value);
477         return NewLIR3(kThumb2LslRRI5, r_dest.GetReg(), r_src1.GetReg(), value);
480         return NewLIR3(kThumbLsrRRI5, r_dest.GetReg(), r_src1.GetReg(), value);
482         return NewLIR3(kThumb2LsrRRI5, r_dest.GetReg(), r_src1.GetReg(), value);
485         return NewLIR3(kThumbAsrRRI5, r_dest.GetReg(), r_src1.GetReg(), value);
487         return NewLIR3(kThumb2AsrRRI5, r_dest.GetReg(), r_src1.GetReg(), value);
489       return NewLIR3(kThumb2RorRRI5, r_dest.GetReg(), r_src1.GetReg(), value);
491       if (r_dest.Low8() && (r_src1 == rs_r13sp) && (value <= 1020) && ((value & 0x3) == 0)) {
492         return NewLIR3(kThumbAddSpRel, r_dest.GetReg(), r_src1.GetReg(), value >> 2);
493       } else if (r_dest.Low8() && (r_src1 == rs_r15pc) &&
495         return NewLIR3(kThumbAddPcRel, r_dest.GetReg(), r_src1.GetReg(), value >> 2);
504         return NewLIR3(opcode, r_dest.GetReg(), r_src1.GetReg(), abs_value);
519         return NewLIR3(opcode, r_dest.GetReg(), r_src1.GetReg(), abs_value);
549           return NewLIR3(kThumb2BicRRI8M, r_dest.GetReg(), r_src1.GetReg(), mod_imm);
586     return NewLIR3(opcode, r_dest.GetReg(), r_src1.GetReg(), mod_imm);
591       res = NewLIR4(alt_opcode, r_dest.GetReg(), r_src1.GetReg(), r_scratch.GetReg(), 0);
593       res = NewLIR3(alt_opcode, r_dest.GetReg(), r_src1.GetReg(), r_scratch.GetReg());
641 LIR* ArmMir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) {
645   if (r_dest.IsFloat()) {
646     DCHECK(!r_dest.IsPair());
651       NewLIR2(kThumb2Vmovd_IMM8, r_dest.GetReg(), 0);
653       res = NewLIR3(kThumb2Vsubd, r_dest.GetReg(), r_dest.GetReg(), r_dest.GetReg());
657         res = NewLIR2(kThumb2Vmovd_IMM8, r_dest.GetReg(), encoded_imm);
662     DCHECK(r_dest.IsPair());
664       res = LoadConstantNoClobber(r_dest.GetLow(), val_lo);
665       LoadConstantNoClobber(r_dest.GetHigh(), val_hi);
675     if (r_dest.IsFloat()) {
677                    r_dest.GetReg(), rs_r15pc.GetReg(), 0, 0, 0, data_target);
679       DCHECK(r_dest.IsPair());
681                    r_dest.GetLowReg(), r_dest.GetHighReg(), rs_r15pc.GetReg(), 0, 0, data_target);
692 LIR* ArmMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
694   bool all_low_regs = r_base.Low8() && r_index.Low8() && r_dest.Low8();
700   if (r_dest.IsFloat()) {
701     if (r_dest.IsSingle()) {
706       DCHECK(r_dest.IsDouble());
727       load = NewLIR3(opcode, r_dest.GetReg(), reg_ptr.GetReg(), 0);
751     load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg());
753     load = NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale);
854 LIR* ArmMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
860   bool all_low = r_dest.Is32Bit() && r_base.Low8() && r_dest.Low8();
867       if (r_dest.IsFloat()) {
868         DCHECK(!r_dest.IsPair());
869         load = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vldrd, r_base, displacement, r_dest);
871         DCHECK(r_dest.IsPair());
872         // Use the r_dest.GetLow() for the temporary pointer if needed.
873         load = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2LdrdI8, r_base, displacement, r_dest,
874                                                     r_dest.GetLow());
883       if (r_dest.IsFloat()) {
884         DCHECK(r_dest.IsSingle());
885         load = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vldrs, r_base, displacement, r_dest);
889       if (r_dest.Low8() && (r_base == rs_rARM_PC) && (displacement <= 1020) &&
894       } else if (r_dest.Low8() && (r_base == rs_rARM_SP) && (displacement <= 1020) &&
947       load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), encoded_disp);
951       DCHECK(!r_dest.IsFloat());
952       load = LoadBaseIndexed(r_base, reg_offset, r_dest, 0, size);
960     AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit());
965 LIR* ArmMir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
977     DCHECK(!r_dest.IsFloat());  // See RegClassForFieldLoadSave().
981     LIR* lir = NewLIR3(kThumb2Ldrexd, r_dest.GetLowReg(), r_dest.GetHighReg(), r_ptr.GetReg());
985     load = LoadBaseDispBody(r_base, displacement, r_dest, size);
1143 LIR* ArmMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
1145   DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
1146   if (r_dest.IsDouble()) {
1149     if (r_dest.IsSingle()) {
1156   LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
1157   if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {