Cross Reference: /art/compiler/dex/quick/mips/utility

Lines Matching refs:r_dest
25 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
28   DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
29   if (r_dest.IsDouble()) {
32     if (r_dest.IsSingle()) {
38         r_src = r_dest;
39         r_dest = t_opnd;
47   LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src.GetReg(), r_dest.GetReg());
48   if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
76  * 1) r_dest is freshly returned from AllocTemp or
79 LIR* MipsMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
82   RegStorage r_dest_save = r_dest;
83   int is_fp_reg = r_dest.IsFloat();
85     DCHECK(r_dest.IsSingle());
86     r_dest = AllocTemp();
91     res = NewLIR2(kMipsMove, r_dest.GetReg(), rZERO);
93     res = NewLIR3(kMipsOri, r_dest.GetReg(), rZERO, value);
95     res = NewLIR3(kMipsAddiu, r_dest.GetReg(), rZERO, value);
97     res = NewLIR2(kMipsLui, r_dest.GetReg(), value >> 16);
99       NewLIR3(kMipsOri, r_dest.GetReg(), r_dest.GetReg(), value);
103     NewLIR2(kMipsMtc1, r_dest.GetReg(), r_dest_save.GetReg());
104     FreeTemp(r_dest);
161 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) {
199   return NewLIR3(opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg());
202 LIR* MipsMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) {
271     res = NewLIR3(opcode, r_dest.GetReg(), r_src1.GetReg(), value);
273     if (r_dest != r_src1) {
274       res = LoadConstant(r_dest, value);
275       NewLIR3(opcode, r_dest.GetReg(), r_src1.GetReg(), r_dest.GetReg());
279       NewLIR3(opcode, r_dest.GetReg(), r_src1.GetReg(), r_scratch.GetReg());
328 LIR* MipsMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset,
339 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
344 LIR* MipsMir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) {
346   if (!r_dest.IsPair()) {
348     r_dest = Solo64ToPair64(r_dest);
350   res = LoadConstantNoClobber(r_dest.GetLow(), Low32Bits(value));
351   LoadConstantNoClobber(r_dest.GetHigh(), High32Bits(value));
356 LIR* MipsMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
363   if (r_dest.IsFloat()) {
364     DCHECK(r_dest.IsSingle());
403   res = NewLIR3(opcode, r_dest.GetReg(), 0, t_reg.GetReg());
454 // FIXME: don't split r_dest into 2 containers.
455 LIR* MipsMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
470   bool pair = r_dest.IsPair();
477         r_dest = Solo64ToPair64(r_dest);
480       if (r_dest.IsFloat()) {
481         DCHECK_EQ(r_dest.GetLowReg(), r_dest.GetHighReg() - 1);
493       if (r_dest.IsFloat()) {
495         DCHECK(r_dest.IsSingle());
519       load = res = NewLIR3(opcode, r_dest.GetReg(), displacement, r_base.GetReg());
521       load = res = NewLIR3(opcode, r_dest.GetLowReg(), displacement + LOWORD_OFFSET, r_base.GetReg());
522       load2 = NewLIR3(opcode, r_dest.GetHighReg(), displacement + HIWORD_OFFSET, r_base.GetReg());
528       load = NewLIR3(opcode, r_dest.GetLowReg(), LOWORD_OFFSET, r_tmp.GetReg());
529       load2 = NewLIR3(opcode, r_dest.GetHighReg(), HIWORD_OFFSET, r_tmp.GetReg());
532       RegStorage r_tmp = (r_base == r_dest) ? AllocTemp() : r_dest;
534       load = NewLIR3(opcode, r_dest.GetReg(), 0, r_tmp.GetReg());
535       if (r_tmp != r_dest)
552 LIR* MipsMir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
556     return GenAtomic64Load(r_base, displacement, r_dest);
564   load = LoadBaseDispBody(r_base, displacement, r_dest, size);
573 // FIXME: don't split r_dest into 2 containers.