Lines Matching defs:t5
17 register uint32_t t0, t1, t2, t3, t4, t5, t6;
44 "shrl.qb %[t5], %[t0], 3 \n\t"
45 "and %[t4], %[t5], %[s5] \n\t"
50 "shrl.ph %[t5], %[s2], 10 \n\t"
53 "and %[t5], %[t0], %[s6] \n\t"
56 "subu.qb %[t5], %[t5], %[t2] \n\t"
59 "muleu_s.ph.qbr %[t5], %[s4], %[t5] \n\t"
64 "shra.ph %[t5], %[t5], 8 \n\t"
67 "addu.qb %[t5], %[t5], %[t2] \n\t"
70 "andi %[t0], %[t5], 0xffff \n\t"
77 "srl %[t0], %[t5], 16 \n\t"
78 "sll %[t5], %[t0], 5 \n\t"
79 "or %[t0], %[t5], %[s1] \n\t"
88 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [s0]"=&r"(s0),
121 register int32_t t0, t1, t2, t3, t4, t5, t6;
142 "srav %[t5], %[dither_scan], %[t4] \n\t"
143 "andi %[t3], %[t5], 0xf \n\t"
146 "sll %[t5], %[t4], 2 \n\t"
147 "srav %[t6], %[dither_scan], %[t5] \n\t"
153 "addiu %[t5], %[t4], 1 \n\t"
154 "ins %[t0], %[t5], 16, 16 \n\t"
159 "shrl.qb %[t5], %[t4], 5 \n\t"
160 "subu.qb %[t6], %[t3], %[t5] \n\t"
161 "addq.ph %[t5], %[t6], %[t4] \n\t"
180 "andi %[t6], %[t5], 0xffff \n\t"
181 "srl %[t7], %[t5], 16 \n\t"
182 "subq.ph %[t5], %[s1], %[t0] \n\t"
183 "srl %[t0], %[t5], 3 \n\t"
185 " lhu %[t5], 0(%[dst]) \n\t"
190 "andi %[t3], %[t5], 0x7e0 \n\t"
192 "and %[t8], %[s2], %[t5] \n\t"
193 "or %[t5], %[t6], %[t8] \n\t"
195 "mul %[t1], %[t6], %[t5] \n\t"
196 "addu %[t5], %[t1], %[t9] \n\t"
197 "srl %[t6], %[t5], 5 \n\t"
198 "and %[t5], %[s2], %[t6] \n\t"
201 "or %[t1], %[t5], %[t6] \n\t"
205 " lhu %[t5], 2(%[dst]) \n\t"
210 "andi %[t3], %[t5], 0x7e0 \n\t"
212 "and %[t8], %[s2], %[t5] \n\t"
213 "or %[t5], %[t6], %[t8] \n\t"
215 "mul %[t1], %[t6], %[t5] \n\t"
216 "addu %[t5], %[t1], %[t9] \n\t"
217 "srl %[t6], %[t5], 5 \n\t"
218 "and %[t5], %[s2], %[t6] \n\t"
221 "or %[t1], %[t5], %[t6] \n\t"
232 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [t7]"=&r"(t7),
269 register uint32_t t0, t1, t2, t3, t4, t5;
309 "preceu.ph.qbla %[t5], %[t0] \n\t"
315 "preceu.ph.qbla %[t5], %[t8] \n\t"
326 "shra.ph %[t2], %[t5], 6 \n\t"
327 "addu.qb %[t3], %[t5], %[t0] \n\t"
339 "andi %[t5], %[t8], 0xFF \n\t"
345 "sll %[t7], %[t5], 5 \n\t"
360 [t3]"=&r"(t3), [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6),
378 register int32_t t0, t1, t2, t3, t4, t5, t6;
436 "sll %[t5], %[s0], 8 \n\t"
438 "precrq.qb.ph %[t4], %[t5], %[t6] \n\t"
440 "preceu.ph.qbla %[t5], %[t4] \n\t"
460 "shrl.qb %[t3], %[t5], 5 \n\t"
461 "addu.qb %[t5], %[t5], %[t0] \n\t"
462 "subu.qb %[t5], %[t5], %[t3] \n\t"
463 "shrl.qb %[t5], %[t5], 3 \n\t"
476 "cmpu.lt.qb %[t5], %[s3] \n\t"
479 "subu.qb %[t5], %[t5], %[s3] \n\t"
480 "muleu_s.ph.qbl %[t0], %[t5], %[sc_mul] \n\t"
481 "muleu_s.ph.qbr %[t1], %[t5], %[sc_mul] \n\t"
482 "precrq.qb.ph %[t5], %[t0], %[t1] \n\t"
483 "addu.qb %[t5], %[t5], %[s0] \n\t"
495 "or %[s1], %[s0], %[t5] \n\t"
509 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [s0]"=&r"(s0),
550 register uint32_t t0, t1, t2, t3, t4, t5, t6, t7, t8;
590 "or %[t5], %[t2], %[t1] \n\t"
591 "replv.ph %[t2], %[t5] \n\t"
598 "sll %[t5], %[t0], 16 \n\t"
599 "or %[t0], %[t5], %[t1] \n\t"
605 "shra.ph %[t5], %[t7], 5 \n\t"
620 "muleu_s.ph.qbl %[t0], %[t2], %[t5] \n\t"
642 [t3]"=&r"(t3), [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6),
661 register uint32_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
678 "lh %[t5], 2(%[dst]) \n\t"
679 "sll %[t5], %[t5], 16 \n\t"
689 "packrl.ph %[t9], %[t4], %[t5] \n\t"
696 "shra.ph %[t5], %[s3], 8 \n\t"
697 "and %[t5], %[t5], 0xFF00FF \n\t"
698 "addq.ph %[dst_scale], %[s3], %[t5] \n\t"
744 [t2]"=&r"(t2), [t3]"=&r"(t3), [t4]"=&r"(t4), [t5]"=&r"(t5),
771 register int32_t t0, t1, t2, t3, t4, t5, t6, t7;
788 "preceu.ph.qbl %[t5], %[t1] \n\t"
792 "muleu_s.ph.qbr %[t5], %[t6], %[t5] \n\t"
796 "precrq.qb.ph %[t2], %[t5], %[t4] \n\t"
805 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [t7]"=&r"(t7)