Lines Matching defs:Imm
4418 unsigned OpCmode, Imm;
4435 Imm = SplatBits;
4445 Imm = SplatBits;
4451 Imm = SplatBits >> 8;
4465 Imm = SplatBits;
4471 Imm = SplatBits >> 8;
4477 Imm = SplatBits >> 16;
4483 Imm = SplatBits >> 24;
4494 Imm = SplatBits >> 8;
4502 Imm = SplatBits >> 16;
4520 Imm = 0;
4524 Imm |= ImmMask;
4534 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4546 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4632 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4639 Imm = M[0];
4644 unsigned ExpectedElt = Imm;
4662 bool &ReverseVEXT, unsigned &Imm) {
4670 Imm = M[0];
4675 unsigned ExpectedElt = Imm;
4692 Imm -= NumElts;
5276 unsigned Imm, WhichResult;
5284 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5456 unsigned Imm;
5457 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5461 DAG.getConstant(Imm, MVT::i32));
5472 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5474 DAG.getConstant(Imm, MVT::i32));
9054 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9056 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9994 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9997 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
9999 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
10001 return Imm >= 0 && Imm <= 255;
10008 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10010 int64_t AbsImm = llvm::abs64(Imm);
10646 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10650 return ARM_AM::getFP32Imm(Imm) != -1;
10652 return ARM_AM::getFP64Imm(Imm) != -1;
10768 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,