Lines Matching refs:RegKind
87 // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
93 unsigned RegKind : 8;
152 createMem(RegisterKind RegKind, unsigned Base, const MCExpr *Disp,
156 Op->Mem.RegKind = RegKind;
177 bool isReg(RegisterKind RegKind) const {
178 return Kind == KindReg && Reg.Kind == RegKind;
207 bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
209 Mem.RegKind == RegKind &&
213 bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
214 return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
216 bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
217 return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
219 bool isMemDisp12Len8(RegisterKind RegKind) const {
220 return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
322 const unsigned *Regs, RegisterKind RegKind);
325 const unsigned *Regs, RegisterKind RegKind,
493 // Regs maps asm register numbers to LLVM register numbers and RegKind
498 RegisterKind RegKind) {
513 if (parseRegister(Reg, RegGR, Regs, RegKind))
529 if (parseRegister(Reg, RegGR, Regs, RegKind))
546 RegisterKind RegKind, MemoryKind MemKind) {
551 if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
574 Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,