Cross Reference: /external/valgrind/main/callgrind/sim.c

Lines Matching refs:CacheModelResult
140     WriteBackMemAccess } CacheModelResult;
142 typedef CacheModelResult (*simcall_type)(Addr, UChar);
243  *  CacheModelResult cachesim_I1_ref(Addr a, UChar size)
244  *  CacheModelResult cachesim_D1_ref(Addr a, UChar size)
316 CacheModelResult cachesim_I1_ref(Addr a, UChar size)
324 CacheModelResult cachesim_D1_ref(Addr a, UChar size)
341  *  CacheModelResult cachesim_I1_Read(Addr a, UChar size)
342  *  CacheModelResult cachesim_D1_Read(Addr a, UChar size)
343  *  CacheModelResult cachesim_D1_Write(Addr a, UChar size)
424 CacheModelResult cachesim_I1_Read(Addr a, UChar size)
436 CacheModelResult cachesim_D1_Read(Addr a, UChar size)
448 CacheModelResult cachesim_D1_Write(Addr a, UChar size)
531 CacheModelResult prefetch_I1_ref(Addr a, UChar size)
540 CacheModelResult prefetch_D1_ref(Addr a, UChar size)
552 CacheModelResult prefetch_I1_Read(Addr a, UChar size)
565 CacheModelResult prefetch_D1_Read(Addr a, UChar size)
578 CacheModelResult prefetch_D1_Write(Addr a, UChar size)
687 static CacheModelResult cacheuse##_##L##_doRead(Addr a, UChar size)         \
883 CacheModelResult cacheuse_LL_access(Addr memline, line_loaded* l1_loaded)
939 static CacheModelResult update##_##L##_use(cache_t2* cache, int idx, \
1022 void inc_costs(CacheModelResult r, ULong* c1, ULong* c2)
1049 const HChar* cacheRes(CacheModelResult r)
1065     CacheModelResult IrRes;
1089     CacheModelResult Ir1Res, Ir2Res;
1122     CacheModelResult Ir1Res, Ir2Res, Ir3Res;
1162     CacheModelResult IrRes, DrRes;
1198     CacheModelResult DrRes;
1225     CacheModelResult IrRes, DwRes;
1258     CacheModelResult DwRes;