Searched defs:DestReg (Results 1 - 25 of 52) sorted by relevance

123

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DAMDGPUInstrInfo.cpp134 unsigned DestReg, int FrameIndex,
132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DR600InstrInfo.cpp51 unsigned DestReg, unsigned SrcReg,
54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
63 .addReg(DestReg, RegState::Define | RegState::Implicit);
68 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DAMDGPUInstrInfo.cpp134 unsigned DestReg, int FrameIndex,
132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp42 unsigned DestReg, unsigned SrcReg,
44 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
80 unsigned DestReg, int FI,
84 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
85 isARMLowRegister(DestReg))) && "Unknown regclass!");
88 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
89 isARMLowRegister(DestReg))) {
100 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
40 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
79 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx,
50 .addReg(DestReg, getDefRegState(true), SubIdx)
35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DThumb2InstrInfo.cpp115 unsigned DestReg, unsigned SrcReg,
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
170 unsigned DestReg, int FI,
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
204 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
113 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
169 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
212 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
[all...]
H A DThumb1RegisterInfo.cpp65 unsigned DestReg, unsigned SubIdx,
77 .addReg(DestReg, getDefRegState(true), SubIdx)
91 unsigned DestReg, unsigned BaseReg,
97 bool isHigh = !isARMLowRegister(DestReg) ||
108 unsigned LdReg = DestReg;
109 if (DestReg == ARM::SP) {
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
132 if (DestReg == ARM::SP || isSub)
168 unsigned DestReg, unsigned BaseReg,
184 if (DestReg
62 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
88 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
165 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
299 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp89 int DestReg = MI->getOperand(0).getReg(); local
93 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
95 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
102 int DestReg = MI->getOperand(0).getReg(); local
106 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
108 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
115 int DestReg = MI->getOperand(0).getReg(); local
119 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
121 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
128 int DestReg local
139 int DestReg = MI->getOperand(0).getReg(); local
[all...]
H A DHexagonSplitTFRCondSets.cpp98 int DestReg = MI->getOperand(0).getReg(); local
114 if (DestReg != SrcReg1) {
116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
118 if (DestReg != SrcReg2) {
120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
128 int DestReg = MI->getOperand(0).getReg(); local
133 if (DestReg != SrcReg1) {
135 TII->get(Hexagon::TFR_cPt), DestReg).
140 TII->get(Hexagon::TFRI_cNotPt), DestReg).
145 TII->get(Hexagon::TFRI_cNotPt_f), DestReg)
156 int DestReg = MI->getOperand(0).getReg(); local
184 int DestReg = MI->getOperand(0).getReg(); local
[all...]
H A DHexagonCopyToCombine.cpp93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
121 unsigned DestReg = MI->getOperand(0).getReg(); local
123 return Hexagon::IntRegsRegClass.contains(DestReg) &&
131 unsigned DestReg = MI->getOperand(0).getReg(); local
134 return Hexagon::IntRegsRegClass.contains(DestReg) &&
149 unsigned DestReg = MI->getOperand(0).getReg(); local
150 return Hexagon::IntRegsRegClass.contains(DestReg);
221 isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg, unsigned DestReg, const TargetRegisterInfo *TRI) argument
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp67 unsigned DestReg, int FrameIdx,
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
93 unsigned DestReg, unsigned SrcReg,
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
65 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
91 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp37 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
49 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
52 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
55 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
58 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
61 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
69 unsigned &DestReg) const {
84 DestReg
35 copyPhysReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp190 unsigned DestReg = MI.getOperand(0).getReg(); local
191 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
192 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
H A DSparcInstrInfo.cpp283 unsigned DestReg, unsigned SrcReg,
295 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
296 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
298 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
299 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
301 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
303 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
311 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
314 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
338 unsigned Dst = TRI->getSubReg(DestReg, subRegId
281 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
389 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
/external/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp150 unsigned DestReg,
155 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
148 rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &tri, bool Late) argument
H A DPHIElimination.cpp231 unsigned DestReg = MPhi->getOperand(0).getReg(); local
248 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
260 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
264 TII->get(TargetOpcode::COPY), DestReg)
302 LV->addVirtualRegisterDead(DestReg, PHICopy);
303 LV->removeVirtualRegisterDead(DestReg, MPhi);
326 LiveInterval &DestLI = LIS->getInterval(DestReg);
341 // instruction from DestReg's live interval.
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local
117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
118 VRBase = DestReg;
120 } else if (DestReg != SrcReg)
473 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
474 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
475 VRBase = DestReg;
892 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
893 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
897 DestReg)
[all...]
H A DFunctionLoweringInfo.cpp322 unsigned DestReg = ValueMap[PN]; local
323 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
325 LiveOutRegInfo.grow(DestReg);
326 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
/external/llvm/lib/Target/R600/
H A DR600InstrInfo.cpp51 unsigned DestReg, unsigned SrcReg,
54 if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
55 AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
59 } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
60 AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
70 RI.getSubReg(DestReg, SubRegIndex),
72 .addReg(DestReg,
77 DestReg, SrcReg);
49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DR600MachineScheduler.cpp273 unsigned DestReg = MI->getOperand(0).getReg(); local
274 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
275 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
277 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
279 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
281 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
283 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
362 unsigned DestReg = MI->getOperand(DstIndex).getReg(); local
369 MO.getReg() == DestReg)
372 // Constrains the regclass of DestReg t
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp343 unsigned DestReg, unsigned SrcReg,
345 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
349 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
356 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
360 if (DestReg == XCore::SP && GRSrc) {
394 unsigned DestReg, int FrameIndex,
408 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
341 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
392 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp595 unsigned DestReg = local
599 .addReg(DestReg, RegState::Define | RegState::Dead)
H A DAArch64LoadStoreOptimizer.cpp646 unsigned DestReg = MemMI->getOperand(0).getReg(); local
653 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
701 unsigned DestReg = MemMI->getOperand(0).getReg(); local
712 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))

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