Searched defs:FirstReg (Results 1 - 5 of 5) sorted by relevance
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 265 unsigned FirstReg = 0; local 273 if (!FirstReg) FirstReg = R; 276 return FirstReg;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 667 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, local 673 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || 674 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { 676 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? 678 unsigned OldFirstReg = FirstReg; 679 FirstReg = MRI.createVirtualRegister(FirstRC); 680 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) 685 .addReg(FirstReg).addReg(SecondReg)
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 1163 unsigned FirstReg = FirstRegs[NumRegs - 1]; local 1166 MCOperand::CreateReg(FirstReg + getVectorListStart() - AArch64::Q0)); 1174 unsigned FirstReg = FirstRegs[NumRegs - 1]; local 1177 MCOperand::CreateReg(FirstReg + getVectorListStart() - AArch64::Q0)); 2832 int64_t FirstReg = tryMatchVectorRegister(Kind, true); local 2833 if (FirstReg == -1) 2835 int64_t PrevReg = FirstReg; 2894 FirstReg, Count, NumElements, ElementKind, S, getLoc(), getContext()));
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 1923 unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); local 1944 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 3541 unsigned FirstReg = Reg; local 3545 FirstReg = Reg = getDRegFromQReg(Reg); 3687 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3690 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3700 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3702 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3707 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
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