/external/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 3043 SmallVector<int, 16> Mask(SVI->getShuffleMask()); 3045 for (unsigned i = 0; i < Mask.size(); ++i) { 3046 if (SplatElem != -1 && Mask[i] != -1 && Mask[i] != SplatElem) 3048 SplatElem = Mask[i]; 3288 ConstantInt* Mask = dyn_cast<ConstantInt>(And->getOperand(1)); local 3289 if (!Mask || !Mask->getUniqueInteger().isPowerOf2())
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 519 SDValue Mask = N->getOperand(0); local 523 Mask = PromoteTargetBoolean(Mask, OpTy); 527 LHS.getValueType(), Mask, LHS, RHS); 1437 // Mask out the high bit, which we know is set.
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H A D | TargetLowering.cpp | 380 "Mask size mismatches value type size!"); 1085 /// in Mask are known to be either zero or one and return them in the 1342 const APInt &Mask = local 1347 if ((newMask & Mask) == Mask) { 1352 bestMask = Mask.lshr(offset * (width/8) * 8);
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H A D | LegalizeVectorTypes.cpp | 1248 SDValue Mask = N->getOperand(0); local 1253 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?"); 1267 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
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/external/llvm/lib/IR/ |
H A D | Constants.cpp | 2023 Constant *Mask) { 2024 assert(ShuffleVectorInst::isValidOperands(V1, V2, Mask) && 2027 if (Constant *FC = ConstantFoldShuffleVectorInstruction(V1, V2, Mask)) 2030 unsigned NElts = Mask->getType()->getVectorNumElements(); 2035 Constant *ArgVec[] = { V1, V2, Mask }; 2022 getShuffleVector(Constant *V1, Constant *V2, Constant *Mask) argument
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H A D | Instructions.cpp | 1541 ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, argument 1545 cast<VectorType>(Mask->getType())->getNumElements()), 1550 assert(isValidOperands(V1, V2, Mask) && 1554 Op<2>() = Mask; 1558 ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, argument 1562 cast<VectorType>(Mask->getType())->getNumElements()), 1567 assert(isValidOperands(V1, V2, Mask) && 1572 Op<2>() = Mask; 1577 const Value *Mask) { 1582 // Mask mus 1576 isValidOperands(const Value *V1, const Value *V2, const Value *Mask) argument 1627 getMaskValue(Constant *Mask, unsigned i) argument 1639 getShuffleMask(Constant *Mask, SmallVectorImpl<int> &Result) argument [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 63 // instructions that for the IT block. Firstcond and Mask correspond to the 65 void setITState(char Firstcond, char Mask) { argument 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 740 unsigned Mask = MI.getOperand(1).getImm(); local 741 ITBlock.setITState(Firstcond, Mask);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 560 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); local 562 if (!Mask) 565 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); 568 return SDValue(); // Mask+1 is not a power of 2 683 APInt Mask, InvMask; local 689 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) { 694 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 697 Mask.getBitWidth() == InvMask.getBitWidth() && Mask 1575 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), local 1588 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), local [all...] |
H A D | MipsISelLowering.cpp | 626 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 642 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 1090 unsigned Mask = RegInfo.createVirtualRegister(RC); local 1153 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1155 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1186 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1191 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1194 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1213 .addReg(OldVal).addReg(Mask); 1323 unsigned Mask local 2368 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); local [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2786 SDValue Mask = N->getOperand(1); local 2789 std::swap(Val, Mask); 2805 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 1061 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32); local 1070 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg 1240 unsigned Mask = 0; local 1242 Mask = 0xff; 1244 Mask = 0xffff; 1266 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 919 const uint32_t *Mask = ((hasReturnsTwice) local 922 assert(Mask && "Missing call preserved mask for calling convention"); 923 Ops.push_back(DAG.getRegisterMask(Mask)); 1232 const uint32_t *Mask = ((hasReturnsTwice) local 1235 assert(Mask && "Missing call preserved mask for calling convention"); 1236 Ops.push_back(DAG.getRegisterMask(Mask)); 1708 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 1907 const uint32_t *Mask = getTargetMachine() local 1909 assert(Mask && "Missing call preserved mask for calling convention"); 1910 Ops.push_back(DAG.getRegisterMask(Mask)); 2103 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType()); local 2136 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); local 2143 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); local [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 2350 unsigned Mask = 1; local 2352 if (ErrorInfo & Mask) { 2354 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 2356 Mask <<= 1; 2497 unsigned Mask = 1; local 2499 if (ErrorInfoMissingFeature & Mask) { 2501 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask); 2503 Mask <<= 1;
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 782 uint64_t Mask, 792 Mask != (0xffu << ScaleLog)) 825 uint64_t Mask, 845 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT); 892 uint64_t Mask, 900 unsigned MaskLZ = countLeadingZeros(Mask); 901 unsigned MaskTZ = countTrailingZeros(Mask); 912 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true; 1079 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1); local 1083 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, 781 FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 824 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 891 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 1260 uint64_t Mask = N.getConstantOperandVal(1); local [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCompares.cpp | 1038 Constant *Mask = Builder->getInt(Val); local 1041 Mask, Shr->getName()+".mask"); 1466 Constant *Mask = Builder->getInt(APInt::getLowBitsSet(TypeBits, local 1470 Builder->CreateAnd(LHSI->getOperand(0),Mask, LHSI->getName()+".mask"); 1490 Constant *Mask = ConstantInt::get(LHSI->getOperand(0)->getType(), local 1494 Builder->CreateAnd(LHSI->getOperand(0), Mask, LHSI->getName()+".mask"); 3071 // a * Cst icmp eq/ne b * Cst --> a & Mask icmp b & Mask 3072 // Mask = -1 >> count-trailing-zeros(Cst). 3075 ConstantInt *Mask local 3270 Value *Mask = Builder->CreateAnd(A, Builder->getInt(MaskV)); local [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | SROA.cpp | 1896 APInt Mask = ~Ty->getMask().zext(IntTy->getBitWidth()).shl(ShAmt); local 1897 Old = IRB.CreateAnd(Old, Mask, Name + ".mask"); 1922 SmallVector<Constant*, 8> Mask; local 1923 Mask.reserve(NumElements); 1925 Mask.push_back(IRB.getInt32(i)); 1927 ConstantVector::get(Mask), 1959 SmallVector<Constant*, 8> Mask; local 1960 Mask.reserve(VecTy->getNumElements()); 1963 Mask.push_back(IRB.getInt32(i - BeginIndex)); 1965 Mask [all...] |
/external/llvm/lib/Transforms/Vectorize/ |
H A D | BBVectorize.cpp | 351 std::vector<Constant*> &Mask); 2320 std::vector<Constant*> &Mask) { 2325 Mask[v+MaskOffset] = UndefValue::get(Type::getInt32Ty(Context)); 2331 Mask[v+MaskOffset] = 2354 std::vector<Constant*> Mask(NumElem); 2371 0, Mask); 2375 NumInElemI, Mask); 2377 return ConstantVector::get(Mask); 2573 std::vector<Constant *> Mask(numElem); 2577 Mask[ 2317 fillNewShuffleMask(LLVMContext& Context, Instruction *J, unsigned MaskOffset, unsigned NumInElem, unsigned NumInElem1, unsigned IdxOffset, std::vector<Constant*> &Mask) argument [all...] |
/external/chromium_org/v8/src/ |
H A D | hydrogen-instructions.cc | 179 int32_t Range::Mask() const { function in class:v8::internal::Range 3107 ? left()->range()->Mask() 3110 ? right()->range()->Mask()
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/external/clang/lib/CodeGen/ |
H A D | CGExpr.cpp | 1092 llvm::Constant *Mask[] = { local 1098 llvm::Value *MaskV = llvm::ConstantVector::get(Mask); 1196 SmallVector<llvm::Constant*, 4> Mask; local 1197 Mask.push_back(llvm::ConstantInt::get(llvm::Type::getInt32Ty(VMContext), 1199 Mask.push_back(llvm::ConstantInt::get(llvm::Type::getInt32Ty(VMContext), 1201 Mask.push_back(llvm::ConstantInt::get(llvm::Type::getInt32Ty(VMContext), 1203 Mask.push_back(llvm::UndefValue::get(llvm::Type::getInt32Ty(VMContext))); 1205 llvm::Value *MaskV = llvm::ConstantVector::get(Mask); 1346 SmallVector<llvm::Constant*, 4> Mask; local 1348 Mask 1586 SmallVector<llvm::Constant*, 4> Mask; local [all...] |
H A D | CGExprScalar.cpp | 898 // Vector Mask Case 903 Value *Mask; local 909 Mask = CGF.EmitScalarExpr(E->getExpr(2)); 922 Mask = RHS; 925 llvm::VectorType *MTy = cast<llvm::VectorType>(Mask->getType()); 931 // Mask off the high bits of each shuffle index. 934 Mask = Builder.CreateAnd(Mask, MaskBits, "mask"); 947 Value *Indx = Builder.CreateExtractElement(Mask, IIndx, "shuf_idx"); 1158 llvm::Constant *Mask local 1211 llvm::Constant *Mask = llvm::ConstantVector::get(Args); local 1227 llvm::Constant *Mask = llvm::ConstantVector::get(Args); local 3262 llvm::Constant *Mask = llvm::ConstantVector::get(Args); local [all...] |
H A D | TargetInfo.cpp | 1073 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -Align); local 1074 Addr = CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 2522 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align); 2524 CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 3810 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, ~(Align - 1)); local 3811 llvm::Value *Aligned = Builder.CreateAnd(AsInt, Mask); 5386 llvm::Value *Mask = llvm::ConstantInt::get(IntTy, -TypeAlign); local 5388 llvm::Value *And = CGF.Builder.CreateAnd(Add, Mask);
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/external/clang/lib/Sema/ |
H A D | SemaType.cpp | 2002 unsigned Mask; member in struct:Qual 2019 if (Quals & QualKinds[I].Mask) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 1300 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and 1302 const int *Mask; member in class:llvm::ShuffleVectorSDNode 1307 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) { 1314 return makeArrayRef(Mask, VT.getVectorNumElements()); 1318 return Mask[Idx]; 1321 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); } 1326 if (Mask[i] >= 0) 1327 return Mask[i]; 1331 static bool isSplatMask(const int *Mask, EVT VT);
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 3829 unsigned Mask = 1; local 3831 if (ErrorInfo & Mask) { 3833 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 3835 Mask <<= 1;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 2101 unsigned Mask = (1 << NumBits) - 1; local 2102 if ((unsigned)Offset <= Mask * Scale) { 2120 ImmedOffset = ImmedOffset & Mask; 2128 Offset &= ~(Mask*Scale);
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