/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinterDwarf.cpp | 294 unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8; local 297 SmallBitVector Coverage(RegSize, false); 306 SmallBitVector Intersection(RegSize, false);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64LoadStoreOptimizer.cpp | 704 unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize(); local 732 if (isMatchingUpdateInsn(MI, BaseReg, RegSize))
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 61 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize); 63 unsigned MFLoOpc, unsigned RegSize); 164 unsigned RegSize) { 177 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); 188 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); 194 unsigned RegSize) { 207 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); 217 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); 163 expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize) argument 192 expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, unsigned MFLoOpc, unsigned RegSize) argument
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H A D | MipsISelLowering.cpp | 3449 unsigned RegSize = regSize(); local 3450 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3451 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3452 RegSize * 2); 3458 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3497 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); local 3499 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3501 "RegSize."); 3505 // If Align > RegSize, th 3679 unsigned RegSize = CC.regSize(); local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 709 unsigned RegSize = RegisterVT.getSizeInBits(); local 713 if (NumZeroBits == RegSize) { 725 if (NumSignBits == RegSize) 727 else if (NumZeroBits >= RegSize-1) 729 else if (NumSignBits > RegSize-8) 731 else if (NumZeroBits >= RegSize-8) 733 else if (NumSignBits > RegSize-16) 735 else if (NumZeroBits >= RegSize-16) 737 else if (NumSignBits > RegSize-32) 739 else if (NumZeroBits >= RegSize [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes member in class:llvm::MCRegisterClass 86 unsigned getSize() const { return RegSize; }
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 632 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} 634 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} 636 operator bool() const { return RegSize; } 638 unsigned RegSize, ImmLSB, ImmSize; member in struct:__anon25318::LogicOp 722 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); 724 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { 726 if (And.RegSize == 64)
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/external/clang/lib/CodeGen/ |
H A D | TargetInfo.cpp | 3551 int RegSize; local 3558 RegSize = 8 * AllocatedGPR; 3565 RegSize = 16 * AllocatedVFP; 3603 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
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