Searched defs:SrcReg1 (Results 1 - 6 of 6) sorted by relevance
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitTFRCondSets.cpp | 99 int SrcReg1 = MI->getOperand(2).getReg(); local 114 if (DestReg != SrcReg1) { 116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 129 int SrcReg1 = MI->getOperand(2).getReg(); local 133 if (DestReg != SrcReg1) { 136 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 185 int SrcReg1 = MI->getOperand(1).getReg(); local 192 DestReg).addReg(SrcReg1).addImm(Immed1); 195 DestReg).addReg(SrcReg1).addImm(Immed2); 199 addReg(SrcReg1) [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
H A D | radeon_program_alu.c | 63 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) 74 fpi->U.I.SrcReg[1] = SrcReg1; 82 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, 94 fpi->U.I.SrcReg[1] = SrcReg1; 59 emit2( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) argument 78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_program_alu.c | 63 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) 74 fpi->U.I.SrcReg[1] = SrcReg1; 82 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, 94 fpi->U.I.SrcReg[1] = SrcReg1; 59 emit2( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) argument 78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 948 unsigned SrcReg1 = getRegForValue(Src1Value); local 949 if (SrcReg1 == 0) 961 SrcReg1 = EmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); 962 if (SrcReg1 == 0) 975 .addReg(SrcReg1) 981 .addReg(SrcReg1) 986 .addReg(SrcReg1); 989 .addReg(SrcReg1)
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 792 unsigned SrcReg1 = getRegForValue(SrcValue1); local 793 if (SrcReg1 == 0) 805 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) 807 SrcReg1 = ExtReg; 819 .addReg(SrcReg1).addReg(SrcReg2); 822 .addReg(SrcReg1).addImm(Imm); 1121 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); local 1122 if (SrcReg1 == 0) return false; 1135 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); 1139 MRI.setRegClass(SrcReg1, [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1435 unsigned SrcReg1 = getRegForValue(Src1Value); local 1436 if (SrcReg1 == 0) return false; 1446 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); 1447 if (SrcReg1 == 0) return false; 1455 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); 1459 .addReg(SrcReg1).addReg(SrcReg2)); 1463 .addReg(SrcReg1); 1772 unsigned SrcReg1 local [all...] |
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