/external/llvm/lib/Target/R600/ |
H A D | AMDGPUTargetTransformInfo.cpp | 40 const AMDGPUTargetMachine *TM; member in class:__anon25265::final 49 AMDGPUTTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) { 53 AMDGPUTTI(const AMDGPUTargetMachine *TM) argument 54 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()), 55 TLI(TM->getTargetLowering()) { 90 llvm::createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM) { argument 91 return new AMDGPUTTI(TM);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcSubtarget.cpp | 79 const std::string &FS, TargetMachine &TM, 83 InstrInfo(*this), TLInfo(TM), TSInfo(DL), FrameLowering(*this) {} 78 SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool is64Bit) argument
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H A D | SparcTargetMachine.cpp | 43 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) argument 44 : TargetPassConfig(TM, PM) {}
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZShortenInst.cpp | 51 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) { argument 52 return new SystemZShortenInst(TM);
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H A D | SystemZTargetMachine.cpp | 36 SystemZPassConfig(SystemZTargetMachine *TM, PassManagerBase &PM) argument 37 : TargetPassConfig(TM, PM) {}
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreTargetObjectFile.cpp | 21 void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ argument 22 TargetLoweringObjectFileELF::Initialize(Ctx, TM); 124 const TargetMachine &TM) const { 136 const TargetMachine &TM) const{ 148 if (TM.getCodeModel() == CodeModel::Small || 150 TM.getDataLayout()->getTypeAllocSize(ObjType) < CodeModelLargeSize) {
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H A D | XCoreISelLowering.h | 97 explicit XCoreTargetLowering(const TargetMachine &TM); 126 const TargetMachine &TM; member in class:llvm::XCoreTargetLowering
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H A D | XCoreTargetMachine.cpp | 37 XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM) argument 38 : TargetPassConfig(TM, PM) {}
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.h | 35 AMDGPUTargetMachine &TM; member in class:llvm::R600InstrInfo 63 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
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H A D | AMDGPUTargetMachine.cpp | 75 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM) argument 76 : TargetPassConfig(TM, PM) {} 98 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); 107 PM->add(createAMDGPUPeepholeOpt(*TM)); 113 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); 116 PM->add(createSIAssignInterpRegsPass(*TM)); 118 PM->add(createAMDGPUConvertToISAPass(*TM)); 133 PM->add(createAMDGPUCFGPreparationPass(*TM)); 134 PM->add(createAMDGPUCFGStructurizerPass(*TM)); 136 const AMDGPUSubtarget &ST = TM [all...] |
H A D | R600ExpandSpecialInstrs.cpp | 47 FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) { argument 48 return new R600ExpandSpecialInstrsPass(TM);
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H A D | SIAssignInterpRegs.cpp | 36 TargetMachine &TM; member in class:__anon26489::SIAssignInterpRegsPass 43 MachineFunctionPass(ID), TM(tm) { } 126 const TargetInstrInfo * TII = TM.getInstrInfo();
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUTargetMachine.cpp | 75 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM) argument 76 : TargetPassConfig(TM, PM) {} 98 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); 107 PM->add(createAMDGPUPeepholeOpt(*TM)); 113 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); 116 PM->add(createSIAssignInterpRegsPass(*TM)); 118 PM->add(createAMDGPUConvertToISAPass(*TM)); 133 PM->add(createAMDGPUCFGPreparationPass(*TM)); 134 PM->add(createAMDGPUCFGStructurizerPass(*TM)); 136 const AMDGPUSubtarget &ST = TM [all...] |
H A D | R600ExpandSpecialInstrs.cpp | 47 FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) { argument 48 return new R600ExpandSpecialInstrsPass(TM);
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H A D | SIAssignInterpRegs.cpp | 36 TargetMachine &TM; member in class:__anon12916::SIAssignInterpRegsPass 43 MachineFunctionPass(ID), TM(tm) { } 126 const TargetInstrInfo * TII = TM.getInstrInfo();
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/external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
H A D | SkPdfFieldDictionary_autogen.cpp | 71 SkString SkPdfFieldDictionary::TM(SkPdfNativeDoc* doc) { function in class:SkPdfFieldDictionary 72 SkPdfNativeObject* ret = get("TM", ""); 80 return get("TM", "") != NULL;
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineConstantPool.h | 135 const TargetMachine &TM; ///< The target machine. member in class:llvm::MachineConstantPool 144 explicit MachineConstantPool(const TargetMachine &TM) argument 145 : TM(TM), PoolAlignment(1) {}
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/external/llvm/include/llvm/ |
H A D | PassSupport.h | 88 template <typename PassName> Pass *callTargetMachineCtor(TargetMachine *TM) { argument 89 return new PassName(TM);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMInstrInfo.cpp | 105 const ARMTargetMachine *TM = variable 107 if (TM->getRelocationModel() != Reloc::PIC_) 112 unsigned PCAdj = TM->getSubtarget<ARMSubtarget>().isThumb() ? 4 : 8; 116 unsigned Align = TM->getDataLayout() 125 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? 127 const TargetInstrInfo &TII = *TM->getInstrInfo(); 137 Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 57 HexagonExpandPredSpillCode(const HexagonTargetMachine& TM) : argument 58 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) { 199 llvm::createHexagonExpandPredSpillCode(const HexagonTargetMachine &TM) { argument 200 return new HexagonExpandPredSpillCode(TM);
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H A D | HexagonSplitConst32AndConst64.cpp | 55 HexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) argument 56 : MachineFunctionPass(ID), QTM(TM) {} 178 llvm::createHexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) { argument 179 return new HexagonSplitConst32AndConst64(TM);
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H A D | HexagonSplitTFRCondSets.cpp | 66 HexagonSplitTFRCondSets(const HexagonTargetMachine& TM) : argument 67 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) { 235 llvm::createHexagonSplitTFRCondSets(const HexagonTargetMachine &TM) { argument 236 return new HexagonSplitTFRCondSets(TM);
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H A D | HexagonTargetMachine.cpp | 81 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) argument 82 : TargetPassConfig(TM, PM) { 115 HexagonTargetMachine &TM = getHexagonTargetMachine(); local 119 addPass(createHexagonRemoveExtendArgs(TM)); 121 addPass(createHexagonISelDag(TM, getOptLevel())); 139 const HexagonTargetMachine &TM = getHexagonTargetMachine(); local 142 addPass(createHexagonCFGOptimizer(TM)); 147 const HexagonTargetMachine &TM = getHexagonTargetMachine(); local 152 addPass(createHexagonSplitConst32AndConst64(TM)); 158 const HexagonTargetMachine &TM local [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 42 MSP430AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 43 : AsmPrinter(TM, Streamer) {}
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetObjectFile.cpp | 24 const TargetMachine &TM, MachineModuleInfo *MMI, 30 const MCSymbol *Sym = TM.getSymbol(GV, Mang); 38 GV, Encoding, Mang, TM, MMI, Streamer); 42 const GlobalValue *GV, Mangler &Mang, const TargetMachine &TM, 44 return TM.getSymbol(GV, Mang); 48 X86LinuxTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { argument 49 TargetLoweringObjectFileELF::Initialize(Ctx, TM); 50 InitializeELF(TM.Options.UseInitArray); 60 const ConstantExpr *CE, Mangler &Mang, const TargetMachine &TM) const { 105 return MCSymbolRefExpr::Create(TM 22 getTTypeGlobalReference( const GlobalValue *GV, unsigned Encoding, Mangler &Mang, const TargetMachine &TM, MachineModuleInfo *MMI, MCStreamer &Streamer) const argument 41 getCFIPersonalitySymbol( const GlobalValue *GV, Mangler &Mang, const TargetMachine &TM, MachineModuleInfo *MMI) const argument [all...] |