/external/chromium_org/v8/src/x64/ |
H A D | codegen-x64.h | 57 Register base_reg, 62 : base_reg_(base_reg), 70 Register base_reg, 75 : base_reg_(base_reg), 83 Register base_reg, 88 : base_reg_(base_reg), 56 StackArgumentsAccessor( Register base_reg, int argument_count_immediate, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument 69 StackArgumentsAccessor( Register base_reg, Register argument_count_reg, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument 82 StackArgumentsAccessor( Register base_reg, const ParameterCount& parameter_count, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument
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H A D | disasm-x64.cc | 340 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64 1420 NameOfCPURegister(base_reg(current & 0x07))); 1426 NameOfCPURegister(base_reg(current & 0x07))); 1450 NameOfCPURegister(base_reg(current & 0x07)),
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H A D | macro-assembler-x64.cc | 738 Register base_reg = r15; local 739 Move(base_reg, next_address); 740 movp(prev_next_address_reg, Operand(base_reg, kNextOffset)); 741 movp(prev_limit_reg, Operand(base_reg, kLimitOffset)); 742 addl(Operand(base_reg, kLevelOffset), Immediate(1)); 789 subl(Operand(base_reg, kLevelOffset), Immediate(1)); 790 movp(Operand(base_reg, kNextOffset), prev_next_address_reg); 791 cmpp(prev_limit_reg, Operand(base_reg, kLimitOffset)); 852 movp(Operand(base_reg, kLimitOffset), prev_limit_reg);
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 423 uint32_t base_reg; local 435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; 436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; 438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; 444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 423 uint32_t base_reg; local 435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; 436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; 438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; 444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
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/external/chromium_org/third_party/mesa/src/src/mesa/program/ |
H A D | register_allocate.c | 210 * Adds a conflict between base_reg and reg, and also between reg and 211 * anything that base_reg conflicts with. 219 unsigned int base_reg, unsigned int reg) 223 ra_add_reg_conflict(regs, reg, base_reg); 225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) { 226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]); 218 ra_add_transitive_reg_conflict(struct ra_regs *regs, unsigned int base_reg, unsigned int reg) argument
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/external/mesa3d/src/mesa/program/ |
H A D | register_allocate.c | 210 * Adds a conflict between base_reg and reg, and also between reg and 211 * anything that base_reg conflicts with. 219 unsigned int base_reg, unsigned int reg) 223 ra_add_reg_conflict(regs, reg, base_reg); 225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) { 226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]); 218 ra_add_transitive_reg_conflict(struct ra_regs *regs, unsigned int base_reg, unsigned int reg) argument
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/external/lldb/include/lldb/Core/ |
H A D | EmulateInstruction.h | 190 RegisterInfo base_reg; // base register number member in struct:lldb_private::EmulateInstruction::Context::__anon24389::RegisterPlusIndirectOffset 197 RegisterInfo base_reg; // base register for address calculation member in struct:lldb_private::EmulateInstruction::Context::__anon24389::RegisterToRegisterPlusOffset 203 RegisterInfo base_reg; // base register for address calculation member in struct:lldb_private::EmulateInstruction::Context::__anon24389::RegisterToRegisterPlusIndirectOffset 246 SetRegisterPlusOffset (RegisterInfo base_reg, argument 250 info.RegisterPlusOffset.reg = base_reg; 255 SetRegisterPlusIndirectOffset (RegisterInfo base_reg, argument 259 info.RegisterPlusIndirectOffset.base_reg = base_reg; 265 RegisterInfo base_reg, 270 info.RegisterToRegisterPlusOffset.base_reg 264 SetRegisterToRegisterPlusOffset(RegisterInfo data_reg, RegisterInfo base_reg, int64_t offset) argument 275 SetRegisterToRegisterPlusIndirectOffset(RegisterInfo base_reg, RegisterInfo offset_reg, RegisterInfo data_reg) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_emit.c | 1323 GLuint base_reg, 1343 brw_message_reg(base_reg + 1), 1357 base_reg, 1322 fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, GLuint target, GLuint eot ) argument
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H A D | brw_blorp_blit.cpp | 493 void alloc_push_const_regs(int base_reg); 743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) argument 748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_emit.c | 1323 GLuint base_reg, 1343 brw_message_reg(base_reg + 1), 1357 base_reg, 1322 fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, GLuint target, GLuint eot ) argument
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H A D | brw_blorp_blit.cpp | 493 void alloc_push_const_regs(int base_reg); 743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) argument 748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
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/external/qemu/ |
H A D | gdbstub.c | 260 int base_reg; member in struct:GDBRegisterState 1393 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { 1394 return r->get_reg(env, mem_buf, reg - r->base_reg); 1409 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { 1410 return r->set_reg(env, mem_buf, reg - r->base_reg); 1431 s->base_reg = last_reg; 1447 if (g_pos != s->base_reg) { 1449 "Expected %d got %d\n", xml, g_pos, s->base_reg); [all...] |
/external/lldb/source/Plugins/Instruction/ARM/ |
H A D | EmulateInstructionARM.cpp | 3964 RegisterInfo base_reg; local 3965 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg); 3970 ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base)); 3979 context.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base)); 4097 RegisterInfo base_reg; local 4098 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg); 4122 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); 4222 RegisterInfo base_reg; local 4223 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg); 4247 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, R 4373 RegisterInfo base_reg; local 4498 RegisterInfo base_reg; local 4687 RegisterInfo base_reg; local 4887 RegisterInfo base_reg; local 5017 RegisterInfo base_reg; local 5185 RegisterInfo base_reg; local 5200 RegisterInfo base_reg; local 5855 RegisterInfo base_reg; local 6062 RegisterInfo base_reg; local 6235 RegisterInfo base_reg; local 6473 RegisterInfo base_reg; local 6611 RegisterInfo base_reg; local 6725 RegisterInfo base_reg; local 6892 RegisterInfo base_reg; local 7053 RegisterInfo base_reg; local 7152 RegisterInfo base_reg; local 7299 RegisterInfo base_reg; local 7450 RegisterInfo base_reg; local 7564 RegisterInfo base_reg; local 7728 RegisterInfo base_reg; local 8207 RegisterInfo base_reg; local 9822 RegisterInfo base_reg; local 10022 RegisterInfo base_reg; local 10170 RegisterInfo base_reg; local 10422 RegisterInfo base_reg; local 10551 RegisterInfo base_reg; local 10720 RegisterInfo base_reg; local 10913 RegisterInfo base_reg; local 11067 RegisterInfo base_reg; local 11205 RegisterInfo base_reg; local 11376 RegisterInfo base_reg; local 11548 RegisterInfo base_reg; local 11715 RegisterInfo base_reg; local 11887 RegisterInfo base_reg; local 12013 RegisterInfo base_reg; local [all...] |