Searched defs:dst (Results 1 - 21 of 21) sorted by relevance

/art/runtime/base/unix_file/
H A Drandom_access_file_utils_test.cc28 StringFile dst; local
33 ASSERT_EQ(dst.ToStringPiece(), "");
35 ASSERT_TRUE(CopyFile(src, &dst));
36 ASSERT_EQ(src.ToStringPiece(), dst.ToStringPiece());
41 StringFile dst; local
42 ASSERT_FALSE(CopyFile(src, &dst));
47 FdFile dst(-1);
53 ASSERT_FALSE(CopyFile(src, &dst));
H A Drandom_access_file_utils.cc23 bool CopyFile(const RandomAccessFile& src, RandomAccessFile* dst) { argument
30 if (dst->Write(&buf[0], n, offset) != n) {
/art/runtime/
H A Dreflection-inl.h32 const JValue& src, JValue* dst) {
35 dst->SetJ(src.GetJ());
46 dst->SetS(src.GetI());
53 dst->SetI(src.GetI());
60 dst->SetJ(src.GetI());
67 dst->SetF(src.GetI());
70 dst->SetF(src.GetJ());
77 dst->SetD(src.GetI());
80 dst->SetD(src.GetJ());
83 dst
30 ConvertPrimitiveValue(const ThrowLocation* throw_location, bool unbox_for_result, Primitive::Type srcType, Primitive::Type dstType, const JValue& src, JValue* dst) argument
[all...]
H A Dmonitor_android.cc37 static char* EventLogWriteInt(char* dst, int value) { argument
38 *dst++ = EVENT_TYPE_INT;
39 Set4LE(reinterpret_cast<uint8_t*>(dst), value);
40 return dst + 4;
43 static char* EventLogWriteString(char* dst, const char* value, size_t len) { argument
44 *dst++ = EVENT_TYPE_STRING;
46 Set4LE(reinterpret_cast<uint8_t*>(dst), len);
47 dst += 4;
48 memcpy(dst, value, len);
49 return dst
[all...]
H A Dclass_linker.cc2836 Handle<mirror::Class> klass, Handle<mirror::ArtField> dst) {
2838 dst->SetDexFieldIndex(field_idx);
2839 dst->SetDeclaringClass(klass.Get());
2840 dst->SetAccessFlags(it.GetFieldAccessFlags());
2850 mirror::ArtMethod* dst = AllocArtMethod(self); local
2851 if (UNLIKELY(dst == nullptr)) {
2855 DCHECK(dst->IsArtMethod()) << PrettyDescriptor(dst->GetClass());
2858 dst->SetDexMethodIndex(dex_method_idx);
2859 dst
2835 LoadField(const DexFile& , const ClassDataItemIterator& it, Handle<mirror::Class> klass, Handle<mirror::ArtField> dst) argument
[all...]
H A Ddebugger.cc1308 uint8_t* dst = expandBufAddSpace(pReply, count * width); local
1311 for (int i = 0; i < count; ++i) JDWP::Write8BE(&dst, src8[offset + i]);
1314 for (int i = 0; i < count; ++i) JDWP::Write4BE(&dst, src4[offset + i]);
1317 for (int i = 0; i < count; ++i) JDWP::Write2BE(&dst, src2[offset + i]);
1320 memcpy(dst, &src[offset * width], count * width);
1343 T* dst = reinterpret_cast<T*>(a->GetRawData(sizeof(T), offset)); variable
1345 *dst++ = src.ReadValue(sizeof(T));
1353 mirror::Array* dst = DecodeArray(array_id, status); local
1354 if (dst == NULL) {
1358 if (offset < 0 || count < 0 || offset > dst
[all...]
/art/runtime/base/
H A Dstringprintf.cc23 void StringAppendV(std::string* dst, const char* format, va_list ap) { argument
38 dst->append(space, result);
60 dst->append(buf, result);
74 void StringAppendF(std::string* dst, const char* format, ...) { argument
77 StringAppendV(dst, format, ap);
/art/runtime/jdwp/
H A Djdwp_bits.h100 static inline void Write1BE(uint8_t** dst, uint8_t value) { argument
101 Set1(*dst, value);
102 *dst += sizeof(value);
105 static inline void Write2BE(uint8_t** dst, uint16_t value) { argument
106 Set2BE(*dst, value);
107 *dst += sizeof(value);
110 static inline void Write4BE(uint8_t** dst, uint32_t value) { argument
111 Set4BE(*dst, value);
112 *dst += sizeof(value);
115 static inline void Write8BE(uint8_t** dst, uint64_ argument
[all...]
/art/compiler/
H A Dimage_writer.h89 byte* dst = image_->Begin() + offset; local
90 return reinterpret_cast<mirror::Object*>(dst);
H A Dimage_writer.cc602 byte* dst = image_writer->image_->Begin() + offset; local
606 memcpy(dst, src, n);
607 Object* copy = reinterpret_cast<Object*>(dst);
/art/runtime/interpreter/
H A Dinterpreter_goto_table_impl.cc368 uint32_t dst = inst->VRegA_11n(inst_data); local
370 shadow_frame.SetVReg(dst, val);
372 shadow_frame.SetVRegReference(dst, NULL);
379 uint32_t dst = inst->VRegA_21s(inst_data); local
381 shadow_frame.SetVReg(dst, val);
383 shadow_frame.SetVRegReference(dst, NULL);
390 uint32_t dst = inst->VRegA_31i(inst_data); local
392 shadow_frame.SetVReg(dst, val);
394 shadow_frame.SetVRegReference(dst, NULL);
401 uint32_t dst local
[all...]
H A Dinterpreter_switch_impl.cc281 uint4_t dst = inst->VRegA_11n(inst_data); local
283 shadow_frame.SetVReg(dst, val);
285 shadow_frame.SetVRegReference(dst, NULL);
292 uint8_t dst = inst->VRegA_21s(inst_data); local
294 shadow_frame.SetVReg(dst, val);
296 shadow_frame.SetVRegReference(dst, NULL);
303 uint8_t dst = inst->VRegA_31i(inst_data); local
305 shadow_frame.SetVReg(dst, val);
307 shadow_frame.SetVRegReference(dst, NULL);
314 uint8_t dst local
[all...]
H A Dinterpreter_common.cc885 ObjectArray<Object>* dst = shadow_frame->GetVRegReference(arg_offset + 2)->AsObjectArray<Object>(); local
887 dst->Set(dstPos + i, src->Get(srcPos + i));
891 CharArray* dst = shadow_frame->GetVRegReference(arg_offset + 2)->AsCharArray(); local
893 dst->Set(dstPos + i, src->Get(srcPos + i));
897 IntArray* dst = shadow_frame->GetVRegReference(arg_offset + 2)->AsIntArray(); local
899 dst->Set(dstPos + i, src->Get(srcPos + i));
/art/compiler/utils/arm64/
H A Dassembler_arm64.cc288 Arm64ManagedRegister dst = m_dst.AsArm64(); local
289 CHECK(dst.IsCoreRegister()) << dst;
290 LoadWFromOffset(kLoadWord, dst.AsOverlappingCoreRegisterLow(), SP, offs.Int32Value());
295 Arm64ManagedRegister dst = m_dst.AsArm64(); local
297 CHECK(dst.IsCoreRegister() && base.IsCoreRegister());
298 LoadWFromOffset(kLoadWord, dst.AsOverlappingCoreRegisterLow(), base.AsCoreRegister(),
303 Arm64ManagedRegister dst = m_dst.AsArm64(); local
305 CHECK(dst.IsCoreRegister() && base.IsCoreRegister());
306 // Remove dst an
313 Arm64ManagedRegister dst = m_dst.AsArm64(); local
320 Arm64ManagedRegister dst = m_dst.AsArm64(); local
[all...]
/art/compiler/optimizing/
H A Dcode_generator_x86.cc1490 void ParallelMoveResolverX86::MoveMemoryToMemory(int dst, int src) { argument
1495 __ movl(Address(ESP, dst + stack_offset), static_cast<Register>(ensure_scratch.GetRegister()));
/art/compiler/utils/mips/
H A Dassembler_mips.cc459 MipsManagedRegister dst = m_dst.AsMips(); local
460 if (dst.IsNoRegister()) {
461 CHECK_EQ(0u, size) << dst;
462 } else if (dst.IsCoreRegister()) {
463 CHECK_EQ(4u, size) << dst;
464 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset);
465 } else if (dst.IsRegisterPair()) {
466 CHECK_EQ(8u, size) << dst;
467 LoadFromOffset(kLoadWord, dst.AsRegisterPairLow(), src_register, src_offset);
468 LoadFromOffset(kLoadWord, dst
[all...]
/art/compiler/utils/x86/
H A Dassembler_x86.cc105 void X86Assembler::movl(Register dst, const Immediate& imm) { argument
107 EmitUint8(0xB8 + dst);
112 void X86Assembler::movl(Register dst, Register src) { argument
115 EmitRegisterOperand(src, dst);
119 void X86Assembler::movl(Register dst, const Address& src) { argument
122 EmitOperand(dst, src);
126 void X86Assembler::movl(const Address& dst, Register src) { argument
129 EmitOperand(src, dst);
133 void X86Assembler::movl(const Address& dst, const Immediate& imm) { argument
136 EmitOperand(0, dst);
140 movl(const Address& dst, Label* lbl) argument
147 movzxb(Register dst, ByteRegister src) argument
155 movzxb(Register dst, const Address& src) argument
163 movsxb(Register dst, ByteRegister src) argument
171 movsxb(Register dst, const Address& src) argument
184 movb(const Address& dst, ByteRegister src) argument
191 movb(const Address& dst, const Immediate& imm) argument
200 movzxw(Register dst, Register src) argument
208 movzxw(Register dst, const Address& src) argument
216 movsxw(Register dst, Register src) argument
224 movsxw(Register dst, const Address& src) argument
237 movw(const Address& dst, Register src) argument
245 leal(Register dst, const Address& src) argument
252 cmovl(Condition condition, Register dst, Register src) argument
260 setb(Condition condition, Register dst) argument
268 movss(XmmRegister dst, const Address& src) argument
277 movss(const Address& dst, XmmRegister src) argument
286 movss(XmmRegister dst, XmmRegister src) argument
295 movd(XmmRegister dst, Register src) argument
304 movd(Register dst, XmmRegister src) argument
313 addss(XmmRegister dst, XmmRegister src) argument
322 addss(XmmRegister dst, const Address& src) argument
331 subss(XmmRegister dst, XmmRegister src) argument
340 subss(XmmRegister dst, const Address& src) argument
349 mulss(XmmRegister dst, XmmRegister src) argument
358 mulss(XmmRegister dst, const Address& src) argument
367 divss(XmmRegister dst, XmmRegister src) argument
376 divss(XmmRegister dst, const Address& src) argument
392 fstps(const Address& dst) argument
399 movsd(XmmRegister dst, const Address& src) argument
408 movsd(const Address& dst, XmmRegister src) argument
417 movsd(XmmRegister dst, XmmRegister src) argument
426 addsd(XmmRegister dst, XmmRegister src) argument
435 addsd(XmmRegister dst, const Address& src) argument
444 subsd(XmmRegister dst, XmmRegister src) argument
453 subsd(XmmRegister dst, const Address& src) argument
462 mulsd(XmmRegister dst, XmmRegister src) argument
471 mulsd(XmmRegister dst, const Address& src) argument
480 divsd(XmmRegister dst, XmmRegister src) argument
489 divsd(XmmRegister dst, const Address& src) argument
498 cvtsi2ss(XmmRegister dst, Register src) argument
507 cvtsi2sd(XmmRegister dst, Register src) argument
516 cvtss2si(Register dst, XmmRegister src) argument
525 cvtss2sd(XmmRegister dst, XmmRegister src) argument
534 cvtsd2si(Register dst, XmmRegister src) argument
543 cvttss2si(Register dst, XmmRegister src) argument
552 cvttsd2si(Register dst, XmmRegister src) argument
561 cvtsd2ss(XmmRegister dst, XmmRegister src) argument
570 cvtdq2pd(XmmRegister dst, XmmRegister src) argument
596 sqrtsd(XmmRegister dst, XmmRegister src) argument
605 sqrtss(XmmRegister dst, XmmRegister src) argument
614 xorpd(XmmRegister dst, const Address& src) argument
623 xorpd(XmmRegister dst, XmmRegister src) argument
632 xorps(XmmRegister dst, const Address& src) argument
640 xorps(XmmRegister dst, XmmRegister src) argument
648 andpd(XmmRegister dst, const Address& src) argument
664 fstpl(const Address& dst) argument
671 fnstcw(const Address& dst) argument
685 fistpl(const Address& dst) argument
692 fistps(const Address& dst) argument
742 xchgl(Register dst, Register src) argument
775 addl(Register dst, Register src) argument
841 andl(Register dst, Register src) argument
848 andl(Register dst, const Immediate& imm) argument
854 orl(Register dst, Register src) argument
861 orl(Register dst, const Immediate& imm) argument
867 xorl(Register dst, Register src) argument
873 xorl(Register dst, const Immediate& imm) argument
903 adcl(Register dst, Register src) argument
910 adcl(Register dst, const Address& address) argument
917 subl(Register dst, Register src) argument
950 imull(Register dst, Register src) argument
1002 sbbl(Register dst, Register src) argument
1015 sbbl(Register dst, const Address& address) argument
1078 shld(Register dst, Register src) argument
1260 LoadDoubleConstant(XmmRegister dst, double value) argument
[all...]
/art/compiler/utils/x86_64/
H A Dassembler_x86_64.cc105 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { argument
109 EmitRex64(dst);
111 EmitRegisterOperand(0, dst.LowBits());
114 EmitRex64(dst);
115 EmitUint8(0xB8 + dst.LowBits());
121 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { argument
123 EmitOptionalRex32(dst);
124 EmitUint8(0xB8 + dst.LowBits());
129 void X86_64Assembler::movq(CpuRegister dst, CpuRegister src) { argument
132 EmitRex64(src, dst);
138 movl(CpuRegister dst, CpuRegister src) argument
146 movq(CpuRegister dst, const Address& src) argument
154 movl(CpuRegister dst, const Address& src) argument
162 movq(const Address& dst, CpuRegister src) argument
170 movl(const Address& dst, CpuRegister src) argument
177 movl(const Address& dst, const Immediate& imm) argument
185 movzxb(CpuRegister dst, CpuRegister src) argument
194 movzxb(CpuRegister dst, const Address& src) argument
203 movsxb(CpuRegister dst, CpuRegister src) argument
212 movsxb(CpuRegister dst, const Address& src) argument
226 movb(const Address& dst, CpuRegister src) argument
234 movb(const Address& dst, const Immediate& imm) argument
243 movzxw(CpuRegister dst, CpuRegister src) argument
252 movzxw(CpuRegister dst, const Address& src) argument
261 movsxw(CpuRegister dst, CpuRegister src) argument
270 movsxw(CpuRegister dst, const Address& src) argument
284 movw(const Address& dst, CpuRegister src) argument
293 leaq(CpuRegister dst, const Address& src) argument
301 movss(XmmRegister dst, const Address& src) argument
311 movss(const Address& dst, XmmRegister src) argument
321 movss(XmmRegister dst, XmmRegister src) argument
331 movd(XmmRegister dst, CpuRegister src) argument
341 movd(CpuRegister dst, XmmRegister src) argument
351 addss(XmmRegister dst, XmmRegister src) argument
361 addss(XmmRegister dst, const Address& src) argument
371 subss(XmmRegister dst, XmmRegister src) argument
381 subss(XmmRegister dst, const Address& src) argument
391 mulss(XmmRegister dst, XmmRegister src) argument
401 mulss(XmmRegister dst, const Address& src) argument
411 divss(XmmRegister dst, XmmRegister src) argument
421 divss(XmmRegister dst, const Address& src) argument
438 fstps(const Address& dst) argument
445 movsd(XmmRegister dst, const Address& src) argument
455 movsd(const Address& dst, XmmRegister src) argument
465 movsd(XmmRegister dst, XmmRegister src) argument
475 addsd(XmmRegister dst, XmmRegister src) argument
485 addsd(XmmRegister dst, const Address& src) argument
495 subsd(XmmRegister dst, XmmRegister src) argument
505 subsd(XmmRegister dst, const Address& src) argument
515 mulsd(XmmRegister dst, XmmRegister src) argument
525 mulsd(XmmRegister dst, const Address& src) argument
535 divsd(XmmRegister dst, XmmRegister src) argument
545 divsd(XmmRegister dst, const Address& src) argument
555 cvtsi2ss(XmmRegister dst, CpuRegister src) argument
565 cvtsi2sd(XmmRegister dst, CpuRegister src) argument
575 cvtss2si(CpuRegister dst, XmmRegister src) argument
585 cvtss2sd(XmmRegister dst, XmmRegister src) argument
595 cvtsd2si(CpuRegister dst, XmmRegister src) argument
605 cvttss2si(CpuRegister dst, XmmRegister src) argument
615 cvttsd2si(CpuRegister dst, XmmRegister src) argument
625 cvtsd2ss(XmmRegister dst, XmmRegister src) argument
635 cvtdq2pd(XmmRegister dst, XmmRegister src) argument
664 sqrtsd(XmmRegister dst, XmmRegister src) argument
674 sqrtss(XmmRegister dst, XmmRegister src) argument
684 xorpd(XmmRegister dst, const Address& src) argument
694 xorpd(XmmRegister dst, XmmRegister src) argument
704 xorps(XmmRegister dst, const Address& src) argument
713 xorps(XmmRegister dst, XmmRegister src) argument
722 andpd(XmmRegister dst, const Address& src) argument
739 fstpl(const Address& dst) argument
746 fnstcw(const Address& dst) argument
760 fistpl(const Address& dst) argument
767 fistps(const Address& dst) argument
817 xchgl(CpuRegister dst, CpuRegister src) argument
825 xchgq(CpuRegister dst, CpuRegister src) argument
888 addl(CpuRegister dst, CpuRegister src) argument
961 andl(CpuRegister dst, CpuRegister src) argument
969 andl(CpuRegister dst, const Immediate& imm) argument
984 orl(CpuRegister dst, CpuRegister src) argument
992 orl(CpuRegister dst, const Immediate& imm) argument
999 xorl(CpuRegister dst, CpuRegister src) argument
1007 xorq(CpuRegister dst, CpuRegister src) argument
1015 xorq(CpuRegister dst, const Immediate& imm) argument
1090 addq(CpuRegister dst, const Address& address) argument
1098 addq(CpuRegister dst, CpuRegister src) argument
1122 subl(CpuRegister dst, CpuRegister src) argument
1145 subq(CpuRegister dst, CpuRegister src) argument
1183 imull(CpuRegister dst, CpuRegister src) argument
1444 setcc(Condition condition, CpuRegister dst) argument
1456 LoadDoubleConstant(XmmRegister dst, double value) argument
1642 EmitOptionalRex32(CpuRegister dst, CpuRegister src) argument
1646 EmitOptionalRex32(XmmRegister dst, XmmRegister src) argument
1650 EmitOptionalRex32(CpuRegister dst, XmmRegister src) argument
1654 EmitOptionalRex32(XmmRegister dst, CpuRegister src) argument
1665 EmitOptionalRex32(CpuRegister dst, const Operand& operand) argument
1675 EmitOptionalRex32(XmmRegister dst, const Operand& operand) argument
1689 EmitRex64(CpuRegister dst, CpuRegister src) argument
1693 EmitRex64(CpuRegister dst, const Operand& operand) argument
1703 EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) argument
1707 EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) argument
[all...]
/art/runtime/gc/
H A Dheap.h375 void WriteBarrierField(const mirror::Object* dst, MemberOffset /*offset*/, argument
377 card_table_->MarkCard(dst);
381 void WriteBarrierArray(const mirror::Object* dst, int /*start_offset*/, argument
383 card_table_->MarkCard(dst);
/art/test/MyClassNatives/
H A DMyClassNatives.java33 static native void arraycopy(Object src, int src_pos, Object dst, int dst_pos, int length); argument
/art/compiler/jni/
H A Djni_compiler_test.cc868 void my_arraycopy(JNIEnv* env, jclass klass, jobject src, jint src_pos, jobject dst, jint dst_pos, jint length) { argument
870 EXPECT_TRUE(env->IsSameObject(JniCompilerTest::jklass_, dst));

Completed in 5081 milliseconds