| /system/core/libpixelflinger/codeflinger/ |
| H A D | ARMAssembler.cpp | 458 uint32_t immediate, uint32_t& rot, uint32_t& imm)
461 imm = immediate;
462 if (imm > 0x7F) { // skip the easy cases
463 while (!(imm&3) || (imm&0xFC000000)) {
465 newval = imm >> 2;
466 newval |= (imm&3) << 30;
467 imm = newval;
477 if (imm>=0x100)
480 if (((imm>>(ro
457 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument
490 uint32_t rot, imm; local
494 uint32_t ARMAssembler::imm(uint32_t immediate) function in class:android::ARMAssembler
496 uint32_t rot, imm; local
[all...] |
| H A D | ARMAssemblerProxy.cpp | 81 int ARMAssemblerProxy::buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm) argument
83 return mTarget->buildImmediate(i, rot, imm);
88 uint32_t ARMAssemblerProxy::imm(uint32_t immediate) function in class:android::ARMAssemblerProxy
90 return mTarget->imm(immediate);
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| H A D | Arm64Assembler.cpp | 366 int imm = mAddrMode.immediate; local
367 *mPC++ = A64_MOVZ_W(mTmpReg2, imm & 0x0000FFFF, 0);
368 *mPC++ = A64_MOVK_W(mTmpReg2, (imm >> 16) & 0x0000FFFF, 16);
484 int imm = mAddrMode.immediate; local
485 *mPC++ = A64_MOVZ_W(mTmpReg1, imm & 0x0000FFFF, 0);
486 *mPC++ = A64_MOVK_W(mTmpReg1, (imm >> 16) & 0x0000FFFF, 16);
587 int imm = mAddrMode.immediate; local
588 if(imm >= 0 && imm < (1<<12))
589 *mPC++ = A64_ADD_IMM_X(mTmpReg1, mZeroReg, imm,
843 uint32_t imm = 0x00FF00FF; local
860 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument
871 uint32_t rot, imm; local
875 uint32_t ArmToArm64Assembler::imm(uint32_t immediate) function in class:android::ArmToArm64Assembler
1082 A64_ADD_IMM_X(uint32_t Rd, uint32_t Rn, uint32_t imm, uint32_t shift) argument
1089 A64_SUB_IMM_X(uint32_t Rd, uint32_t Rn, uint32_t imm, uint32_t shift) argument
1177 A64_MOVZ_X(uint32_t Rd, uint32_t imm, uint32_t shift) argument
1184 A64_MOVK_W(uint32_t Rd, uint32_t imm, uint32_t shift) argument
1191 A64_MOVZ_W(uint32_t Rd, uint32_t imm, uint32_t shift) argument
[all...] |
| H A D | MIPSAssembler.cpp | 43 ** Refactored ARM address-mode static functions (imm(), reg_imm(), imm12_pre(), etc.)
211 uint32_t immediate, uint32_t& rot, uint32_t& imm)
215 imm = immediate;
227 uint32_t ArmToMipsAssembler::imm(uint32_t immediate) function in class:android::ArmToMipsAssembler
373 // this works with the imm(), reg_imm() methods above, which are directly
1445 // MD00086 pdf says this is: ADDIU rt, rs, imm -- they do not use Rd
1446 void MIPSAssembler::ADDIU(int Rt, int Rs, int16_t imm) argument
1448 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1459 void MIPSAssembler::SUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j) argument
1461 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm)
210 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument
1533 SLTI(int Rt, int Rs, int16_t imm) argument
1545 SLTIU(int Rt, int Rs, int16_t imm) argument
1563 ANDI(int Rt, int Rs, uint16_t imm) argument
1575 ORI(int Rt, int Rs, uint16_t imm) argument
1597 XORI(int Rt, int Rs, uint16_t imm) argument
[all...] |
| H A D | mips_opcode.h | 52 unsigned imm: 16; member in struct:__anon180::__anon181
87 unsigned imm: 16; member in struct:__anon180::__anon185
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