/art/runtime/ |
H A D | dex_instruction_visitor.h | 33 const Instruction* inst = Instruction::At(&code[i]); local 34 switch (inst->Opcode()) { 37 derived->Do_ ## cname(inst); \ 47 i += inst->SizeInCodeUnits(); 54 void Do_ ## cname(const Instruction* inst) { \ 56 derived->Do_Default(inst); \
|
H A D | quick_exception_handler.cc | 206 const Instruction* inst = Instruction::At(code_item->insns_ + dex_pc); local 207 uint32_t new_dex_pc = dex_pc + inst->SizeInCodeUnits();
|
/art/compiler/sea_ir/types/ |
H A D | type_inference.cc | 47 FunctionTypeInfo::FunctionTypeInfo(const SeaGraph* graph, InstructionNode* inst, argument 49 dex_method_idx_(inst->GetInstruction()->VRegB_35c()), type_cache_(types),
|
/art/compiler/dex/ |
H A D | dex_to_dex_compiler.cc | 61 void CompileReturnVoid(Instruction* inst, uint32_t dex_pc); 65 // the given "inst". 66 Instruction* CompileCheckCast(Instruction* inst, uint32_t dex_pc); 74 void CompileInstanceFieldAccess(Instruction* inst, uint32_t dex_pc, 83 void CompileInvokeVirtual(Instruction* inst, uint32_t dex_pc, 98 Instruction* inst = const_cast<Instruction*>(Instruction::At(insns)); local 101 inst = const_cast<Instruction*>(inst->Next()), dex_pc = inst->GetDexPc(insns)) { 102 switch (inst 156 CompileReturnVoid(Instruction* inst, uint32_t dex_pc) argument 175 CompileCheckCast(Instruction* inst, uint32_t dex_pc) argument 203 CompileInstanceFieldAccess(Instruction* inst, uint32_t dex_pc, Instruction::Code new_opcode, bool is_put) argument 229 CompileInvokeVirtual(Instruction* inst, uint32_t dex_pc, Instruction::Code new_opcode, bool is_range) argument [all...] |
H A D | verified_method.cc | 202 const Instruction* inst = Instruction::At(insns); local 205 for (; inst < end; inst = inst->Next()) { 206 bool is_virtual = (inst->Opcode() == Instruction::INVOKE_VIRTUAL) || 207 (inst->Opcode() == Instruction::INVOKE_VIRTUAL_RANGE); 208 bool is_interface = (inst->Opcode() == Instruction::INVOKE_INTERFACE) || 209 (inst->Opcode() == Instruction::INVOKE_INTERFACE_RANGE); 215 uint32_t dex_pc = inst->GetDexPc(insns); 217 bool is_range = (inst 276 const Instruction* inst = Instruction::At(code_item->insns_); local [all...] |
H A D | mir_graph.cc | 141 const Instruction* inst = Instruction::At(code_ptr); local 142 decoded_instruction->opcode = inst->Opcode(); 143 decoded_instruction->vA = inst->HasVRegA() ? inst->VRegA() : 0; 144 decoded_instruction->vB = inst->HasVRegB() ? inst->VRegB() : 0; 145 decoded_instruction->vB_wide = inst->HasWideVRegB() ? inst->WideVRegB() : 0; 146 decoded_instruction->vC = inst->HasVRegC() ? inst [all...] |
/art/compiler/sea_ir/ir/ |
H A D | instruction_nodes.h | 111 explicit ConstInstructionNode(const art::Instruction* inst): argument 112 InstructionNode(inst) { } 126 explicit UnnamedConstInstructionNode(const art::Instruction* inst, int32_t value): argument 127 ConstInstructionNode(inst), value_(value) { } 148 explicit ReturnInstructionNode(const art::Instruction* inst): InstructionNode(inst) { } argument 157 explicit IfNeInstructionNode(const art::Instruction* inst): InstructionNode(inst) { argument 158 DCHECK(InstructionTools::IsDefinition(inst) == false); 170 explicit MoveResultInstructionNode(const art::Instruction* inst) argument 184 InvokeStaticInstructionNode(const art::Instruction* inst) argument 204 AddIntInstructionNode(const art::Instruction* inst) argument 213 AddIntLitInstructionNode(const art::Instruction* inst) argument 230 GotoInstructionNode(const art::Instruction* inst) argument 239 IfEqzInstructionNode(const art::Instruction* inst) argument [all...] |
H A D | sea.cc | 208 const art::Instruction* inst = art::Instruction::At(&code[i]); local 209 if (inst->IsBranch() || inst->IsUnconditional()) { 210 int32_t offset = inst->GetTargetOffset(); 215 if (inst->CanFlowThrough() 216 && (target_regions.end() == target_regions.find(&code[i + inst->SizeInCodeUnits()]))) { 219 std::pair<const uint16_t*, Region*>(&code[i + inst->SizeInCodeUnits()], region)); 222 i += inst->SizeInCodeUnits(); 235 const art::Instruction* inst = art::Instruction::At(&code[i]); local 237 sea_ir::InstructionNode::Create(inst); [all...] |
/art/runtime/interpreter/ |
H A D | interpreter_common.h | 101 const Instruction* inst, uint16_t inst_data, JValue* result); 106 static inline bool DoInvoke(Thread* self, ShadowFrame& shadow_frame, const Instruction* inst, argument 108 const uint32_t method_idx = (is_range) ? inst->VRegB_3rc() : inst->VRegB_35c(); 109 const uint32_t vregC = (is_range) ? inst->VRegC_3rc() : inst->VRegC_35c(); 124 return DoCall<is_range, do_access_check>(method, self, shadow_frame, inst, inst_data, result); 132 const Instruction* inst, uint16_t inst_data, 134 const uint32_t vregC = (is_range) ? inst->VRegC_3rc() : inst 131 DoInvokeVirtualQuick(Thread* self, ShadowFrame& shadow_frame, const Instruction* inst, uint16_t inst_data, JValue* result) argument [all...] |
H A D | interpreter_goto_table_impl.cc | 24 // - "inst" : the current Instruction*. 35 inst = inst->RelativeAt(disp); \ 38 TraceExecution(shadow_frame, inst, dex_pc, mh); \ 39 inst_data = inst->Fetch16(0); \ 40 goto *currentHandlersTable[inst->Opcode(inst_data)]; \ 145 const Instruction* inst = Instruction::At(code_item->insns_ + dex_pc); local 168 shadow_frame.SetVReg(inst->VRegA_12x(inst_data), 169 shadow_frame.GetVReg(inst->VRegB_12x(inst_data))); 174 shadow_frame.SetVReg(inst [all...] |
H A D | interpreter_switch_impl.cc | 29 inst->GetDexPc(insns), \ 35 inst = inst->RelativeAt(displacement); \ 44 inst = inst->_next_function(); \ 51 DCHECK(!inst->IsReturn()); \ 81 const Instruction* inst = Instruction::At(insns + dex_pc); local 84 dex_pc = inst->GetDexPc(insns); 86 TraceExecution(shadow_frame, inst, dex_pc, mh); 87 inst_data = inst [all...] |
H A D | interpreter_common.cc | 30 bool DoFieldGet(Thread* self, ShadowFrame& shadow_frame, const Instruction* inst, argument 33 const uint32_t field_idx = is_static ? inst->VRegB_21c() : inst->VRegC_22c(); 44 obj = shadow_frame.GetVRegReference(inst->VRegB_22c(inst_data)); 58 uint32_t vregA = is_static ? inst->VRegA_21c(inst_data) : inst->VRegA_22c(inst_data); 91 const Instruction* inst, \ 122 bool DoIGetQuick(ShadowFrame& shadow_frame, const Instruction* inst, uint16_t inst_data) { argument 123 Object* obj = shadow_frame.GetVRegReference(inst->VRegB_22c(inst_data)); 130 MemberOffset field_offset(inst 205 DoFieldPut(Thread* self, const ShadowFrame& shadow_frame, const Instruction* inst, uint16_t inst_data) argument 325 DoIPutQuick(const ShadowFrame& shadow_frame, const Instruction* inst, uint16_t inst_data) argument 488 UnexpectedOpcode(const Instruction* inst, MethodHelper& mh) argument 524 DoCall(ArtMethod* method, Thread* self, ShadowFrame& shadow_frame, const Instruction* inst, uint16_t inst_data, JValue* result) argument 661 DoFilledNewArray(const Instruction* inst, const ShadowFrame& shadow_frame, Thread* self, JValue* result) argument [all...] |
/art/compiler/dex/quick/mips/ |
H A D | target_mips.cc | 489 LIR *inst = LoadWordDisp(tmp, 0, tmp); local 491 return inst;
|
/art/compiler/dex/quick/x86/ |
H A D | utility_x86.cc | 892 LIR* inst = NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(), local 895 *compare = inst;
|
/art/compiler/llvm/ |
H A D | ir_builder.h | 80 ::llvm::LoadInst* inst = LLVMIRBuilder::CreateLoad(ptr); local 81 inst->setMetadata(::llvm::LLVMContext::MD_tbaa, tbaa_info); 82 return inst; 86 ::llvm::StoreInst* inst = LLVMIRBuilder::CreateStore(val, ptr); local 87 inst->setMetadata(::llvm::LLVMContext::MD_tbaa, tbaa_info); 88 return inst; 94 ::llvm::AtomicCmpXchgInst* inst = local 96 inst->setMetadata(::llvm::LLVMContext::MD_tbaa, tbaa_info); 97 return inst; 175 void SetTBAA(::llvm::Instruction* inst, TBAASpecialTyp argument [all...] |
H A D | gbc_expander.cc | 168 llvm::Value* ExpandToRuntime(RuntimeId rt, llvm::CallInst& inst); 642 llvm::Value* GBCExpanderPass::ExpandToRuntime(RuntimeId rt, llvm::CallInst& inst) { argument 646 unsigned num_args = inst.getNumArgOperands(); 653 args.push_back(inst.getArgOperand(i));
|
/art/runtime/verifier/ |
H A D | register_line.cc | 92 RegType& RegisterLine::GetInvocationThis(const Instruction* inst, bool is_range) { argument 93 const size_t args_count = is_range ? inst->VRegA_3rc() : inst->VRegA_35c(); 99 const uint32_t this_reg = (is_range) ? inst->VRegC_3rc() : inst->VRegC_35c(); 283 void RegisterLine::CheckUnaryOp(const Instruction* inst, argument 286 if (VerifyRegisterType(inst->VRegB_12x(), src_type)) { 287 SetRegisterType(inst->VRegA_12x(), dst_type); 291 void RegisterLine::CheckUnaryOpWide(const Instruction* inst, argument 294 if (VerifyRegisterTypeWide(inst 299 CheckUnaryOpToWide(const Instruction* inst, RegType& dst_type1, RegType& dst_type2, RegType& src_type) argument 307 CheckUnaryOpFromWide(const Instruction* inst, RegType& dst_type, RegType& src_type1, RegType& src_type2) argument 315 CheckBinaryOp(const Instruction* inst, RegType& dst_type, RegType& src_type1, RegType& src_type2, bool check_boolean_op) argument 335 CheckBinaryOpWide(const Instruction* inst, RegType& dst_type1, RegType& dst_type2, RegType& src_type1_1, RegType& src_type1_2, RegType& src_type2_1, RegType& src_type2_2) argument 345 CheckBinaryOpWideShift(const Instruction* inst, RegType& long_lo_type, RegType& long_hi_type, RegType& int_type) argument 354 CheckBinaryOp2addr(const Instruction* inst, RegType& dst_type, RegType& src_type1, RegType& src_type2, bool check_boolean_op) argument 373 CheckBinaryOp2addrWide(const Instruction* inst, RegType& dst_type1, RegType& dst_type2, RegType& src_type1_1, RegType& src_type1_2, RegType& src_type2_1, RegType& src_type2_2) argument 385 CheckBinaryOp2addrWideShift(const Instruction* inst, RegType& long_lo_type, RegType& long_hi_type, RegType& int_type) argument 396 CheckLiteralOp(const Instruction* inst, RegType& dst_type, RegType& src_type, bool check_boolean_op, bool is_lit16) argument [all...] |
H A D | method_verifier.cc | 398 const Instruction* inst = Instruction::At(code_item_->insns_ + dex_pc); local 399 return GetQuickFieldAccess(inst, register_line); 428 const Instruction* inst = Instruction::At(code_item_->insns_ + dex_pc); local 429 const bool is_range = (inst->Opcode() == Instruction::INVOKE_VIRTUAL_RANGE_QUICK); 430 return GetQuickInvokedMethod(inst, register_line, is_range); 540 const Instruction* inst = Instruction::At(insns); local 546 Instruction::Code opcode = inst->Opcode(); 567 size_t inst_size = inst->SizeInCodeUnits(); 570 inst = inst 643 const Instruction* inst = Instruction::At(code_item_->insns_); local 669 VerifyInstruction(const Instruction* inst, uint32_t code_offset) argument 1141 const Instruction* inst = Instruction::At(code_item_->insns_); local 1448 const Instruction* inst = Instruction::At(insns); local 3094 VerifyInvocationArgsFromIterator(T* it, const Instruction* inst, MethodType method_type, bool is_range, mirror::ArtMethod* res_method) argument 3213 VerifyInvocationArgsUnresolvedMethod(const Instruction* inst, MethodType method_type, bool is_range) argument 3252 VerifyInvocationArgs(const Instruction* inst, MethodType method_type, bool is_range, bool is_super) argument 3297 GetQuickInvokedMethod(const Instruction* inst, RegisterLine* reg_line, bool is_range) argument 3325 VerifyInvokeVirtualQuickArgs(const Instruction* inst, bool is_range) argument 3416 VerifyNewArray(const Instruction* inst, bool is_filled, bool is_range) argument 3464 VerifyAGet(const Instruction* inst, RegType& insn_type, bool is_primitive) argument 3564 VerifyAPut(const Instruction* inst, RegType& insn_type, bool is_primitive) argument 3698 VerifyISGet(const Instruction* inst, RegType& insn_type, bool is_primitive, bool is_static) argument 3764 VerifyISPut(const Instruction* inst, RegType& insn_type, bool is_primitive, bool is_static) argument 3818 GetQuickFieldAccess(const Instruction* inst, RegisterLine* reg_line) argument 3841 VerifyIGetQuick(const Instruction* inst, RegType& insn_type, bool is_primitive) argument 3901 VerifyIPutQuick(const Instruction* inst, RegType& insn_type, bool is_primitive) argument [all...] |
/art/compiler/dex/portable/ |
H A D | mir_to_gbc.cc | 91 ::llvm::Instruction* inst = ::llvm::dyn_cast< ::llvm::Instruction>(placeholder); local 92 DCHECK(inst != NULL); 93 inst->eraseFromParent(); 1537 ::llvm::Instruction* inst = irb_->CreateCall(intr); local 1545 inst->setMetadata("RegInfo", reg_info_node); 1946 ::llvm::Instruction* inst = ::llvm::dyn_cast< ::llvm::Instruction>(it++); local 1947 DCHECK(inst != NULL); 1948 ::llvm::Value* val = ::llvm::dyn_cast< ::llvm::Value>(inst); 1951 inst->eraseFromParent();
|
/art/compiler/dex/quick/ |
H A D | codegen_util.cc | 82 void Mir2Lir::MarkSafepointPC(LIR* inst) { argument 83 DCHECK(!inst->flags.use_def_invalid); 84 inst->u.m.def_mask = &kEncodeAll; 1186 LIR* inst = Load32Disp(base_reg, offset, temp_reg); local 1188 *compare = inst;
|
H A D | gen_common.cc | 1962 LIR* inst = CheckSuspendUsingLoad(); local 1963 MarkSafepointPC(inst); 1986 LIR* inst = CheckSuspendUsingLoad(); local 1987 MarkSafepointPC(inst);
|
/art/compiler/utils/arm/ |
H A D | assembler_arm32.cc | 1220 int32_t Arm32Assembler::EncodeBranchOffset(int offset, int32_t inst) { argument 1229 return (inst & ~kBranchOffsetMask) | offset; 1233 int Arm32Assembler::DecodeBranchOffset(int32_t inst) { argument 1235 return ((((inst & kBranchOffsetMask) << 8) >> 6) + 8);
|
H A D | assembler_thumb2.cc | 2223 int32_t Thumb2Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) { argument 2231 if ((inst & B12) == B12) { 2243 inst &= ~(0x3ff << 16 | 0x7ff); 2253 inst &= ~(0x3f << 16 | 0x7ff); 2256 inst &= ~(B26 | B13 | B11); 2257 inst |= value; 2258 return inst;
|
/art/compiler/utils/mips/ |
H A D | assembler_mips.cc | 124 int32_t MipsAssembler::EncodeBranchOffset(int offset, int32_t inst, bool is_jump) { argument 132 return (inst & ~kJumpOffsetMask) | offset; 135 return (inst & ~kBranchOffsetMask) | offset; 139 int MipsAssembler::DecodeBranchOffset(int32_t inst, bool is_jump) { argument 142 return (((inst & kJumpOffsetMask) << 6) >> 4); 144 return (((inst & kBranchOffsetMask) << 16) >> 14);
|