/art/compiler/dex/quick/arm/ |
H A D | assemble_arm.cc | 1070 uint8_t* ArmMir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { argument 1071 for (; lir != NULL; lir = NEXT_LIR(lir)) { 1072 if (!lir->flags.is_nop) { 1073 int opcode = lir->opcode; 1077 if (lir->offset & 0x2) { 1083 } else if (LIKELY(!lir->flags.is_nop)) { 1084 const ArmEncodingMap *encoder = &EncodingMap[lir->opcode]; 1089 operand = lir 1211 LIR* lir; local 1631 GetInsnSize(LIR* lir) argument [all...] |
H A D | target_arm.cc | 162 void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, argument 165 DCHECK(!lir->flags.use_def_invalid); 167 int opcode = lir->opcode; 182 def_mask->SetBits(EncodeArmRegList(lir->operands[0])); 186 def_mask->SetBits(EncodeArmRegList(lir->operands[1])); 190 def_mask->SetBits(EncodeArmRegList(lir->operands[0])); 194 for (int i = 0; i < lir->operands[2]; i++) { 195 SetupRegMask(def_mask, lir->operands[1] + i); 209 use_mask->SetBits(EncodeArmRegList(lir->operands[0])); 213 use_mask->SetBits(EncodeArmRegList(lir 353 BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) argument 537 IsUnconditionalBranch(LIR* lir) argument [all...] |
H A D | utility_arm.cc | 836 LIR* lir = nullptr; local 838 lir = NewLIR3(opcode, r_src_dest.GetReg(), r_ptr.GetReg(), encoded_disp); 840 lir = NewLIR4(opcode, r_src_dest.GetLowReg(), r_src_dest.GetHighReg(), r_ptr.GetReg(), 846 return lir; 981 LIR* lir = NewLIR3(kThumb2Ldrexd, r_dest.GetLowReg(), r_dest.GetHighReg(), r_ptr.GetReg()); local 983 return lir; 1172 size_t ArmMir2Lir::GetInstructionOffset(LIR* lir) { argument 1173 uint64_t check_flags = GetTargetInstFlags(lir->opcode); 1175 size_t offset = (check_flags & IS_TERTIARY_OP) ? lir->operands[2] : 0;
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/art/compiler/dex/quick/arm64/ |
H A D | assemble_arm64.cc | 652 uint8_t* Arm64Mir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { argument 653 for (; lir != nullptr; lir = NEXT_LIR(lir)) { 654 bool opcode_is_wide = IS_WIDE(lir->opcode); 655 ArmOpcode opcode = UNWIDE(lir->opcode); 661 if (LIKELY(!lir->flags.is_nop)) { 670 uint32_t operand = lir->operands[i]; 747 << " @ 0x" << std::hex << lir->dalvik_offset; 815 LIR* lir; local 953 GetInsnSize(LIR* lir) argument [all...] |
H A D | target_arm64.cc | 166 void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, argument 169 DCHECK(!lir->flags.use_def_invalid); 335 std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { argument 352 operand = lir->operands[nc-'0']; 357 int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : 407 snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's', 411 bool is_wide = IS_WIDE(lir->opcode); 453 snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); 465 strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); 472 reinterpret_cast<uintptr_t>(base_addr) + lir 566 IsUnconditionalBranch(LIR* lir) argument [all...] |
H A D | utility_arm64.cc | 90 size_t Arm64Mir2Lir::GetLoadStoreSize(LIR* lir) { argument 91 bool opcode_is_wide = IS_WIDE(lir->opcode); 92 ArmOpcode opcode = UNWIDE(lir->opcode); 99 size_t Arm64Mir2Lir::GetInstructionOffset(LIR* lir) { argument 100 size_t offset = lir->operands[2]; 101 uint64_t check_flags = GetTargetInstFlags(lir->opcode); 105 offset = offset * (1 << GetLoadStoreSize(lir));
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/art/compiler/dex/quick/mips/ |
H A D | assemble_mips.cc | 460 void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir) { argument 463 int opcode = lir->opcode; 464 int dalvik_offset = lir->dalvik_offset; 485 LIR* hop_branch = RawLIR(dalvik_offset, opcode, lir->operands[0], 486 lir->operands[1], 0, 0, 0, hop_target); 487 InsertLIRBefore(lir, hop_branch); 490 InsertLIRBefore(lir, curr_pc); 493 lir->target); 494 InsertLIRBefore(lir, delta_hi); 495 InsertLIRBefore(lir, ancho 516 LIR *lir; local 712 GetInsnSize(LIR* lir) argument 720 LIR* lir; local [all...] |
H A D | target_mips.cc | 146 void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, argument 149 DCHECK(!lir->flags.use_def_invalid); 194 std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { argument 211 operand = lir->operands[nc-'0']; 245 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 + (operand << 1), 246 lir->target); 252 int offset_1 = lir->operands[0]; 253 int offset_2 = NEXT_LIR(lir)->operands[0]; 255 (((reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4) & ~3) + 557 bool MipsMir2Lir::IsUnconditionalBranch(LIR* lir) { argument [all...] |
/art/compiler/dex/quick/ |
H A D | mir_to_lir-inl.h | 161 inline void Mir2Lir::SetupResourceMasks(LIR* lir) { argument 162 int opcode = lir->opcode; 165 lir->u.m.use_mask = lir->u.m.def_mask = &kEncodeNone; 167 lir->flags.fixup = kFixupLabel; 176 lir->flags.fixup = kFixupLabel; 180 lir->flags.size = GetInsnSize(lir); 181 estimated_native_code_size_ += lir->flags.size; 207 lir [all...] |
H A D | local_optimizations.cc | 92 inline void Mir2Lir::EliminateLoad(LIR* lir, int reg_id) { argument 93 DCHECK(RegStorage::SameRegType(lir->operands[0], reg_id)); 97 if (lir->operands[0] == reg_id) { 98 NopLIR(lir); 105 dest_reg = RegStorage::Solo32(lir->operands[0]); 109 dest_reg = RegStorage::Solo64(lir->operands[0]); 113 dest_reg = RegStorage::FloatSolo32(lir->operands[0]); 117 dest_reg = RegStorage::FloatSolo64(lir->operands[0]); 124 ConvertMemOpIntoMove(lir, dest_reg, src_reg); 125 NopLIR(lir); [all...] |
H A D | mir_to_lir.cc | 1314 size_t Mir2Lir::GetInstructionOffset(LIR* lir) { argument
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H A D | codegen_util.cc | 104 void Mir2Lir::UnlinkLIR(LIR* lir) { argument 105 if (UNLIKELY(lir == first_lir_insn_)) { 106 first_lir_insn_ = lir->next; 107 if (lir->next != NULL) { 108 lir->next->prev = NULL; 110 DCHECK(lir->next == NULL); 111 DCHECK(lir == last_lir_insn_); 114 } else if (lir == last_lir_insn_) { 115 last_lir_insn_ = lir->prev; 116 lir 124 NopLIR(LIR* lir) argument 131 SetMemRefType(LIR* lir, bool is_load, int mem_type) argument 171 AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit) argument 189 DumpLIRInsn(LIR* lir, unsigned char* base_addr) argument 588 AssignLiteralOffsetCommon(LIR* lir, CodeOffset offset) argument 596 AssignLiteralPointerOffsetCommon(LIR* lir, CodeOffset offset, unsigned int element_size) argument 1117 AppendLIR(LIR* lir) argument [all...] |
/art/compiler/dex/quick/x86/ |
H A D | fp_x86.cc | 630 LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP.GetReg(), displacement, 0x7fffffff); local 631 AnnotateDalvikRegAccess(lir, displacement >> 2, false /*is_load */, false /* is_64bit */); 632 AnnotateDalvikRegAccess(lir, displacement >> 2, true /* is_load */, false /* is_64bit*/); 694 LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP.GetReg(), displacement + HIWORD_OFFSET, 0x7fffffff); local 695 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, true /* is_load */, true /* is_64bit*/); 696 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, false /*is_load */, true /* is_64bit */);
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H A D | assemble_x86.cc | 675 size_t X86Mir2Lir::GetInsnSize(LIR* lir) { argument 676 DCHECK(!IsPseudoLirOp(lir->opcode)); 677 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 678 DCHECK_EQ(entry->opcode, lir->opcode) << entry->name; 684 return lir->operands[0]; // Length of nop is sole operand. 687 case kRegOpcode: // lir operands - 0: reg 688 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 689 case kReg: // lir operands - 0: reg 690 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 691 case kMem: // lir operand 1584 EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) argument 1599 LIR *lir; local 1900 LIR* lir; local [all...] |
H A D | int_x86.cc | 99 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , 118 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); 1615 LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), local 1617 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1621 lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); 1622 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1650 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, local 1652 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1654 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1658 lir 2486 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); local 2518 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); local 2526 LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); local [all...] |
H A D | target_x86.cc | 253 void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, argument 256 DCHECK(!lir->flags.use_def_invalid); 291 if (lir->opcode == kX86RepneScasw) { 333 std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { argument 352 int operand = lir->operands[operand_number]; 363 static_cast<uint32_t>(lir->operands[operand_number+1])); 383 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 384 lir->target); 754 bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { argument 755 return (lir [all...] |