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Searched defs:rm (Results 1 - 7 of 7) sorted by relevance

/art/compiler/utils/x86/
H A D	assembler_x86.h	55 Register rm() const { function in class:art::x86::Operand 92 void SetModRM(int mod, Register rm) { argument 94 encoding_[0] = (mod << 6) \| rm; 577 inline void EmitRegisterOperand(int rm, int reg); 578 inline void EmitXmmRegisterOperand(int rm, XmmRegister reg); 582 void EmitOperand(int rm, const Operand& operand); 584 void EmitComplex(int rm, const Operand& operand, const Immediate& immediate); 589 void EmitGenericShift(int rm, Register reg, const Immediate& imm); 590 void EmitGenericShift(int rm, Register operand, Register shifter); 603 inline void X86Assembler::EmitRegisterOperand(int rm, in argument 609 EmitXmmRegisterOperand(int rm, XmmRegister reg) argument [all...]
/art/compiler/utils/x86_64/
H A D	assembler_x86_64.h	67 Register rm() const { function in class:art::x86_64::Operand 109 void SetModRM(uint8_t mod, CpuRegister rm) { argument 111 if (rm.NeedsRex()) { 114 encoding_[0] = (mod << 6) \| rm.LowBits(); 621 void EmitRegisterOperand(uint8_t rm, uint8_t reg); 622 void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg); 626 void EmitOperand(uint8_t rm, const Operand& operand); 628 void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate); 633 void EmitGenericShift(bool wide, int rm, CpuRegister reg, const Immediate& imm); 634 void EmitGenericShift(int rm, CpuRegiste 673 EmitRegisterOperand(uint8_t rm, uint8_t reg) argument 679 EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) argument [all...]
/art/disassembler/
H A D	disassembler_x86.cc	`203 bool store = false; // stores to memory (ie rm is on the left) 204 bool load = false; // loads from memory (ie rm is on the right) 1093 uint8_t rm = modrm & 7; local 1095 if (mod == 0 && rm == 5) { 1103 } else if (rm == 4 && mod != 3) { // SIB 1144 DumpRmReg(address, rex_w, rm, byte_operand \|\| byte_second_operand, 1149 DumpBaseReg(address, rex64, rm);`
H A D	disassembler_arm.cc	149 explicit Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {} 151 ArmRegister rm; member in struct:art::arm::Rm 154 os << r.rm; 1485 ArmRegister rm(instr, 0); 1487 args << Rt << ", [" << Rn << ", " << rm; local 1638 ThumbRegister rm(instr, 3); 1647 args << Rd << ", " << rm << ", #" << imm5; 1701 ThumbRegister rm(instr, 3); 1704 args << rdn << ", " << rm; local 1713 ArmRegister rm(inst 1717 args << DN_Rdn << ", " << rm; local 1728 args << DN_Rdn << ", " << rm; local 1738 args << N_Rn << ", " << rm; local 1746 args << rm; local [all...]
/art/compiler/utils/arm/
H A D	assembler_arm.h	`41 explicit ShifterOperand(Register rm) : type_(kRegister), rm_(rm), rs_(kNoRegister), argument 50 ShifterOperand(Register rm, Shift shift, uint32_t shift_imm = 0) : type_(kRegister), rm_(rm), argument 56 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), argument 202 Address(Register rn, Register rm, Mode am = Offset) : rn_(rn), rm_(rm), offset_(0), argument 204 CHECK_NE(rm, PC); 207 Address(Register rn, Register rm, Shif argument [all...]`
H A D	assembler_arm32.cc	152 void Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { argument 153 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. 154 EmitMulOp(cond, 0, R0, rd, rn, rm); 158 void Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra, argument 160 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 161 EmitMulOp(cond, B21, ra, rd, rn, rm); 165 void Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra, argument 167 // Assembler registers rd, rn, rm, r 172 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument 179 sdiv(Register rd, Register rn, Register rm, Condition cond) argument 195 udiv(Register rd, Register rn, Register rm, Condition cond) argument 615 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument 632 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument 662 clz(Register rd, Register rm, Condition cond) argument 694 EmitMulOp(Condition cond, int32_t opcode, Register rd, Register rn, Register rm, Register rs) argument 1042 Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 1053 Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 1065 Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 1077 Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 1087 Rrx(Register rd, Register rm, bool setcc, Condition cond) argument 1096 Lsl(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 1106 Lsr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 1116 Asr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 1126 Ror(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 1159 blx(Register rm, Condition cond) argument 1169 bx(Register rm, Condition cond) argument 1199 Mov(Register rd, Register rm, Condition cond) argument [all...]
H A D	assembler_thumb2.cc	154 void Thumb2Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { argument 155 if (rd == rm && !IsHighRegister(rd) && !IsHighRegister(rn) && !force_32bit_) { 170 static_cast<uint32_t>(rm); 177 void Thumb2Assembler::mla(Register rd, Register rn, Register rm, Register ra, argument 187 static_cast<uint32_t>(rm); 193 void Thumb2Assembler::mls(Register rd, Register rn, Register rm, Register ra, argument 203 static_cast<uint32_t>(rm); 210 Register rm, Condition cond) { 219 static_cast<uint32_t>(rm); 225 void Thumb2Assembler::sdiv(Register rd, Register rn, Register rm, Conditio argument 209 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument 240 udiv(Register rd, Register rn, Register rm, Condition cond) argument 962 Register rm = so.GetRegister(); local 1092 EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc) argument 1129 EmitShift(Register rd, Register rn, Shift shift, Register rm, bool setcc) argument 1511 clz(Register rd, Register rm, Condition cond) argument 2033 blx(Register rm, Condition cond) argument 2041 bx(Register rm, Condition cond) argument 2069 Mov(Register rd, Register rm, Condition cond) argument 2155 Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 2163 Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 2172 Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 2181 Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 2189 Rrx(Register rd, Register rm, bool setcc, Condition cond) argument 2195 Lsl(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 2202 Lsr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 2209 Asr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 2216 Ror(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument [all...]

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