/external/qemu/target-i386/ |
H A D | ops_sse_header.h | 119 DEF_HELPER_2(glue(movq_mm_T0, SUFFIX), void, Reg, i64) 163 DEF_HELPER_3(cvtsq2ss, void, env, XMMReg, i64) 164 DEF_HELPER_3(cvtsq2sd, void, env, XMMReg, i64)
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/external/chromium_org/third_party/sqlite/src/src/ |
H A D | os_unix.c | 2935 i64 newOffset; 3010 static int seekAndWrite(unixFile *id, i64 offset, const void *pBuf, int cnt){ 3013 i64 newOffset; 3341 static int unixTruncate(sqlite3_file *id, i64 nByte){ 3381 static int unixFileSize(sqlite3_file *id, i64 *pSize){ 3421 static int fcntlSizeHint(unixFile *pFile, i64 nByte){ 3423 i64 nSize; /* Required file size */ 3429 if( nSize>(i64)buf.st_size ){ 3448 i64 iWrite; /* Next offset to write to */ 3485 return fcntlSizeHint((unixFile *)id, *(i64 *)pAr [all...] |
H A D | pragma.c | 145 static void returnSingleInt(Parse *pParse, const char *zLabel, i64 value){ 148 i64 *pI64 = sqlite3DbMallocRaw(pParse->db, sizeof(value)); 581 i64 iLimit = -2;
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H A D | btree.c | 470 i64 iRow, /* The rowid that might be changing */ 652 i64 nKey, /* Integer key for tables. Size of pKey for indices */ 661 assert( nKey==(i64)(int)nKey ); 1810 assert( sizeof(i64)==8 || sizeof(i64)==4 ); 3653 int sqlite3BtreeKeySize(BtCursor *pCur, i64 *pSize){ 4408 i64 intKey, /* The table key */ 4475 i64 nCellKey; 5231 const void *pKey, i64 nKey, /* The key */ 6642 const void *pKey, i64 nKe [all...] |
H A D | mem2.c | 56 i64 iSize; /* Size of this allocation */
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H A D | test2.c | 539 i64 offset;
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H A D | test3.c | 417 sqlite3BtreeKeySize(pCur, (i64*)&n1);
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/external/valgrind/main/none/tests/arm/ |
H A D | neon64.stdout.exp | 20 vmov.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00 21 vmov.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00 45 vmvn.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff 46 vmvn.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff 97 vadd.i64 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 98 vadd.i64 d0, d1, d2 :: Qd 0x0706057c 0x03020178 Qm (i32)0x0000008c Qn (i32)0x00000078 111 vadd.i64 d0, d1, d2 :: Qd 0x00000004 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 112 vadd.i64 d0, d1, d2 :: Qd 0x87060506 0x83020102 Qm (i32)0x80000001 Qn (i32)0x80000002 115 vadd.i64 d13, d14, d15 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 116 vadd.i64 d1 [all...] |
/external/libcxx/test/algorithms/alg.sorting/alg.heap.operations/is.heap/ |
H A D | is_heap_comp.pass.cpp | 144 int i64[] = {0, 0, 0, 1, 1, 1}; local 207 assert(std::is_heap(i64, i64+6, std::greater<int>()) == (std::is_heap_until(i64, i64+6, std::greater<int>()) == i64+6));
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/external/chromium_org/third_party/mesa/src/src/gallium/state_trackers/d3d1x/d3d1xshader/src/ |
H A D | sm4_parse.cpp | 179 op.imm_values[i].i64 = read64();
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/external/chromium_org/third_party/smhasher/src/ |
H A D | pstdint.h | 785 sprintf (str1, "%" PRINTF_INT64_MODIFIER "d %x\n", i64, ~0); 786 if (0 != strcmp (str0, str1)) printf ("Something wrong with i64 : %s\n", str1);
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/external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/src/ |
H A D | sm4_parse.cpp | 179 op.imm_values[i].i64 = read64();
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/external/stlport/stlport/stl/ |
H A D | _limits.h | 261 # define LONGLONG_MIN (-LONGLONG_MAX-1i64)
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/external/clang/www/demo/ |
H A D | index.cgi | 98 $input =~ s@\b(void|i8|i1|i16|i32|i64|float|double|type|label|opaque)\b@<span class="llvm_type">$1</span>@g;
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16ISelLowering.cpp | 145 setOperationAction(ISD::ROTR, MVT::i64, Expand); 147 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 541 default: return getX86SubSuperRegister(Reg, MVT::i64); 668 case MVT::i64:
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H A D | X86ISelLowering.h | 764 return isTargetFTOL() && VT == MVT::i64;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 100 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 229 // i64 conversions are done via library routines even when generating VFP 241 // i64 conversions are done via library routines even when generating VFP 611 // i64 operation support. 612 setOperationAction(ISD::MUL, MVT::i64, Expand); 625 setOperationAction(ISD::SRL, MVT::i64, Custom); 626 setOperationAction(ISD::SRA, MVT::i64, Custom); 647 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); 767 // Turn f64->i64 into VMOVRRD, i64 [all...] |
/external/qemu/ |
H A D | gdbstub.c | 2018 uint64_t i64; local 2044 i64 = va_arg(va, uint64_t); 2045 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 29 setOperationAction(ISD::MUL, MVT::i64, Expand);
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/external/chromium_org/third_party/openssl/openssl/crypto/modes/asm/ |
H A D | ghash-armv4.S | 370 vshl.i64 d22,#48 386 vshl.i64 d22,#48 392 vshl.i64 q10,#1
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/external/kernel-headers/original/uapi/asm-mips/asm/ |
H A D | inst.h | 892 struct m16e_i64 i64; member in union:mips16e_instruction
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/external/libmtp/src/ |
H A D | ptp-pack.c | 652 CTVAL(value->i64,dtoh64a); 691 RARR(value,i64,dtoh64a); 901 htod64a(dpv,value->i64); 962 htod64a(&dpv[sizeof(uint32_t)+i*sizeof(int64_t)],value->a.v[i].i64);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 58 case MVT::i64: return "MVT::i64";
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 29 setOperationAction(ISD::MUL, MVT::i64, Expand);
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