Searched refs:i64 (Results 76 - 100 of 203) sorted by relevance

123456789

/external/chromium_org/third_party/sqlite/src/src/
H A Dfunc.c130 i64 iVal = sqlite3_value_int64(argv[0]);
184 i64 p1, p2;
302 static void *contextMalloc(sqlite3_context *context, i64 nByte){
333 z1 = contextMalloc(context, ((i64)n)+1);
353 z1 = contextMalloc(context, ((i64)n)+1);
855 zText = (char *)contextMalloc(context, (2*(i64)nBlob)+4);
879 z = contextMalloc(context, ((i64)i)+((i64)n)+3);
919 z = zHex = contextMalloc(context, ((i64)n)*2 + 1);
939 i64
[all...]
H A Drowset.c81 i64 v; /* ROWID value for this entry */
167 void sqlite3RowSetInsert(RowSet *p, i64 rowid){
382 int sqlite3RowSetNext(RowSet *p, i64 *pRowid){
H A Dvdbemem.c320 static i64 doubleToInt64(double r){
332 static const i64 maxInt = LARGEST_INT64;
333 static const i64 minInt = SMALLEST_INT64;
344 return (i64)r;
360 i64 sqlite3VdbeIntValue(Mem *pMem){
370 i64 value = 0;
527 void sqlite3VdbeMemSetInt64(Mem *pMem, i64 val){
1060 sqlite3VdbeMemSetInt64(pVal, (i64)pExpr->u.iValue*negInt);
H A Dwal.c403 WAL_HDRSIZE + ((iFrame)-1)*(i64)((szPage)+WAL_FRAME_HDRSIZE) \
1044 i64 nSize; /* Size of log file */
1080 i64 iOffset; /* Next offset to read from log file */
1681 i64 nSize; /* Current size of database file */
1693 i64 nReq = ((i64)mxPage * szPage);
1702 i64 iOffset;
1709 iOffset = (iDbpage-1)*(i64)szPage;
1718 i64 szDb = pWal->hdr.nPage*(i64)szPag
[all...]
/external/libhevc/common/arm/
H A Dihevc_inter_pred_chroma_copy_w16out.s137 vshl.i64 q0,q0,#6 @vshlq_n_s64(temp, 6)
144 vshl.i64 q11,q11,#6 @vshlq_n_s64(temp, 6)
147 vshl.i64 q12,q12,#6 @vshlq_n_s64(temp, 6)
151 vshl.i64 q13,q13,#6 @vshlq_n_s64(temp, 6)
178 vshl.i64 q0,q0,#6 @vshlq_n_s64(temp, 6)
185 vshl.i64 q11,q11,#6 @vshlq_n_s64(temp, 6)
H A Dihevc_inter_pred_luma_copy_w16out.s107 vshl.i64 q0,q0,#6 @vshlq_n_s64(temp, 6)
114 vshl.i64 q11,q11,#6 @vshlq_n_s64(temp, 6)
117 vshl.i64 q12,q12,#6 @vshlq_n_s64(temp, 6)
121 vshl.i64 q13,q13,#6 @vshlq_n_s64(temp, 6)
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp33 addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass);
44 setOperationAction(ISD::ADD, MVT::i64, Legal);
54 setOperationAction(ISD::LOAD, MVT::i64, Custom);
289 /// the operand types from i1 to i64 in order for tablegen to be able to match
299 SDValue OpNode = DAG.getNode(VCCNode, DL, MVT::i64,
300 DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i64,
302 DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i64,
H A DAMDILISelDAGToDAG.cpp138 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
139 R2 = CurDAG->getTargetConstant(0, MVT::i64);
142 R2 = CurDAG->getTargetConstant(0, MVT::i64);
149 R2 = CurDAG->getTargetConstant(0, MVT::i64);
/external/llvm/test/MC/ARM/
H A Dneont2-add-encoding.s9 @ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0x71,0xef,0xa0,0x08]
10 vadd.i64 d16, d17, d16
131 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xef,0xa2,0x04]
132 vaddhn.i64 d16, q8, q9
137 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xff,0xa2,0x04]
138 vraddhn.i64 d16, q8, q9
H A Dneon-add-encoding.s8 @ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf2]
9 vadd.i64 d16, d17, d16
227 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2]
228 vaddhn.i64 d16, q8, q9
233 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf3]
234 vraddhn.i64 d16, q8, q9
242 vadd.i64 d9, d3
247 vadd.i64 q9, q3
252 @ CHECK: vadd.i64 d9, d9, d3 @ encoding: [0x03,0x98,0x39,0xf2]
257 @ CHECK: vadd.i64 q
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDILISelDAGToDAG.cpp138 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
139 R2 = CurDAG->getTargetConstant(0, MVT::i64);
142 R2 = CurDAG->getTargetConstant(0, MVT::i64);
149 R2 = CurDAG->getTargetConstant(0, MVT::i64);
/external/chromium_org/third_party/sqlite/src/test/
H A Dtt3_checkpoint.c75 i64 iCount1, iCount2;
/external/chromium_org/third_party/webrtc/modules/audio_coding/codecs/isac/fix/source/
H A Dfilters_neon.S47 vadd.i64 d16, d16, d17
69 vsub.i64 d31, d26, d0 @ zeros - 33
70 vshl.i64 d27, d26, #32
127 vadd.i64 d16, d17
128 vadd.i64 d18, d19
129 vadd.i64 d18, d16
131 vadd.i64 d18, d17
/external/openssl/crypto/bn/asm/
H A Darmv4-gf2m.S101 vmov.i64 d28, #0x0000ffffffffffff
102 vmov.i64 d29, #0x00000000ffffffff
103 vmov.i64 d30, #0x000000000000ffff
132 vmov.i64 d17, #0
H A Darmv4-gf2m.pl162 vmov.i64 $k48, #0x0000ffffffffffff
163 vmov.i64 $k32, #0x00000000ffffffff
164 vmov.i64 $k16, #0x000000000000ffff
193 vmov.i64 $t3#hi, #0
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp468 if (RetVT == MVT::i64)
479 if (RetVT == MVT::i64)
486 if (RetVT == MVT::i64)
493 if (RetVT == MVT::i64)
500 if (RetVT == MVT::i64)
518 if (RetVT == MVT::i64)
529 if (RetVT == MVT::i64)
536 if (RetVT == MVT::i64)
543 if (RetVT == MVT::i64)
550 if (RetVT == MVT::i64)
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
106 isPPC64 ? MVT::i64 : MVT::i32);
109 isPPC64 ? MVT::i64 : MVT::i32);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expan
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp587 // Truncate values from i64 to i32, for shifts.
588 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 &&
752 if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64)
855 if (N.getValueType() == MVT::i32 && VT == MVT::i64)
857 DL, VT, getUNDEF(DL, MVT::i64), N);
858 if (N.getValueType() == MVT::i64 && VT == MVT::i32)
899 EVT OpcodeVT = MVT::i64;
951 convertTo(SDLoc(N), MVT::i64, Op0),
952 convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input),
957 N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Op
[all...]
/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/jcajce/provider/asymmetric/dh/
H A DKeyAgreementSpi.java39 Integer i64 = Integers.valueOf(64);
44 algorithms.put("DES", i64);
/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp112 setOperationAction(ISD::Constant, MVT::i64, Legal);
142 setOperationAction(ISD::STORE, MVT::i64, Promote);
143 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
155 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
175 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
176 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
188 setOperationAction(ISD::LOAD, MVT::i64, Promote);
189 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
201 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
[all...]
H A DSIISelLowering.cpp34 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
105 setOperationAction(ISD::SELECT, MVT::i64, Custom);
107 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
111 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
169 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
173 setOperationAction(ISD::UDIV, MVT::i64, Expand);
174 setOperationAction(ISD::UREM, MVT::i64, Expand);
257 return VT.bitsGE(MVT::i64);
295 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
[all...]
/external/openssl/crypto/modes/asm/
H A Dghashv8-armx.S13 vshl.i64 q8,q8,#57
20 vshl.i64 q3,q3,#1
/external/qemu/include/qemu/
H A Dtimer.h839 uint64_t i64;
847 return rval.i64;
/external/chromium_org/v8/src/mips/
H A Dsimulator-mips.cc2049 int64_t i64; local
2157 i64 = static_cast<int64_t>(rounded);
2158 set_fpu_register(fd_reg, i64 & 0xffffffff);
2159 set_fpu_register(fd_reg + 1, i64 >> 32);
2164 i64 = static_cast<int64_t>(rounded);
2165 set_fpu_register(fd_reg, i64 & 0xffffffff);
2166 set_fpu_register(fd_reg + 1, i64 >> 32);
2172 i64 = static_cast<int64_t>(rounded);
2173 set_fpu_register(fd_reg, i64 & 0xffffffff);
2174 set_fpu_register(fd_reg + 1, i64 >> 3
[all...]

Completed in 662 milliseconds

123456789