| /art/runtime/arch/arm64/ |
| H A D | registers_arm64.cc | 57 if (rhs >= D0 && rhs < kNumberOfDRegisters) {
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| H A D | registers_arm64.h | 115 D0 = 0, enumerator in enum:art::arm64::DRegister
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| H A D | context_arm64.cc | 119 fprs_[D0] = nullptr;
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| H A D | quick_method_frame_info_arm64.h | 54 (1 << art::arm64::D0) | (1 << art::arm64::D1) | (1 << art::arm64::D2) |
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| /art/compiler/utils/arm/ |
| H A D | managed_register_arm_test.cc | 126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0);
133 EXPECT_EQ(D0, reg.AsDRegister());
295 EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromDRegister(D0)));
303 EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromDRegister(D0)));
311 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromDRegister(D0)));
321 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromDRegister(D0)));
332 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromDRegister(D0)));
342 EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromDRegister(D0)));
352 EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromDRegister(D0)));
356 ArmManagedRegister reg_D0 = ArmManagedRegister::FromDRegister(D0);
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| H A D | constants_arm.h | 60 D0 = 0, enumerator in enum:art::arm::DRegister
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| H A D | assembler_arm32.cc | 285 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
312 dd, D0, D0);
397 EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
407 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
416 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
476 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
486 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
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| H A D | assembler_thumb2.cc | 387 dd, D0, D0);
400 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
482 EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
492 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
501 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
561 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
571 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
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| H A D | assembler_arm.cc | 59 if (rhs >= D0 && rhs < kNumberOfDRegisters) {
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| /art/compiler/utils/mips/ |
| H A D | constants_mips.h | 32 D0 = 0, enumerator in enum:art::mips::DRegister
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| H A D | assembler_mips.cc | 28 if (rhs >= D0 && rhs < kNumberOfDRegisters) {
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| /art/compiler/utils/arm64/ |
| H A D | managed_register_arm64_test.cc | 169 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0);
177 EXPECT_EQ(D0, reg.AsDRegister());
179 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D0)));
221 Arm64ManagedRegister dreg = Arm64ManagedRegister::FromDRegister(D0);
229 EXPECT_EQ(D0, reg.AsOverlappingSRegisterD());
276 EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromDRegister(D0)));
285 EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromDRegister(D0)));
292 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromDRegister(D0)));
304 EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromDRegister(D0)));
312 EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromDRegister(D0)));
[all...] |
| /art/compiler/jni/quick/arm64/ |
| H A D | calling_convention_arm64.cc | 33 D0, D1, D2, D3, D4, D5, D6, D7
53 return Arm64ManagedRegister::FromDRegister(D0);
108 int fp_reg_index = 0; // D0/S0.
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| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 38 return MipsManagedRegister::FromDRegister(D0);
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| /art/compiler/utils/ |
| H A D | assembler_thumb_test.cc | 1023 __ vaddd(D0, D1, D2);
1024 __ vsubd(D0, D1, D2);
1025 __ vmuld(D0, D1, D2);
1026 __ vmlad(D0, D1, D2);
1027 __ vmlsd(D0, D1, D2);
1028 __ vdivd(D0, D1, D2);
1029 __ vabsd(D0, D1);
1030 __ vnegd(D0, D1);
1031 __ vsqrtd(D0, D1);
1071 __ vcmpd(D0, D
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