Searched refs:BaseIdx (Results 1 - 4 of 4) sorted by relevance
/external/llvm/utils/TableGen/ |
H A D | PseudoLoweringEmitter.cpp | 58 unsigned BaseIdx); 75 IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { 83 OperandMap[BaseIdx + i].Kind = OpData::Reg; 84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); 91 // FIXME: We probably shouldn't ever get a non-zero BaseIdx here. 92 assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); 93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) 97 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 102 OperandMap[BaseIdx + i + I].Kind = OpData::Operand; 105 OperandMap[BaseIdx 74 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, IndexedMap<OpData> &OperandMap, unsigned BaseIdx) argument [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
H A D | Store.cpp | 470 SVal BaseIdx = ElemR->getIndex(); local 472 if (!BaseIdx.getAs<nonloc::ConcreteInt>()) 476 BaseIdx.castAs<nonloc::ConcreteInt>().getValue();
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 2893 SDValue BaseIdx = N->getOperand(1); local 2900 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), 2901 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 6084 /// in range [BaseIdx, LastIdx). 6087 unsigned BaseIdx, unsigned LastIdx, 6091 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!"); 6097 unsigned ExpectedVExtractIdx = BaseIdx; 6098 unsigned NumElts = LastIdx - BaseIdx; 6104 SDValue Op = N->getOperand(i + BaseIdx); 6110 ExpectedVExtractIdx = BaseIdx; 6143 ExpectedVExtractIdx = BaseIdx; 6085 isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode, SelectionDAG &DAG, unsigned BaseIdx, unsigned LastIdx, SDValue &V0, SDValue &V1) argument
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