Searched refs:MSR_MTRRphysMask (Results 1 - 2 of 2) sorted by relevance

/external/qemu/target-i386/
H A Dmisc_helper.c335 case MSR_MTRRphysMask(0):
336 case MSR_MTRRphysMask(1):
337 case MSR_MTRRphysMask(2):
338 case MSR_MTRRphysMask(3):
339 case MSR_MTRRphysMask(4):
340 case MSR_MTRRphysMask(5):
341 case MSR_MTRRphysMask(6):
342 case MSR_MTRRphysMask(7):
343 env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask = val;
454 case MSR_MTRRphysMask(
[all...]
H A Dcpu.h333 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) macro

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