Searched refs:OUT_CB_REG (Results 1 - 8 of 8) sorted by relevance

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/
H A Dr300_context.c276 OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
279 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
286 OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
293 OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
299 OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
302 OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
310 OUT_CB_REG(R300_GB_SELECT, 0);
311 OUT_CB_REG(R300_FG_FOG_BLEND, 0);
312 OUT_CB_REG(R300_GA_OFFSET, 0);
313 OUT_CB_REG(R300_SU_TEX_WRA
[all...]
H A Dr300_fs.c272 OUT_CB_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
273 OUT_CB_REG(R500_US_PIXSIZE, code->max_temp_idx);
274 OUT_CB_REG(R500_US_FC_CTRL, code->us_fc_ctrl);
276 OUT_CB_REG(R500_US_FC_INT_CONST_0 + (i * 4),
279 OUT_CB_REG(R500_US_CODE_RANGE,
281 OUT_CB_REG(R500_US_CODE_OFFSET, 0);
282 OUT_CB_REG(R500_US_CODE_ADDR,
285 OUT_CB_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
302 OUT_CB_REG(R500_GA_US_VECTOR_INDEX,
338 OUT_CB_REG(R300_US_CONFI
[all...]
H A Dr300_cb.h130 #define OUT_CB_REG(register, value) do { \ macro
H A Dr300_state.c404 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
409 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
416 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
421 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
426 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
431 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
533 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
550 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
664 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
669 OUT_CB_REG(R500_ZB_STENCILREFMASK_B
[all...]
/external/mesa3d/src/gallium/drivers/r300/
H A Dr300_context.c276 OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
279 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
286 OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
293 OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
299 OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
302 OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
310 OUT_CB_REG(R300_GB_SELECT, 0);
311 OUT_CB_REG(R300_FG_FOG_BLEND, 0);
312 OUT_CB_REG(R300_GA_OFFSET, 0);
313 OUT_CB_REG(R300_SU_TEX_WRA
[all...]
H A Dr300_fs.c272 OUT_CB_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
273 OUT_CB_REG(R500_US_PIXSIZE, code->max_temp_idx);
274 OUT_CB_REG(R500_US_FC_CTRL, code->us_fc_ctrl);
276 OUT_CB_REG(R500_US_FC_INT_CONST_0 + (i * 4),
279 OUT_CB_REG(R500_US_CODE_RANGE,
281 OUT_CB_REG(R500_US_CODE_OFFSET, 0);
282 OUT_CB_REG(R500_US_CODE_ADDR,
285 OUT_CB_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
302 OUT_CB_REG(R500_GA_US_VECTOR_INDEX,
338 OUT_CB_REG(R300_US_CONFI
[all...]
H A Dr300_cb.h130 #define OUT_CB_REG(register, value) do { \ macro
H A Dr300_state.c404 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
409 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
416 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
421 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
426 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
431 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
533 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
550 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
664 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
669 OUT_CB_REG(R500_ZB_STENCILREFMASK_B
[all...]

Completed in 155 milliseconds