/external/llvm/lib/Target/ARM/ |
H A D | Thumb2RegisterInfo.h | 33 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
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H A D | ARMLoadStoreOptimizer.cpp | 103 ARMCC::CondCodes Pred, unsigned PredReg); 106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, 120 unsigned PredReg, 126 ARMCC::CondCodes Pred, unsigned PredReg, 336 ARMCC::CondCodes Pred, unsigned PredReg) { 388 .addImm(Pred).addReg(PredReg); 406 .addImm(Pred).addReg(PredReg); 417 unsigned PredReg, unsigned Scratch, DebugLoc dl, 481 .addImm(Pred).addReg(PredReg); 485 .addImm(Pred).addReg(PredReg); 332 UpdateBaseRegUses(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc dl, unsigned Base, unsigned WordOffset, ARMCC::CondCodes Pred, unsigned PredReg) argument 413 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument 610 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument 708 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument 793 isMatchingDecrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument 828 isMatchingIncrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument 994 unsigned PredReg = 0; local 1151 unsigned PredReg = 0; local 1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1415 unsigned PredReg = 0; local 1534 unsigned PredReg = 0; local 1875 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument 2037 unsigned BaseReg = 0, PredReg = 0; local 2134 unsigned PredReg = 0; local [all...] |
H A D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, 35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | Thumb2InstrInfo.cpp | 61 unsigned PredReg = 0; local 62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); 109 unsigned PredReg = 0; local 110 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 215 ARMCC::CondCodes Pred, unsigned PredReg, 220 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 244 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 253 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 259 .addImm((unsigned)Pred).addReg(PredReg) 212 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
H A D | Thumb1RegisterInfo.h | 41 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
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H A D | Thumb2InstrInfo.h | 69 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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H A D | Thumb2ITBlockPass.cpp | 171 unsigned PredReg = 0; local 172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
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H A D | ARMBaseRegisterInfo.cpp | 403 unsigned PredReg, unsigned MIFlags) const { 414 .addImm(0).addImm(Pred).addReg(PredReg) 760 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); local 768 Offset, Pred, PredReg, TII); 772 Offset, Pred, PredReg, TII); 398 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMBaseInstrInfo.h | 382 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 403 ARMCC::CondCodes Pred, unsigned PredReg, 409 ARMCC::CondCodes Pred, unsigned PredReg,
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H A D | MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); local 298 MIB.addImm(Pred).addReg(PredReg); 310 MIB.addImm(Pred).addReg(PredReg);
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H A D | ARMBaseRegisterInfo.h | 173 unsigned PredReg = 0,
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H A D | Thumb2SizeReduction.cpp | 581 unsigned PredReg = 0; local 582 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 685 unsigned PredReg = 0; local 686 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 782 unsigned PredReg = 0; local 783 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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H A D | Thumb1RegisterInfo.cpp | 67 ARMCC::CondCodes Pred, unsigned PredReg, 78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) 371 unsigned PredReg; 372 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { 62 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMFrameLowering.cpp | 120 unsigned PredReg = 0) { 123 Pred, PredReg, TII, MIFlags); 126 Pred, PredReg, TII, MIFlags); 134 unsigned PredReg = 0) { 136 MIFlags, Pred, PredReg); 1657 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1658 unsigned PredReg = Old->getOperand(2).getReg(); local 1660 Pred, PredReg); 1662 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1663 unsigned PredReg local [all...] |
H A D | ARMConstantIslandPass.cpp | 1350 unsigned PredReg = 0; local 1351 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); 1796 unsigned PredReg = 0; local 1797 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); 1815 Pred = getInstrPredicate(CmpMI, PredReg);
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H A D | ARMExpandPseudoInsts.cpp | 656 unsigned PredReg = 0; local 657 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); 684 LO16.addImm(Pred).addReg(PredReg).addReg(0); 685 HI16.addImm(Pred).addReg(PredReg).addReg(0); 733 LO16.addImm(Pred).addReg(PredReg); 734 HI16.addImm(Pred).addReg(PredReg);
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H A D | ARMBaseInstrInfo.cpp | 1634 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { argument 1637 PredReg = 0; 1641 PredReg = MI->getOperand(PIdx+1).getReg(); 1664 unsigned PredReg = 0; local 1665 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1667 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1843 ARMCC::CondCodes Pred, unsigned PredReg, 1848 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1870 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1840 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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H A D | ARMISelDAGToDAG.cpp | 2468 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2469 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; 2731 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2732 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2751 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2752 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2770 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2771 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg(); local 501 MachineInstr *CondI = MRI->getVRegDef(PredReg);
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