Searched refs:RADEON_PP_TEX_SIZE_0 (Results 1 - 14 of 14) sorted by relevance

/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_blit.c165 OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0, ((width - 1) |
H A Dradeon_sanity.c136 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
245 { RADEON_PP_TEX_SIZE_0, "RADEON_PP_TEX_SIZE_0" },
248 { RADEON_PP_TEX_SIZE_0+4, "RADEON_PP_TEX_PITCH_0" },
H A Dradeon_state_init.c134 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_blit.c165 OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0, ((width - 1) |
H A Dradeon_sanity.c136 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
245 { RADEON_PP_TEX_SIZE_0, "RADEON_PP_TEX_SIZE_0" },
248 { RADEON_PP_TEX_SIZE_0+4, "RADEON_PP_TEX_PITCH_0" },
H A Dradeon_state_init.c134 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
H A Dr200_sanity.c140 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
H A Dr200_state_init.c139 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_sanity.c140 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
H A Dr200_state_init.c139 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/server/
H A Dradeon_reg.h1356 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ macro
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/server/
H A Dradeon_reg.h1356 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ macro
/external/mesa3d/src/mesa/drivers/dri/r200/server/
H A Dradeon_reg.h1356 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ macro
/external/mesa3d/src/mesa/drivers/dri/radeon/server/
H A Dradeon_reg.h1356 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ macro

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