Searched refs:RD2 (Results 1 - 6 of 6) sorted by relevance
/external/chromium_org/net/http/ |
H A D | md4.cc | 71 #define RD2(a,b,c,d,k,s) a += G(b,c,d) + X[k] + 0x5A827999; a = ROTL(a,s) macro 129 RD2(A,B,C,D, 0,3); RD2(D,A,B,C, 4,5); RD2(C,D,A,B, 8, 9); RD2(B,C,D,A,12,13); 130 RD2(A,B,C,D, 1,3); RD2(D,A,B,C, 5,5); RD2(C,D,A,B, 9, 9); RD2(B,C,D,A,13,13); 131 RD2( [all...] |
/external/valgrind/main/none/tests/arm/ |
H A D | vfp.c | 113 #define TESTINSN_vmov_2core_2single(instruction, RD1, RD2, SN, SM, SNval, SMval) \ 122 "mov " #RD2 ", #0x4\n\t" \ 125 "str " #RD2 ", [%0, #+4]\n\t" \ 128 : #RD1, #RD2, #SN, #SM, "memory" \ 130 printf("%s :: "#RD1" 0x%08x "#RD2" 0x%08x\n", \ 173 #define TESTINSN_vmov_2core_double(instruction, RD1, RD2, DN, DNval0, DNval1) \ 180 "mov " #RD2 ", #55\n\t" \ 184 "str " #RD2 ", [%0, #+4]\n\t" \ 187 : #DN, #RD1, #RD2, "memory" \ 189 printf("%s :: "#RD1" 0x%08x "#RD2" [all...] |
H A D | v6intARM.c | 100 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ 111 "mov " #RD2 ",%4;" \ 116 "mov %1," #RD2 ";" \ 120 : #RD, #RD2, #RM, #RS, "cc", "memory" \
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H A D | v6intThumb.c | 190 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \ 199 "mov " #RD2 ",%4;" \ 204 "mov %1," #RD2 ";" \ 208 : #RD, #RD2, #RM, #RS, "cc", "memory" \ 298 #define TESTINSTPCMISALIGNED_2OUT(instruction, RD, RD2, label, cvin) \ 307 "mov " #RD2 ", #0;" \ 322 "mov %1, " #RD2 ";" \ 326 : #RD, #RD2, "cc", "memory" \
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H A D | v6media.c | 109 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ 118 "mov " #RD2 ",%4;" \ 123 "mov %1," #RD2 ";" \ 127 : #RD, #RD2, #RM, #RS, "cc", "memory" \
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 2848 unsigned RD2 = RegInfo.createVirtualRegister(RC); local 2849 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) 2855 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
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