Searched refs:R_CS (Results 1 - 13 of 13) sorted by relevance

/external/qemu/target-i386/
H A Dseg_helper.c142 if (seg_reg == R_CS) {
173 if (seg_reg == R_SS || seg_reg == R_CS)
369 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
401 tss_load_seg(env, R_CS, new_segs[R_CS]);
410 if (new_eip > env->segs[R_CS].limit) {
636 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
653 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
674 cpu_x86_load_seg_cache(env, R_CS, selector,
810 PUSHQ(esp, env->segs[R_CS]
[all...]
H A Dhax-all.c729 get_seg(&env->segs[R_CS], &sregs->_cs);
748 set_v8086_seg(&sregs->_cs, &env->segs[R_CS]);
755 set_seg(&sregs->_cs, &env->segs[R_CS]);
794 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
806 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
809 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
H A Dkvm.c398 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
405 set_seg(&sregs.cs, &env->segs[R_CS]);
513 get_seg(&env->segs[R_CS], &sregs.cs);
546 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
558 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
561 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
H A Dcpu.h73 #define R_CS 1 macro
890 if (seg_reg == R_CS) {
900 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1126 *cs_base = env->segs[R_CS].base;
H A Dsvm_helper.c146 &env->segs[R_CS]);
203 env, R_CS);
505 &env->segs[R_CS]);
567 env, R_CS);
H A Dsmm_helper.c161 cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
H A Dhelper.c499 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
H A Dtranslate.c2559 call this function with seg_reg == R_CS */
4312 s->override = R_CS;
4367 s->override = R_CS;
4869 gen_op_movl_seg_T0_vm(R_CS);
5311 if (reg >= 6 || reg == R_CS)
6400 gen_op_movl_seg_T0_vm(R_CS);
/external/qemu/
H A Dgdbstub.c541 case 2: GET_REG32(env->segs[R_CS].selector);
600 case 2: LOAD_SEG(10, R_CS); return 4;
H A Dtranslate-all.c1165 (intptr_t)cpu_single_env->segs[R_CS].base);
/external/qemu/hw/intc/
H A Dapic.c505 cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12,
/external/valgrind/main/VEX/priv/
H A Dguest_x86_toIR.c305 #define R_CS 1 macro
488 case R_CS: return OFFB_CS;
1294 case R_CS: return "%cs";
13053 putSReg( R_CS, unop(Iop_32to16, mkexpr(t3)) );
14120 dis_push_segreg( R_CS, sz ); break;
H A Dguest_amd64_toIR.c466 #define R_CS 1 macro
2153 //.. case R_CS: return "%cs";
[all...]

Completed in 1364 milliseconds