Searched refs:R_SS (Results 1 - 11 of 11) sorted by relevance

/external/qemu/target-i386/
H A Dseg_helper.c150 } else if (seg_reg == R_SS) {
173 if (seg_reg == R_SS || seg_reg == R_CS)
402 tss_load_seg(env, R_SS, new_segs[R_SS]);
533 if (env->segs[R_SS].flags & DESC_B_MASK)
538 ssp = env->segs[R_SS].base + esp;
603 sp_mask = get_sp_mask(env->segs[R_SS].flags);
604 ssp = env->segs[R_SS].base;
632 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
649 PUSHW(ssp, esp, sp_mask, env->segs[R_SS]
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H A Dhax-all.c734 get_seg(&env->segs[R_SS], &sregs->_ss);
753 set_v8086_seg(&sregs->_ss, &env->segs[R_SS]);
760 set_seg(&sregs->_ss, &env->segs[R_SS]);
811 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
820 env->segs[R_SS].base) != 0) <<
H A Dkvm.c403 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
410 set_seg(&sregs.ss, &env->segs[R_SS]);
518 get_seg(&env->segs[R_SS], &sregs.ss);
563 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
572 env->segs[R_SS].base) != 0) <<
H A Dsvm_helper.c148 &env->segs[R_SS]);
205 env, R_SS);
507 &env->segs[R_SS]);
569 env, R_SS);
H A Dcpu.h74 #define R_SS 2 macro
906 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
922 env->segs[R_SS].base) != 0) <<
H A Dsmm_helper.c165 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
H A Dtranslate.c2240 override = R_SS;
2313 override = R_SS;
2569 because ss32 may change. For R_SS, translation must always
2572 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2576 if (seg_reg == R_SS)
2644 gen_op_addl_A0_seg(s, R_SS);
2649 gen_op_addl_A0_seg(s, R_SS);
2684 gen_op_addl_A0_seg(s, R_SS);
2688 gen_op_addl_A0_seg(s, R_SS);
2712 gen_op_addl_A0_seg(s, R_SS);
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H A Dhelper.c508 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
/external/qemu/
H A Dgdbstub.c542 case 3: GET_REG32(env->segs[R_SS].selector);
601 case 3: LOAD_SEG(11, R_SS); return 4;
/external/valgrind/main/VEX/priv/
H A Dguest_x86_toIR.c306 #define R_SS 2 macro
489 case R_SS: return OFFB_SS;
1295 case R_SS: return "%ss";
13985 dis_pop_segreg( R_SS, sz ); break;
14126 dis_push_segreg( R_SS, sz ); break;
H A Dguest_amd64_toIR.c467 #define R_SS 2 macro
2154 //.. case R_SS: return "%ss";
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