/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.h | 27 const NVPTXRegisterInfo RegInfo; member in class:llvm::NVPTXInstrInfo 32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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H A D | NVPTXPrologEpilogPass.cpp | 112 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); local 212 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
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H A D | NVPTXInstrInfo.cpp | 33 : NVPTXGenInstrInfo(), RegInfo(STI) {}
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 56 const Thumb1RegisterInfo *RegInfo = local 75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 92 const Thumb1RegisterInfo *RegInfo = local 104 unsigned FramePtr = RegInfo->getFrameRegister(MF); 105 unsigned BasePtr = RegInfo->getBaseRegister(); 118 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 129 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), 260 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 281 if (RegInfo 324 const Thumb1RegisterInfo *RegInfo = local [all...] |
H A D | ARMFrameLowering.cpp | 50 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local 60 RegInfo->needsStackRealignment(MF) || 166 const ARMBaseRegisterInfo *RegInfo = local 178 unsigned FramePtr = RegInfo->getFrameRegister(MF); 516 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { 550 if (RegInfo->hasBasePointer(MF)) { 553 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 558 RegInfo->getBaseRegister()) 577 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local 587 unsigned FramePtr = RegInfo 720 const ARMBaseRegisterInfo *RegInfo = local 1347 const ARMBaseRegisterInfo *RegInfo = local 1387 const ARMBaseRegisterInfo *RegInfo = local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 131 const MipsRegisterInfo &RegInfo = local 134 const TargetRegisterClass *RC = RegInfo.intRegClass(4); 138 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); 151 const MipsRegisterInfo &RegInfo = local 154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); 160 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); 174 const MipsRegisterInfo &RegInfo = local 177 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); 181 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); 182 unsigned Hi = RegInfo 204 const MipsRegisterInfo &RegInfo = local 239 const MipsRegisterInfo &RegInfo = local 282 const MipsRegisterInfo &RegInfo = local 401 const MipsRegisterInfo &RegInfo = local [all...] |
H A D | MipsSERegisterInfo.cpp | 171 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); local 172 unsigned Reg = RegInfo.createVirtualRegister(RC);
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H A D | Mips16ISelDAGToDAG.cpp | 73 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 80 V0 = RegInfo.createVirtualRegister(RC); 81 V1 = RegInfo.createVirtualRegister(RC); 82 V2 = RegInfo.createVirtualRegister(RC);
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H A D | MipsISelLowering.cpp | 960 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 991 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 992 unsigned AndRes = RegInfo.createVirtualRegister(RC); 993 unsigned Success = RegInfo.createVirtualRegister(RC); 1059 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 1061 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1079 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 1088 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1089 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1090 unsigned Mask = RegInfo 1229 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 1311 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 1450 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local [all...] |
H A D | MipsSEISelLowering.cpp | 2746 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 2775 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2781 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2811 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 2842 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2848 unsigned RD2 = RegInfo.createVirtualRegister(RC); 2874 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 2883 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2908 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 2917 unsigned Wt = RegInfo 2937 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 2971 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 3019 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 3129 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 3160 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 3188 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local 3217 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 49 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local 52 RegInfo->needsStackRealignment(MF) || 442 const X86RegisterInfo *RegInfo = 462 unsigned SlotSize = RegInfo->getSlotSize(); 463 unsigned FramePtr = RegInfo->getFrameRegister(MF); 464 unsigned StackPtr = RegInfo->getStackRegister(); 465 unsigned BasePtr = RegInfo->getBaseRegister(); 492 !RegInfo->needsStackRealignment(MF) && 538 if (RegInfo->needsStackRealignment(MF)) { 567 unsigned DwarfFramePtr = RegInfo [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 89 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local 90 assert(!RegInfo->needsStackRealignment(MF) && 207 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( local 299 if (RegInfo->hasBasePointer(MF)) 305 unsigned FramePtr = RegInfo->getFrameRegister(MF); 375 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true); 382 unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true); 439 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( local 496 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); 550 const AArch64RegisterInfo *RegInfo local 763 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( local [all...] |
H A D | AArch64CleanupLocalDynamicTLSPass.cpp | 120 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 121 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
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/external/llvm/lib/CodeGen/ |
H A D | MachineFunction.cpp | 59 RegInfo = new (Allocator) MachineRegisterInfo(TM); 61 RegInfo = nullptr; 96 if (RegInfo) { 97 RegInfo->~MachineRegisterInfo(); 98 Allocator.Deallocate(RegInfo); 336 if (RegInfo) { 337 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA"); 338 if (!RegInfo->tracksLiveness()) 355 if (RegInfo && !RegInfo 629 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local [all...] |
H A D | MachineInstr.cpp | 131 MachineRegisterInfo *RegInfo = nullptr; local 135 RegInfo = &MF->getRegInfo(); 139 if (RegInfo && WasReg) 140 RegInfo->removeRegOperandFromUseList(this); 162 if (RegInfo) 163 RegInfo->addRegOperandToUseList(this); 1270 const TargetRegisterInfo &RegInfo) { 1273 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1278 MO.substPhysReg(ToReg, RegInfo); 1285 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1267 substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) argument 1684 addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound) argument 1743 clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo) argument 1757 addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound) argument 1809 addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo) argument [all...] |
H A D | PrologEpilogInserter.cpp | 242 const TargetRegisterInfo *RegInfo = F.getTarget().getRegisterInfo(); local 247 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F); 271 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) { 286 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); 289 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) { 518 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); local 521 RegInfo->useFPForScavengingIndex(Fn) && 522 !RegInfo->needsStackRealignment(Fn)); 650 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 359 const MCRegisterInfo *RegInfo; member in struct:__anon25200::MipsOperand::RegIdxOp 383 const MCRegisterInfo *RegInfo, 388 Op->RegIdx.RegInfo = RegInfo; 402 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 410 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 420 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID) 428 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) 436 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID) 444 return RegIdx.RegInfo 382 CreateReg(unsigned Index, RegKind RegKind, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 736 CreateNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 745 CreateGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 753 CreateFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 761 CreateFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 769 CreateACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 777 CreateMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 785 CreateMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineFunction.h | 82 // RegInfo - Information about each register in use in the function. 83 MachineRegisterInfo *RegInfo; member in class:llvm::MachineFunction 167 MachineRegisterInfo &getRegInfo() { return *RegInfo; } 168 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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H A D | MachineInstr.h | 972 const TargetRegisterInfo &RegInfo); 979 const TargetRegisterInfo *RegInfo, 982 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is 984 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo); 990 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, 996 const TargetRegisterInfo *RegInfo = nullptr);
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H A D | FunctionLoweringInfo.h | 57 MachineRegisterInfo *RegInfo; member in class:llvm::FunctionLoweringInfo
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H A D | SelectionDAGISel.h | 47 MachineRegisterInfo *RegInfo; member in class:llvm::SelectionDAGISel
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 374 const PPCRegisterInfo *RegInfo = local 391 !RegInfo->hasBasePointer(MF)) { // No special alignment. 461 const PPCRegisterInfo *RegInfo = local 463 bool HasBP = RegInfo->hasBasePointer(MF); 501 const PPCRegisterInfo *RegInfo = local 546 bool HasBP = RegInfo->hasBasePointer(MF); 816 const PPCRegisterInfo *RegInfo = local 849 bool HasBP = RegInfo->hasBasePointer(MF); 1056 const PPCRegisterInfo *RegInfo = local 1061 unsigned LR = RegInfo 1222 const PPCRegisterInfo *RegInfo = local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 803 const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); local 805 RegInfo->getFrameRegister(MF), MVT::i32); 849 const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); local 851 RegInfo->getFrameRegister(MF), MVT::i32); 1282 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 1329 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1330 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1382 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1383 RegInfo.addLiveIn(ArgRegs[i], VReg);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 64 RegInfo = &MF->getRegInfo(); 248 return RegInfo->
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 435 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 439 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
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