Searched refs:isPredicated (Results 1 - 25 of 38) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp207 if(!isPredicated(LastInst)) {
231 isPredicated(SecondLastInst) &&
233 !isPredicated(LastInst)) {
314 if (isPredicated(I)) {
332 if (isPredicated(I)) {
343 R600InstrInfo::isPredicated(const MachineInstr *MI) const function in class:R600InstrInfo
H A DR600InstrInfo.h75 bool isPredicated(const MachineInstr *MI) const;
H A DAMDGPUInstrInfo.cpp209 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:AMDGPUInstrInfo
H A DAMDGPUInstrInfo.h116 bool isPredicated(const MachineInstr *MI) const;
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp207 if(!isPredicated(LastInst)) {
231 isPredicated(SecondLastInst) &&
233 !isPredicated(LastInst)) {
314 if (isPredicated(I)) {
332 if (isPredicated(I)) {
343 R600InstrInfo::isPredicated(const MachineInstr *MI) const function in class:R600InstrInfo
H A DR600InstrInfo.h75 bool isPredicated(const MachineInstr *MI) const;
H A DAMDGPUInstrInfo.cpp209 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:AMDGPUInstrInfo
H A DAMDGPUInstrInfo.h116 bool isPredicated(const MachineInstr *MI) const;
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h134 bool isPredicated(const MachineInstr *MI) const override;
135 bool isPredicated(unsigned Opcode) const;
H A DHexagonVLIWPacketizer.cpp466 if (!QII->isPredicated(MI))
600 if (QII->isPredicated(PacketMI)) {
601 if (!QII->isPredicated(MI))
817 if(!QII->isPredicated(*VIN)) continue;
847 assert(QII->isPredicated(MI) && "Must be predicated instruction");
1203 else if (QII->isPredicated(I) &&
1204 QII->isPredicated(J) &&
H A DHexagonInstrInfo.cpp150 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
982 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:HexagonInstrInfo
988 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { function in class:HexagonInstrInfo
997 assert(isPredicated(MI));
1014 assert(isPredicated(MI));
1021 assert(isPredicated(Opcode));
1525 (isPredicated(MI) && isPredicatedNew(MI)));
1539 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
H A DHexagonPeephole.cpp247 if (QII->isPredicated(MI)) {
H A DHexagonNewValueJump.cpp116 if (QII->isPredicated(II))
/external/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.h131 bool isPredicated(const MachineInstr *MI) const override;
H A DAMDGPUInstrInfo.cpp240 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:AMDGPUInstrInfo
H A DR600InstrInfo.h170 bool isPredicated(const MachineInstr *MI) const override;
/external/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp173 TII->isPredicated(MI);
249 if (!TII->isPredicated(MI)) {
612 if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI))
H A DTargetSchedule.cpp272 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
H A DIfConversion.cpp677 bool isPredicated = TII->isPredicated(I); local
684 if (!isPredicated) {
699 if (BBI.ClobbersPred && !isPredicated) {
1534 if (I->isDebugValue() || TII->isPredicated(I))
1590 if (!TII->isPredicated(I) && !MI->isDebugValue()) {
H A DRegisterScavenging.cpp124 bool isPred = TII->isPredicated(MI);
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h200 bool isPredicated(const MachineInstr *MI) const override;
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp169 return !isPredicated(MI);
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp290 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
323 CantAnalyze = !isPredicated(I);
331 if (!isPredicated(I) &&
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:ARMBaseInstrInfo
2264 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2272 isPredicated(PotentialAND))
2339 if (isPredicated(MI))
2475 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
3975 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3980 if (Subtarget.isCortexA9() && !isPredicated(M
[all...]
H A DARMBaseInstrInfo.h75 bool isPredicated(const MachineInstr *MI) const override;
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h686 /// isPredicated - Returns true if the instruction is already predicated.
688 virtual bool isPredicated(const MachineInstr *MI) const { function in class:llvm::TargetInstrInfo

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