Searched refs:lwr (Results 1 - 25 of 41) sorted by relevance

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/external/llvm/test/MC/Mips/
H A Dmicromips-loadstore-unaligned.s13 # CHECK-EL: lwr $4, 16($5) # encoding: [0x85,0x60,0x10,0x10]
20 # CHECK-EB: lwr $4, 16($5) # encoding: [0x60,0x85,0x10,0x10]
24 lwr $4, 16($5)
H A Dnacl-mask.s53 lwr $4, 0($10)
94 # CHECK-NEXT: lwr $4, 0($10)
/external/chromium_org/v8/src/mips/
H A Dcodegen-mips.cc135 __ lwr(t8, MemOperand(a1));
297 __ lwr(v1, MemOperand(a1));
305 __ lwr(v1,
340 __ lwr(t0, MemOperand(a1));
341 __ lwr(t1, MemOperand(a1, 1, loadstore_chunk));
342 __ lwr(t2, MemOperand(a1, 2, loadstore_chunk));
348 __ lwr(t3, MemOperand(a1, 3, loadstore_chunk)); // Maybe in delay slot.
354 __ lwr(t4, MemOperand(a1, 4, loadstore_chunk));
355 __ lwr(t5, MemOperand(a1, 5, loadstore_chunk));
356 __ lwr(t
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H A Ddisasm-mips.cc877 Format(instr, "lwr 'rt, 'imm16s('rs)");
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips1-wrong-error.s11 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips1-wrong-error.s11 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
H A Dinvalid-mips3-wrong-error.s17 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/chromium_org/third_party/openssl/openssl/crypto/sha/asm/
H A Dsha1-mips.S41 lwr $8,0($5)
55 lwr $9,1*4+0($5)
79 lwr $10,2*4+0($5)
103 lwr $11,3*4+0($5)
127 lwr $12,4*4+0($5)
151 lwr $13,5*4+0($5)
175 lwr $14,6*4+0($5)
199 lwr $15,7*4+0($5)
223 lwr $16,8*4+0($5)
247 lwr
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H A Dsha256-mips.S50 lwr $8,0($5)
52 lwr $9,4($5)
104 lwr $10,8($5)
156 lwr $11,12($5)
208 lwr $12,16($5)
260 lwr $13,20($5)
312 lwr $14,24($5)
364 lwr $15,28($5)
416 lwr $16,32($5)
468 lwr
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H A Dsha1-mips.pl13 # to deploy lwl/lwr pair to load unaligned input. One could have
112 lwr @X[$j],$j*4+$LSB($inp)
289 lwr @X[0],$LSB($inp)
/external/openssl/crypto/sha/asm/
H A Dsha1-mips.S41 lwr $8,0($5)
55 lwr $9,1*4+0($5)
79 lwr $10,2*4+0($5)
103 lwr $11,3*4+0($5)
127 lwr $12,4*4+0($5)
151 lwr $13,5*4+0($5)
175 lwr $14,6*4+0($5)
199 lwr $15,7*4+0($5)
223 lwr $16,8*4+0($5)
247 lwr
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H A Dsha256-mips.S50 lwr $8,0($5)
52 lwr $9,4($5)
104 lwr $10,8($5)
156 lwr $11,12($5)
208 lwr $12,16($5)
260 lwr $13,20($5)
312 lwr $14,24($5)
364 lwr $15,28($5)
416 lwr $16,32($5)
468 lwr
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H A Dsha1-mips.pl13 # to deploy lwl/lwr pair to load unaligned input. One could have
112 lwr @X[$j],$j*4+$LSB($inp)
289 lwr @X[0],$LSB($inp)
/external/chromium_org/third_party/openssl/openssl/crypto/aes/asm/
H A Daes-mips.S45 lwr $12,3($1) # Te1[s1>>16]
46 lwr $13,3($2) # Te1[s2>>16]
47 lwr $14,3($24) # Te1[s3>>16]
48 lwr $15,3($25) # Te1[s0>>16]
66 lwr $16,2($1) # Te2[s2>>8]
67 lwr $17,2($2) # Te2[s3>>8]
68 lwr $18,2($24) # Te2[s0>>8]
69 lwr $19,2($25) # Te2[s1>>8]
87 lwr $20,1($1) # Te3[s3]
88 lwr
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H A Daes-mips.pl18 # additional rotations. Rotations are implemented with lwl/lwr pairs,
146 lwr $t0,2($i0) # Te1[s1>>16]
147 lwr $t1,2($i1) # Te1[s2>>16]
148 lwr $t2,2($i2) # Te1[s3>>16]
149 lwr $t3,2($i3) # Te1[s0>>16]
167 lwr $t4,1($i0) # Te2[s2>>8]
168 lwr $t5,1($i1) # Te2[s3>>8]
169 lwr $t6,1($i2) # Te2[s0>>8]
170 lwr $t7,1($i3) # Te2[s1>>8]
188 lwr
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/external/openssl/crypto/aes/asm/
H A Daes-mips.S45 lwr $12,3($1) # Te1[s1>>16]
46 lwr $13,3($2) # Te1[s2>>16]
47 lwr $14,3($24) # Te1[s3>>16]
48 lwr $15,3($25) # Te1[s0>>16]
66 lwr $16,2($1) # Te2[s2>>8]
67 lwr $17,2($2) # Te2[s3>>8]
68 lwr $18,2($24) # Te2[s0>>8]
69 lwr $19,2($25) # Te2[s1>>8]
87 lwr $20,1($1) # Te3[s3]
88 lwr
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H A Daes-mips.pl18 # additional rotations. Rotations are implemented with lwl/lwr pairs,
146 lwr $t0,2($i0) # Te1[s1>>16]
147 lwr $t1,2($i1) # Te1[s2>>16]
148 lwr $t2,2($i2) # Te1[s3>>16]
149 lwr $t3,2($i3) # Te1[s0>>16]
167 lwr $t4,1($i0) # Te2[s2>>8]
168 lwr $t5,1($i1) # Te2[s3>>8]
169 lwr $t6,1($i2) # Te2[s0>>8]
170 lwr $t7,1($i3) # Te2[s1>>8]
188 lwr
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/external/chromium_org/third_party/sqlite/src/tool/
H A Dmkspeedsql.tcl93 set lwr [expr {$i*100}]
95 puts "SELECT count(*), avg(b) FROM t1 WHERE b>=$lwr AND b<$upr;"
120 set lwr [expr {$i*100}]
122 puts "SELECT count(*), avg(b) FROM t1 WHERE b>=$lwr AND b<$upr;"
156 set lwr [expr {$i*2}]
158 puts "UPDATE t1 SET b=b*2 WHERE a>=$lwr AND a<$upr;"
H A Dspeedtest.tcl154 set lwr [expr {$i*100}]
156 puts $fd "SELECT count(*), avg(b) FROM t2 WHERE b>=$lwr AND b<$upr;"
182 set lwr [expr {$i*100}]
184 puts $fd "SELECT count(*), avg(b) FROM t2 WHERE b>=$lwr AND b<$upr;"
194 set lwr [expr {$i*10}]
196 puts $fd "UPDATE t1 SET b=b*2 WHERE a>=$lwr AND a<$upr;"
/external/pixman/pixman/
H A Dpixman-mips-memcpy-asm.S40 # define LWLO lwr /* low part is right in big-endian */
43 # define LWHI lwr /* high part is right in little-endian */
/external/llvm/test/MC/Mips/mips1/
H A Dvalid.s52 lwr $zero,-19147($gp)
/external/llvm/test/MC/Mips/mips2/
H A Dvalid.s60 lwr $zero,-19147($gp)
/external/llvm/test/MC/Mips/mips32/
H A Dvalid.s65 lwr $zero,-19147($gp)
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s74 lwr $zero,-19147($gp)
/external/chromium_org/third_party/sqlite/src/src/
H A Dbtree.c4448 int lwr, upr; local
4461 lwr = 0;
4466 pCur->aiIdx[pCur->iPage] = (u16)((upr+lwr)/2);
4537 lwr = idx;
4538 upr = lwr - 1;
4547 lwr = idx+1;
4551 if( lwr>upr ){
4554 pCur->aiIdx[pCur->iPage] = (u16)((lwr+upr)/2);
4556 assert( lwr==upr+1 );
4560 }else if( lwr>
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